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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[thirdparty/linux.git] / drivers / bus / ti-sysc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
19
20 #include <linux/platform_data/ti-sysc.h>
21
22 #include <dt-bindings/bus/ti-sysc.h>
23
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
25
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
27
28 enum sysc_clocks {
29 SYSC_FCK,
30 SYSC_ICK,
31 SYSC_OPTFCK0,
32 SYSC_OPTFCK1,
33 SYSC_OPTFCK2,
34 SYSC_OPTFCK3,
35 SYSC_OPTFCK4,
36 SYSC_OPTFCK5,
37 SYSC_OPTFCK6,
38 SYSC_OPTFCK7,
39 SYSC_MAX_CLOCKS,
40 };
41
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
45 };
46
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
49
50 /**
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
77 */
78 struct sysc {
79 struct device *dev;
80 u64 module_pa;
81 u32 module_size;
82 void __iomem *module_va;
83 int offsets[SYSC_MAX_REGS];
84 struct ti_sysc_module_data *mdata;
85 struct clk **clocks;
86 const char **clock_roles;
87 int nr_clocks;
88 struct reset_control *rsts;
89 const char *legacy_mode;
90 const struct sysc_capabilities *cap;
91 struct sysc_config cfg;
92 struct ti_sysc_cookie cookie;
93 const char *name;
94 u32 revision;
95 unsigned int enabled:1;
96 unsigned int needs_resume:1;
97 unsigned int child_needs_resume:1;
98 struct delayed_work idle_work;
99 void (*clk_enable_quirk)(struct sysc *sysc);
100 void (*clk_disable_quirk)(struct sysc *sysc);
101 void (*reset_done_quirk)(struct sysc *sysc);
102 void (*module_enable_quirk)(struct sysc *sysc);
103 };
104
105 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
106 bool is_child);
107
108 static void sysc_write(struct sysc *ddata, int offset, u32 value)
109 {
110 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
111 writew_relaxed(value & 0xffff, ddata->module_va + offset);
112
113 /* Only i2c revision has LO and HI register with stride of 4 */
114 if (ddata->offsets[SYSC_REVISION] >= 0 &&
115 offset == ddata->offsets[SYSC_REVISION]) {
116 u16 hi = value >> 16;
117
118 writew_relaxed(hi, ddata->module_va + offset + 4);
119 }
120
121 return;
122 }
123
124 writel_relaxed(value, ddata->module_va + offset);
125 }
126
127 static u32 sysc_read(struct sysc *ddata, int offset)
128 {
129 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
130 u32 val;
131
132 val = readw_relaxed(ddata->module_va + offset);
133
134 /* Only i2c revision has LO and HI register with stride of 4 */
135 if (ddata->offsets[SYSC_REVISION] >= 0 &&
136 offset == ddata->offsets[SYSC_REVISION]) {
137 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
138
139 val |= tmp << 16;
140 }
141
142 return val;
143 }
144
145 return readl_relaxed(ddata->module_va + offset);
146 }
147
148 static bool sysc_opt_clks_needed(struct sysc *ddata)
149 {
150 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
151 }
152
153 static u32 sysc_read_revision(struct sysc *ddata)
154 {
155 int offset = ddata->offsets[SYSC_REVISION];
156
157 if (offset < 0)
158 return 0;
159
160 return sysc_read(ddata, offset);
161 }
162
163 static u32 sysc_read_sysconfig(struct sysc *ddata)
164 {
165 int offset = ddata->offsets[SYSC_SYSCONFIG];
166
167 if (offset < 0)
168 return 0;
169
170 return sysc_read(ddata, offset);
171 }
172
173 static u32 sysc_read_sysstatus(struct sysc *ddata)
174 {
175 int offset = ddata->offsets[SYSC_SYSSTATUS];
176
177 if (offset < 0)
178 return 0;
179
180 return sysc_read(ddata, offset);
181 }
182
183 static int sysc_add_named_clock_from_child(struct sysc *ddata,
184 const char *name,
185 const char *optfck_name)
186 {
187 struct device_node *np = ddata->dev->of_node;
188 struct device_node *child;
189 struct clk_lookup *cl;
190 struct clk *clock;
191 const char *n;
192
193 if (name)
194 n = name;
195 else
196 n = optfck_name;
197
198 /* Does the clock alias already exist? */
199 clock = of_clk_get_by_name(np, n);
200 if (!IS_ERR(clock)) {
201 clk_put(clock);
202
203 return 0;
204 }
205
206 child = of_get_next_available_child(np, NULL);
207 if (!child)
208 return -ENODEV;
209
210 clock = devm_get_clk_from_child(ddata->dev, child, name);
211 if (IS_ERR(clock))
212 return PTR_ERR(clock);
213
214 /*
215 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
216 * limit for clk_get(). If cl ever needs to be freed, it should be done
217 * with clkdev_drop().
218 */
219 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
220 if (!cl)
221 return -ENOMEM;
222
223 cl->con_id = n;
224 cl->dev_id = dev_name(ddata->dev);
225 cl->clk = clock;
226 clkdev_add(cl);
227
228 clk_put(clock);
229
230 return 0;
231 }
232
233 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
234 {
235 const char *optfck_name;
236 int error, index;
237
238 if (ddata->nr_clocks < SYSC_OPTFCK0)
239 index = SYSC_OPTFCK0;
240 else
241 index = ddata->nr_clocks;
242
243 if (name)
244 optfck_name = name;
245 else
246 optfck_name = clock_names[index];
247
248 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
249 if (error)
250 return error;
251
252 ddata->clock_roles[index] = optfck_name;
253 ddata->nr_clocks++;
254
255 return 0;
256 }
257
258 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
259 {
260 int error, i, index = -ENODEV;
261
262 if (!strncmp(clock_names[SYSC_FCK], name, 3))
263 index = SYSC_FCK;
264 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
265 index = SYSC_ICK;
266
267 if (index < 0) {
268 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
269 if (!ddata->clocks[i]) {
270 index = i;
271 break;
272 }
273 }
274 }
275
276 if (index < 0) {
277 dev_err(ddata->dev, "clock %s not added\n", name);
278 return index;
279 }
280
281 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
282 if (IS_ERR(ddata->clocks[index])) {
283 dev_err(ddata->dev, "clock get error for %s: %li\n",
284 name, PTR_ERR(ddata->clocks[index]));
285
286 return PTR_ERR(ddata->clocks[index]);
287 }
288
289 error = clk_prepare(ddata->clocks[index]);
290 if (error) {
291 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
292 name, error);
293
294 return error;
295 }
296
297 return 0;
298 }
299
300 static int sysc_get_clocks(struct sysc *ddata)
301 {
302 struct device_node *np = ddata->dev->of_node;
303 struct property *prop;
304 const char *name;
305 int nr_fck = 0, nr_ick = 0, i, error = 0;
306
307 ddata->clock_roles = devm_kcalloc(ddata->dev,
308 SYSC_MAX_CLOCKS,
309 sizeof(*ddata->clock_roles),
310 GFP_KERNEL);
311 if (!ddata->clock_roles)
312 return -ENOMEM;
313
314 of_property_for_each_string(np, "clock-names", prop, name) {
315 if (!strncmp(clock_names[SYSC_FCK], name, 3))
316 nr_fck++;
317 if (!strncmp(clock_names[SYSC_ICK], name, 3))
318 nr_ick++;
319 ddata->clock_roles[ddata->nr_clocks] = name;
320 ddata->nr_clocks++;
321 }
322
323 if (ddata->nr_clocks < 1)
324 return 0;
325
326 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
327 error = sysc_init_ext_opt_clock(ddata, NULL);
328 if (error)
329 return error;
330 }
331
332 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
333 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
334
335 return -EINVAL;
336 }
337
338 if (nr_fck > 1 || nr_ick > 1) {
339 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
340
341 return -EINVAL;
342 }
343
344 ddata->clocks = devm_kcalloc(ddata->dev,
345 ddata->nr_clocks, sizeof(*ddata->clocks),
346 GFP_KERNEL);
347 if (!ddata->clocks)
348 return -ENOMEM;
349
350 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
351 const char *name = ddata->clock_roles[i];
352
353 if (!name)
354 continue;
355
356 error = sysc_get_one_clock(ddata, name);
357 if (error)
358 return error;
359 }
360
361 return 0;
362 }
363
364 static int sysc_enable_main_clocks(struct sysc *ddata)
365 {
366 struct clk *clock;
367 int i, error;
368
369 if (!ddata->clocks)
370 return 0;
371
372 for (i = 0; i < SYSC_OPTFCK0; i++) {
373 clock = ddata->clocks[i];
374
375 /* Main clocks may not have ick */
376 if (IS_ERR_OR_NULL(clock))
377 continue;
378
379 error = clk_enable(clock);
380 if (error)
381 goto err_disable;
382 }
383
384 return 0;
385
386 err_disable:
387 for (i--; i >= 0; i--) {
388 clock = ddata->clocks[i];
389
390 /* Main clocks may not have ick */
391 if (IS_ERR_OR_NULL(clock))
392 continue;
393
394 clk_disable(clock);
395 }
396
397 return error;
398 }
399
400 static void sysc_disable_main_clocks(struct sysc *ddata)
401 {
402 struct clk *clock;
403 int i;
404
405 if (!ddata->clocks)
406 return;
407
408 for (i = 0; i < SYSC_OPTFCK0; i++) {
409 clock = ddata->clocks[i];
410 if (IS_ERR_OR_NULL(clock))
411 continue;
412
413 clk_disable(clock);
414 }
415 }
416
417 static int sysc_enable_opt_clocks(struct sysc *ddata)
418 {
419 struct clk *clock;
420 int i, error;
421
422 if (!ddata->clocks)
423 return 0;
424
425 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
426 clock = ddata->clocks[i];
427
428 /* Assume no holes for opt clocks */
429 if (IS_ERR_OR_NULL(clock))
430 return 0;
431
432 error = clk_enable(clock);
433 if (error)
434 goto err_disable;
435 }
436
437 return 0;
438
439 err_disable:
440 for (i--; i >= 0; i--) {
441 clock = ddata->clocks[i];
442 if (IS_ERR_OR_NULL(clock))
443 continue;
444
445 clk_disable(clock);
446 }
447
448 return error;
449 }
450
451 static void sysc_disable_opt_clocks(struct sysc *ddata)
452 {
453 struct clk *clock;
454 int i;
455
456 if (!ddata->clocks)
457 return;
458
459 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
460 clock = ddata->clocks[i];
461
462 /* Assume no holes for opt clocks */
463 if (IS_ERR_OR_NULL(clock))
464 return;
465
466 clk_disable(clock);
467 }
468 }
469
470 static void sysc_clkdm_deny_idle(struct sysc *ddata)
471 {
472 struct ti_sysc_platform_data *pdata;
473
474 if (ddata->legacy_mode)
475 return;
476
477 pdata = dev_get_platdata(ddata->dev);
478 if (pdata && pdata->clkdm_deny_idle)
479 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
480 }
481
482 static void sysc_clkdm_allow_idle(struct sysc *ddata)
483 {
484 struct ti_sysc_platform_data *pdata;
485
486 if (ddata->legacy_mode)
487 return;
488
489 pdata = dev_get_platdata(ddata->dev);
490 if (pdata && pdata->clkdm_allow_idle)
491 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
492 }
493
494 /**
495 * sysc_init_resets - init rstctrl reset line if configured
496 * @ddata: device driver data
497 *
498 * See sysc_rstctrl_reset_deassert().
499 */
500 static int sysc_init_resets(struct sysc *ddata)
501 {
502 ddata->rsts =
503 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
504 if (IS_ERR(ddata->rsts))
505 return PTR_ERR(ddata->rsts);
506
507 return 0;
508 }
509
510 /**
511 * sysc_parse_and_check_child_range - parses module IO region from ranges
512 * @ddata: device driver data
513 *
514 * In general we only need rev, syss, and sysc registers and not the whole
515 * module range. But we do want the offsets for these registers from the
516 * module base. This allows us to check them against the legacy hwmod
517 * platform data. Let's also check the ranges are configured properly.
518 */
519 static int sysc_parse_and_check_child_range(struct sysc *ddata)
520 {
521 struct device_node *np = ddata->dev->of_node;
522 const __be32 *ranges;
523 u32 nr_addr, nr_size;
524 int len, error;
525
526 ranges = of_get_property(np, "ranges", &len);
527 if (!ranges) {
528 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
529
530 return -ENOENT;
531 }
532
533 len /= sizeof(*ranges);
534
535 if (len < 3) {
536 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
537
538 return -EINVAL;
539 }
540
541 error = of_property_read_u32(np, "#address-cells", &nr_addr);
542 if (error)
543 return -ENOENT;
544
545 error = of_property_read_u32(np, "#size-cells", &nr_size);
546 if (error)
547 return -ENOENT;
548
549 if (nr_addr != 1 || nr_size != 1) {
550 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
551
552 return -EINVAL;
553 }
554
555 ranges++;
556 ddata->module_pa = of_translate_address(np, ranges++);
557 ddata->module_size = be32_to_cpup(ranges);
558
559 return 0;
560 }
561
562 static struct device_node *stdout_path;
563
564 static void sysc_init_stdout_path(struct sysc *ddata)
565 {
566 struct device_node *np = NULL;
567 const char *uart;
568
569 if (IS_ERR(stdout_path))
570 return;
571
572 if (stdout_path)
573 return;
574
575 np = of_find_node_by_path("/chosen");
576 if (!np)
577 goto err;
578
579 uart = of_get_property(np, "stdout-path", NULL);
580 if (!uart)
581 goto err;
582
583 np = of_find_node_by_path(uart);
584 if (!np)
585 goto err;
586
587 stdout_path = np;
588
589 return;
590
591 err:
592 stdout_path = ERR_PTR(-ENODEV);
593 }
594
595 static void sysc_check_quirk_stdout(struct sysc *ddata,
596 struct device_node *np)
597 {
598 sysc_init_stdout_path(ddata);
599 if (np != stdout_path)
600 return;
601
602 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
603 SYSC_QUIRK_NO_RESET_ON_INIT;
604 }
605
606 /**
607 * sysc_check_one_child - check child configuration
608 * @ddata: device driver data
609 * @np: child device node
610 *
611 * Let's avoid messy situations where we have new interconnect target
612 * node but children have "ti,hwmods". These belong to the interconnect
613 * target node and are managed by this driver.
614 */
615 static void sysc_check_one_child(struct sysc *ddata,
616 struct device_node *np)
617 {
618 const char *name;
619
620 name = of_get_property(np, "ti,hwmods", NULL);
621 if (name)
622 dev_warn(ddata->dev, "really a child ti,hwmods property?");
623
624 sysc_check_quirk_stdout(ddata, np);
625 sysc_parse_dts_quirks(ddata, np, true);
626 }
627
628 static void sysc_check_children(struct sysc *ddata)
629 {
630 struct device_node *child;
631
632 for_each_child_of_node(ddata->dev->of_node, child)
633 sysc_check_one_child(ddata, child);
634 }
635
636 /*
637 * So far only I2C uses 16-bit read access with clockactivity with revision
638 * in two registers with stride of 4. We can detect this based on the rev
639 * register size to configure things far enough to be able to properly read
640 * the revision register.
641 */
642 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
643 {
644 if (resource_size(res) == 8)
645 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
646 }
647
648 /**
649 * sysc_parse_one - parses the interconnect target module registers
650 * @ddata: device driver data
651 * @reg: register to parse
652 */
653 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
654 {
655 struct resource *res;
656 const char *name;
657
658 switch (reg) {
659 case SYSC_REVISION:
660 case SYSC_SYSCONFIG:
661 case SYSC_SYSSTATUS:
662 name = reg_names[reg];
663 break;
664 default:
665 return -EINVAL;
666 }
667
668 res = platform_get_resource_byname(to_platform_device(ddata->dev),
669 IORESOURCE_MEM, name);
670 if (!res) {
671 ddata->offsets[reg] = -ENODEV;
672
673 return 0;
674 }
675
676 ddata->offsets[reg] = res->start - ddata->module_pa;
677 if (reg == SYSC_REVISION)
678 sysc_check_quirk_16bit(ddata, res);
679
680 return 0;
681 }
682
683 static int sysc_parse_registers(struct sysc *ddata)
684 {
685 int i, error;
686
687 for (i = 0; i < SYSC_MAX_REGS; i++) {
688 error = sysc_parse_one(ddata, i);
689 if (error)
690 return error;
691 }
692
693 return 0;
694 }
695
696 /**
697 * sysc_check_registers - check for misconfigured register overlaps
698 * @ddata: device driver data
699 */
700 static int sysc_check_registers(struct sysc *ddata)
701 {
702 int i, j, nr_regs = 0, nr_matches = 0;
703
704 for (i = 0; i < SYSC_MAX_REGS; i++) {
705 if (ddata->offsets[i] < 0)
706 continue;
707
708 if (ddata->offsets[i] > (ddata->module_size - 4)) {
709 dev_err(ddata->dev, "register outside module range");
710
711 return -EINVAL;
712 }
713
714 for (j = 0; j < SYSC_MAX_REGS; j++) {
715 if (ddata->offsets[j] < 0)
716 continue;
717
718 if (ddata->offsets[i] == ddata->offsets[j])
719 nr_matches++;
720 }
721 nr_regs++;
722 }
723
724 if (nr_matches > nr_regs) {
725 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
726 nr_regs, nr_matches);
727
728 return -EINVAL;
729 }
730
731 return 0;
732 }
733
734 /**
735 * syc_ioremap - ioremap register space for the interconnect target module
736 * @ddata: device driver data
737 *
738 * Note that the interconnect target module registers can be anywhere
739 * within the interconnect target module range. For example, SGX has
740 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
741 * has them at offset 0x1200 in the CPSW_WR child. Usually the
742 * the interconnect target module registers are at the beginning of
743 * the module range though.
744 */
745 static int sysc_ioremap(struct sysc *ddata)
746 {
747 int size;
748
749 if (ddata->offsets[SYSC_REVISION] < 0 &&
750 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
751 ddata->offsets[SYSC_SYSSTATUS] < 0) {
752 size = ddata->module_size;
753 } else {
754 size = max3(ddata->offsets[SYSC_REVISION],
755 ddata->offsets[SYSC_SYSCONFIG],
756 ddata->offsets[SYSC_SYSSTATUS]);
757
758 if (size < SZ_1K)
759 size = SZ_1K;
760
761 if ((size + sizeof(u32)) > ddata->module_size)
762 size = ddata->module_size;
763 }
764
765 ddata->module_va = devm_ioremap(ddata->dev,
766 ddata->module_pa,
767 size + sizeof(u32));
768 if (!ddata->module_va)
769 return -EIO;
770
771 return 0;
772 }
773
774 /**
775 * sysc_map_and_check_registers - ioremap and check device registers
776 * @ddata: device driver data
777 */
778 static int sysc_map_and_check_registers(struct sysc *ddata)
779 {
780 int error;
781
782 error = sysc_parse_and_check_child_range(ddata);
783 if (error)
784 return error;
785
786 sysc_check_children(ddata);
787
788 error = sysc_parse_registers(ddata);
789 if (error)
790 return error;
791
792 error = sysc_ioremap(ddata);
793 if (error)
794 return error;
795
796 error = sysc_check_registers(ddata);
797 if (error)
798 return error;
799
800 return 0;
801 }
802
803 /**
804 * sysc_show_rev - read and show interconnect target module revision
805 * @bufp: buffer to print the information to
806 * @ddata: device driver data
807 */
808 static int sysc_show_rev(char *bufp, struct sysc *ddata)
809 {
810 int len;
811
812 if (ddata->offsets[SYSC_REVISION] < 0)
813 return sprintf(bufp, ":NA");
814
815 len = sprintf(bufp, ":%08x", ddata->revision);
816
817 return len;
818 }
819
820 static int sysc_show_reg(struct sysc *ddata,
821 char *bufp, enum sysc_registers reg)
822 {
823 if (ddata->offsets[reg] < 0)
824 return sprintf(bufp, ":NA");
825
826 return sprintf(bufp, ":%x", ddata->offsets[reg]);
827 }
828
829 static int sysc_show_name(char *bufp, struct sysc *ddata)
830 {
831 if (!ddata->name)
832 return 0;
833
834 return sprintf(bufp, ":%s", ddata->name);
835 }
836
837 /**
838 * sysc_show_registers - show information about interconnect target module
839 * @ddata: device driver data
840 */
841 static void sysc_show_registers(struct sysc *ddata)
842 {
843 char buf[128];
844 char *bufp = buf;
845 int i;
846
847 for (i = 0; i < SYSC_MAX_REGS; i++)
848 bufp += sysc_show_reg(ddata, bufp, i);
849
850 bufp += sysc_show_rev(bufp, ddata);
851 bufp += sysc_show_name(bufp, ddata);
852
853 dev_dbg(ddata->dev, "%llx:%x%s\n",
854 ddata->module_pa, ddata->module_size,
855 buf);
856 }
857
858 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
859 #define SYSC_CLOCACT_ICK 2
860
861 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
862 static int sysc_enable_module(struct device *dev)
863 {
864 struct sysc *ddata;
865 const struct sysc_regbits *regbits;
866 u32 reg, idlemodes, best_mode;
867
868 ddata = dev_get_drvdata(dev);
869 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
870 return 0;
871
872 regbits = ddata->cap->regbits;
873 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
874
875 /* Set CLOCKACTIVITY, we only use it for ick */
876 if (regbits->clkact_shift >= 0 &&
877 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
878 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
879 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
880
881 /* Set SIDLE mode */
882 idlemodes = ddata->cfg.sidlemodes;
883 if (!idlemodes || regbits->sidle_shift < 0)
884 goto set_midle;
885
886 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
887 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
888 best_mode = SYSC_IDLE_NO;
889 } else {
890 best_mode = fls(ddata->cfg.sidlemodes) - 1;
891 if (best_mode > SYSC_IDLE_MASK) {
892 dev_err(dev, "%s: invalid sidlemode\n", __func__);
893 return -EINVAL;
894 }
895
896 /* Set WAKEUP */
897 if (regbits->enwkup_shift >= 0 &&
898 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
899 reg |= BIT(regbits->enwkup_shift);
900 }
901
902 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
903 reg |= best_mode << regbits->sidle_shift;
904 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
905
906 set_midle:
907 /* Set MIDLE mode */
908 idlemodes = ddata->cfg.midlemodes;
909 if (!idlemodes || regbits->midle_shift < 0)
910 goto set_autoidle;
911
912 best_mode = fls(ddata->cfg.midlemodes) - 1;
913 if (best_mode > SYSC_IDLE_MASK) {
914 dev_err(dev, "%s: invalid midlemode\n", __func__);
915 return -EINVAL;
916 }
917
918 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
919 reg |= best_mode << regbits->midle_shift;
920 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
921
922 set_autoidle:
923 /* Autoidle bit must enabled separately if available */
924 if (regbits->autoidle_shift >= 0 &&
925 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
926 reg |= 1 << regbits->autoidle_shift;
927 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
928 }
929
930 if (ddata->module_enable_quirk)
931 ddata->module_enable_quirk(ddata);
932
933 return 0;
934 }
935
936 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
937 {
938 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
939 *best_mode = SYSC_IDLE_SMART_WKUP;
940 else if (idlemodes & BIT(SYSC_IDLE_SMART))
941 *best_mode = SYSC_IDLE_SMART;
942 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
943 *best_mode = SYSC_IDLE_FORCE;
944 else
945 return -EINVAL;
946
947 return 0;
948 }
949
950 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
951 static int sysc_disable_module(struct device *dev)
952 {
953 struct sysc *ddata;
954 const struct sysc_regbits *regbits;
955 u32 reg, idlemodes, best_mode;
956 int ret;
957
958 ddata = dev_get_drvdata(dev);
959 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
960 return 0;
961
962 regbits = ddata->cap->regbits;
963 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
964
965 /* Set MIDLE mode */
966 idlemodes = ddata->cfg.midlemodes;
967 if (!idlemodes || regbits->midle_shift < 0)
968 goto set_sidle;
969
970 ret = sysc_best_idle_mode(idlemodes, &best_mode);
971 if (ret) {
972 dev_err(dev, "%s: invalid midlemode\n", __func__);
973 return ret;
974 }
975
976 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
977 reg |= best_mode << regbits->midle_shift;
978 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
979
980 set_sidle:
981 /* Set SIDLE mode */
982 idlemodes = ddata->cfg.sidlemodes;
983 if (!idlemodes || regbits->sidle_shift < 0)
984 return 0;
985
986 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
987 best_mode = SYSC_IDLE_FORCE;
988 } else {
989 ret = sysc_best_idle_mode(idlemodes, &best_mode);
990 if (ret) {
991 dev_err(dev, "%s: invalid sidlemode\n", __func__);
992 return ret;
993 }
994 }
995
996 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
997 reg |= best_mode << regbits->sidle_shift;
998 if (regbits->autoidle_shift >= 0 &&
999 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1000 reg |= 1 << regbits->autoidle_shift;
1001 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1002
1003 return 0;
1004 }
1005
1006 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1007 struct sysc *ddata)
1008 {
1009 struct ti_sysc_platform_data *pdata;
1010 int error;
1011
1012 pdata = dev_get_platdata(ddata->dev);
1013 if (!pdata)
1014 return 0;
1015
1016 if (!pdata->idle_module)
1017 return -ENODEV;
1018
1019 error = pdata->idle_module(dev, &ddata->cookie);
1020 if (error)
1021 dev_err(dev, "%s: could not idle: %i\n",
1022 __func__, error);
1023
1024 reset_control_assert(ddata->rsts);
1025
1026 return 0;
1027 }
1028
1029 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1030 struct sysc *ddata)
1031 {
1032 struct ti_sysc_platform_data *pdata;
1033 int error;
1034
1035 reset_control_deassert(ddata->rsts);
1036
1037 pdata = dev_get_platdata(ddata->dev);
1038 if (!pdata)
1039 return 0;
1040
1041 if (!pdata->enable_module)
1042 return -ENODEV;
1043
1044 error = pdata->enable_module(dev, &ddata->cookie);
1045 if (error)
1046 dev_err(dev, "%s: could not enable: %i\n",
1047 __func__, error);
1048
1049 return 0;
1050 }
1051
1052 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1053 {
1054 struct sysc *ddata;
1055 int error = 0;
1056
1057 ddata = dev_get_drvdata(dev);
1058
1059 if (!ddata->enabled)
1060 return 0;
1061
1062 sysc_clkdm_deny_idle(ddata);
1063
1064 if (ddata->legacy_mode) {
1065 error = sysc_runtime_suspend_legacy(dev, ddata);
1066 if (error)
1067 goto err_allow_idle;
1068 } else {
1069 error = sysc_disable_module(dev);
1070 if (error)
1071 goto err_allow_idle;
1072 }
1073
1074 sysc_disable_main_clocks(ddata);
1075
1076 if (sysc_opt_clks_needed(ddata))
1077 sysc_disable_opt_clocks(ddata);
1078
1079 ddata->enabled = false;
1080
1081 err_allow_idle:
1082 reset_control_assert(ddata->rsts);
1083
1084 sysc_clkdm_allow_idle(ddata);
1085
1086 return error;
1087 }
1088
1089 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1090 {
1091 struct sysc *ddata;
1092 int error = 0;
1093
1094 ddata = dev_get_drvdata(dev);
1095
1096 if (ddata->enabled)
1097 return 0;
1098
1099
1100 sysc_clkdm_deny_idle(ddata);
1101
1102 reset_control_deassert(ddata->rsts);
1103
1104 if (sysc_opt_clks_needed(ddata)) {
1105 error = sysc_enable_opt_clocks(ddata);
1106 if (error)
1107 goto err_allow_idle;
1108 }
1109
1110 error = sysc_enable_main_clocks(ddata);
1111 if (error)
1112 goto err_opt_clocks;
1113
1114 if (ddata->legacy_mode) {
1115 error = sysc_runtime_resume_legacy(dev, ddata);
1116 if (error)
1117 goto err_main_clocks;
1118 } else {
1119 error = sysc_enable_module(dev);
1120 if (error)
1121 goto err_main_clocks;
1122 }
1123
1124 ddata->enabled = true;
1125
1126 sysc_clkdm_allow_idle(ddata);
1127
1128 return 0;
1129
1130 err_main_clocks:
1131 sysc_disable_main_clocks(ddata);
1132 err_opt_clocks:
1133 if (sysc_opt_clks_needed(ddata))
1134 sysc_disable_opt_clocks(ddata);
1135 err_allow_idle:
1136 sysc_clkdm_allow_idle(ddata);
1137
1138 return error;
1139 }
1140
1141 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1142 {
1143 struct sysc *ddata;
1144
1145 ddata = dev_get_drvdata(dev);
1146
1147 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1148 return 0;
1149
1150 return pm_runtime_force_suspend(dev);
1151 }
1152
1153 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1154 {
1155 struct sysc *ddata;
1156
1157 ddata = dev_get_drvdata(dev);
1158
1159 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1160 return 0;
1161
1162 return pm_runtime_force_resume(dev);
1163 }
1164
1165 static const struct dev_pm_ops sysc_pm_ops = {
1166 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1167 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1168 sysc_runtime_resume,
1169 NULL)
1170 };
1171
1172 /* Module revision register based quirks */
1173 struct sysc_revision_quirk {
1174 const char *name;
1175 u32 base;
1176 int rev_offset;
1177 int sysc_offset;
1178 int syss_offset;
1179 u32 revision;
1180 u32 revision_mask;
1181 u32 quirks;
1182 };
1183
1184 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1185 optrev_val, optrevmask, optquirkmask) \
1186 { \
1187 .name = (optname), \
1188 .base = (optbase), \
1189 .rev_offset = (optrev), \
1190 .sysc_offset = (optsysc), \
1191 .syss_offset = (optsyss), \
1192 .revision = (optrev_val), \
1193 .revision_mask = (optrevmask), \
1194 .quirks = (optquirkmask), \
1195 }
1196
1197 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1198 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1199 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1200 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1201 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1202 SYSC_QUIRK_LEGACY_IDLE),
1203 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1204 SYSC_QUIRK_LEGACY_IDLE),
1205 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1206 SYSC_QUIRK_LEGACY_IDLE),
1207 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1208 SYSC_QUIRK_LEGACY_IDLE),
1209 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1210 SYSC_QUIRK_LEGACY_IDLE),
1211 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1212 0),
1213 /* Some timers on omap4 and later */
1214 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1215 0),
1216 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1217 0),
1218 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1219 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1220 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1221 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1222 /* Uarts on omap4 and later */
1223 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1224 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1225 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1226 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1227
1228 /* Quirks that need to be set based on the module address */
1229 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1230 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1231 SYSC_QUIRK_SWSUP_SIDLE),
1232
1233 /* Quirks that need to be set based on detected module */
1234 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1235 SYSC_MODULE_QUIRK_HDQ1W),
1236 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1237 SYSC_MODULE_QUIRK_HDQ1W),
1238 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1239 SYSC_MODULE_QUIRK_I2C),
1240 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1241 SYSC_MODULE_QUIRK_I2C),
1242 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1243 SYSC_MODULE_QUIRK_I2C),
1244 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1245 SYSC_MODULE_QUIRK_I2C),
1246 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1247 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1248 SYSC_MODULE_QUIRK_SGX),
1249 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1250 SYSC_MODULE_QUIRK_WDT),
1251
1252 #ifdef DEBUG
1253 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1254 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1255 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
1256 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1257 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1258 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1259 0xffff00f0, 0),
1260 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1261 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1262 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1263 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1264 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1265 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1266 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1267 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1268 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1269 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1270 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1271 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1272 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1273 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1274 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1275 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1276 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1277 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1278 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1279 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1280 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1281 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1282 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1283 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1284 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1285 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1286 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1287 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1288 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1289 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1290 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1291 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1292 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1293 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1294 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1295 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1296 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1297 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1298 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1299 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1300 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1301 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1302 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1303 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1304 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1305 0xffffffff, 0),
1306 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1307 #endif
1308 };
1309
1310 /*
1311 * Early quirks based on module base and register offsets only that are
1312 * needed before the module revision can be read
1313 */
1314 static void sysc_init_early_quirks(struct sysc *ddata)
1315 {
1316 const struct sysc_revision_quirk *q;
1317 int i;
1318
1319 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1320 q = &sysc_revision_quirks[i];
1321
1322 if (!q->base)
1323 continue;
1324
1325 if (q->base != ddata->module_pa)
1326 continue;
1327
1328 if (q->rev_offset >= 0 &&
1329 q->rev_offset != ddata->offsets[SYSC_REVISION])
1330 continue;
1331
1332 if (q->sysc_offset >= 0 &&
1333 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1334 continue;
1335
1336 if (q->syss_offset >= 0 &&
1337 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1338 continue;
1339
1340 ddata->name = q->name;
1341 ddata->cfg.quirks |= q->quirks;
1342 }
1343 }
1344
1345 /* Quirks that also consider the revision register value */
1346 static void sysc_init_revision_quirks(struct sysc *ddata)
1347 {
1348 const struct sysc_revision_quirk *q;
1349 int i;
1350
1351 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1352 q = &sysc_revision_quirks[i];
1353
1354 if (q->base && q->base != ddata->module_pa)
1355 continue;
1356
1357 if (q->rev_offset >= 0 &&
1358 q->rev_offset != ddata->offsets[SYSC_REVISION])
1359 continue;
1360
1361 if (q->sysc_offset >= 0 &&
1362 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1363 continue;
1364
1365 if (q->syss_offset >= 0 &&
1366 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1367 continue;
1368
1369 if (q->revision == ddata->revision ||
1370 (q->revision & q->revision_mask) ==
1371 (ddata->revision & q->revision_mask)) {
1372 ddata->name = q->name;
1373 ddata->cfg.quirks |= q->quirks;
1374 }
1375 }
1376 }
1377
1378 /* 1-wire needs module's internal clocks enabled for reset */
1379 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1380 {
1381 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1382 u16 val;
1383
1384 val = sysc_read(ddata, offset);
1385 val |= BIT(5);
1386 sysc_write(ddata, offset, val);
1387 }
1388
1389 /* I2C needs extra enable bit toggling for reset */
1390 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1391 {
1392 int offset;
1393 u16 val;
1394
1395 /* I2C_CON, omap2/3 is different from omap4 and later */
1396 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1397 offset = 0x24;
1398 else
1399 offset = 0xa4;
1400
1401 /* I2C_EN */
1402 val = sysc_read(ddata, offset);
1403 if (enable)
1404 val |= BIT(15);
1405 else
1406 val &= ~BIT(15);
1407 sysc_write(ddata, offset, val);
1408 }
1409
1410 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1411 {
1412 sysc_clk_quirk_i2c(ddata, true);
1413 }
1414
1415 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1416 {
1417 sysc_clk_quirk_i2c(ddata, false);
1418 }
1419
1420 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1421 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1422 {
1423 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1424 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1425
1426 sysc_write(ddata, offset, val);
1427 }
1428
1429 /* Watchdog timer needs a disable sequence after reset */
1430 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1431 {
1432 int wps, spr, error;
1433 u32 val;
1434
1435 wps = 0x34;
1436 spr = 0x48;
1437
1438 sysc_write(ddata, spr, 0xaaaa);
1439 error = readl_poll_timeout(ddata->module_va + wps, val,
1440 !(val & 0x10), 100,
1441 MAX_MODULE_SOFTRESET_WAIT);
1442 if (error)
1443 dev_warn(ddata->dev, "wdt disable spr failed\n");
1444
1445 sysc_write(ddata, wps, 0x5555);
1446 error = readl_poll_timeout(ddata->module_va + wps, val,
1447 !(val & 0x10), 100,
1448 MAX_MODULE_SOFTRESET_WAIT);
1449 if (error)
1450 dev_warn(ddata->dev, "wdt disable wps failed\n");
1451 }
1452
1453 static void sysc_init_module_quirks(struct sysc *ddata)
1454 {
1455 if (ddata->legacy_mode || !ddata->name)
1456 return;
1457
1458 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1459 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1460
1461 return;
1462 }
1463
1464 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1465 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1466 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1467
1468 return;
1469 }
1470
1471 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1472 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1473
1474 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT)
1475 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1476 }
1477
1478 static int sysc_clockdomain_init(struct sysc *ddata)
1479 {
1480 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1481 struct clk *fck = NULL, *ick = NULL;
1482 int error;
1483
1484 if (!pdata || !pdata->init_clockdomain)
1485 return 0;
1486
1487 switch (ddata->nr_clocks) {
1488 case 2:
1489 ick = ddata->clocks[SYSC_ICK];
1490 /* fallthrough */
1491 case 1:
1492 fck = ddata->clocks[SYSC_FCK];
1493 break;
1494 case 0:
1495 return 0;
1496 }
1497
1498 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1499 if (!error || error == -ENODEV)
1500 return 0;
1501
1502 return error;
1503 }
1504
1505 /*
1506 * Note that pdata->init_module() typically does a reset first. After
1507 * pdata->init_module() is done, PM runtime can be used for the interconnect
1508 * target module.
1509 */
1510 static int sysc_legacy_init(struct sysc *ddata)
1511 {
1512 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1513 int error;
1514
1515 if (!pdata || !pdata->init_module)
1516 return 0;
1517
1518 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1519 if (error == -EEXIST)
1520 error = 0;
1521
1522 return error;
1523 }
1524
1525 /**
1526 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1527 * @ddata: device driver data
1528 * @reset: reset before deassert
1529 *
1530 * A module can have both OCP softreset control and external rstctrl.
1531 * If more complicated rstctrl resets are needed, please handle these
1532 * directly from the child device driver and map only the module reset
1533 * for the parent interconnect target module device.
1534 *
1535 * Automatic reset of the module on init can be skipped with the
1536 * "ti,no-reset-on-init" device tree property.
1537 */
1538 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1539 {
1540 int error;
1541
1542 if (!ddata->rsts)
1543 return 0;
1544
1545 if (reset) {
1546 error = reset_control_assert(ddata->rsts);
1547 if (error)
1548 return error;
1549 }
1550
1551 reset_control_deassert(ddata->rsts);
1552
1553 return 0;
1554 }
1555
1556 /*
1557 * Note that the caller must ensure the interconnect target module is enabled
1558 * before calling reset. Otherwise reset will not complete.
1559 */
1560 static int sysc_reset(struct sysc *ddata)
1561 {
1562 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1563 u32 sysc_mask, syss_done;
1564
1565 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1566 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1567
1568 if (ddata->legacy_mode || sysc_offset < 0 ||
1569 ddata->cap->regbits->srst_shift < 0 ||
1570 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1571 return 0;
1572
1573 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1574
1575 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1576 syss_done = 0;
1577 else
1578 syss_done = ddata->cfg.syss_mask;
1579
1580 if (ddata->clk_disable_quirk)
1581 ddata->clk_disable_quirk(ddata);
1582
1583 sysc_val = sysc_read_sysconfig(ddata);
1584 sysc_val |= sysc_mask;
1585 sysc_write(ddata, sysc_offset, sysc_val);
1586
1587 if (ddata->clk_enable_quirk)
1588 ddata->clk_enable_quirk(ddata);
1589
1590 /* Poll on reset status */
1591 if (syss_offset >= 0) {
1592 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1593 (rstval & ddata->cfg.syss_mask) ==
1594 syss_done,
1595 100, MAX_MODULE_SOFTRESET_WAIT);
1596
1597 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1598 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1599 !(rstval & sysc_mask),
1600 100, MAX_MODULE_SOFTRESET_WAIT);
1601 }
1602
1603 if (ddata->reset_done_quirk)
1604 ddata->reset_done_quirk(ddata);
1605
1606 return error;
1607 }
1608
1609 /*
1610 * At this point the module is configured enough to read the revision but
1611 * module may not be completely configured yet to use PM runtime. Enable
1612 * all clocks directly during init to configure the quirks needed for PM
1613 * runtime based on the revision register.
1614 */
1615 static int sysc_init_module(struct sysc *ddata)
1616 {
1617 int error = 0;
1618 bool manage_clocks = true;
1619
1620 error = sysc_rstctrl_reset_deassert(ddata, false);
1621 if (error)
1622 return error;
1623
1624 if (ddata->cfg.quirks &
1625 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1626 manage_clocks = false;
1627
1628 error = sysc_clockdomain_init(ddata);
1629 if (error)
1630 return error;
1631
1632 sysc_clkdm_deny_idle(ddata);
1633
1634 /*
1635 * Always enable clocks. The bootloader may or may not have enabled
1636 * the related clocks.
1637 */
1638 error = sysc_enable_opt_clocks(ddata);
1639 if (error)
1640 return error;
1641
1642 error = sysc_enable_main_clocks(ddata);
1643 if (error)
1644 goto err_opt_clocks;
1645
1646 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1647 error = sysc_rstctrl_reset_deassert(ddata, true);
1648 if (error)
1649 goto err_main_clocks;
1650 }
1651
1652 ddata->revision = sysc_read_revision(ddata);
1653 sysc_init_revision_quirks(ddata);
1654 sysc_init_module_quirks(ddata);
1655
1656 if (ddata->legacy_mode) {
1657 error = sysc_legacy_init(ddata);
1658 if (error)
1659 goto err_main_clocks;
1660 }
1661
1662 if (!ddata->legacy_mode) {
1663 error = sysc_enable_module(ddata->dev);
1664 if (error)
1665 goto err_main_clocks;
1666 }
1667
1668 error = sysc_reset(ddata);
1669 if (error)
1670 dev_err(ddata->dev, "Reset failed with %d\n", error);
1671
1672 if (!ddata->legacy_mode && manage_clocks)
1673 sysc_disable_module(ddata->dev);
1674
1675 err_main_clocks:
1676 if (manage_clocks)
1677 sysc_disable_main_clocks(ddata);
1678 err_opt_clocks:
1679 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1680 if (manage_clocks) {
1681 sysc_disable_opt_clocks(ddata);
1682 sysc_clkdm_allow_idle(ddata);
1683 }
1684
1685 return error;
1686 }
1687
1688 static int sysc_init_sysc_mask(struct sysc *ddata)
1689 {
1690 struct device_node *np = ddata->dev->of_node;
1691 int error;
1692 u32 val;
1693
1694 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1695 if (error)
1696 return 0;
1697
1698 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1699
1700 return 0;
1701 }
1702
1703 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1704 const char *name)
1705 {
1706 struct device_node *np = ddata->dev->of_node;
1707 struct property *prop;
1708 const __be32 *p;
1709 u32 val;
1710
1711 of_property_for_each_u32(np, name, prop, p, val) {
1712 if (val >= SYSC_NR_IDLEMODES) {
1713 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1714 return -EINVAL;
1715 }
1716 *idlemodes |= (1 << val);
1717 }
1718
1719 return 0;
1720 }
1721
1722 static int sysc_init_idlemodes(struct sysc *ddata)
1723 {
1724 int error;
1725
1726 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1727 "ti,sysc-midle");
1728 if (error)
1729 return error;
1730
1731 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1732 "ti,sysc-sidle");
1733 if (error)
1734 return error;
1735
1736 return 0;
1737 }
1738
1739 /*
1740 * Only some devices on omap4 and later have SYSCONFIG reset done
1741 * bit. We can detect this if there is no SYSSTATUS at all, or the
1742 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1743 * have multiple bits for the child devices like OHCI and EHCI.
1744 * Depends on SYSC being parsed first.
1745 */
1746 static int sysc_init_syss_mask(struct sysc *ddata)
1747 {
1748 struct device_node *np = ddata->dev->of_node;
1749 int error;
1750 u32 val;
1751
1752 error = of_property_read_u32(np, "ti,syss-mask", &val);
1753 if (error) {
1754 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1755 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1756 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1757 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1758
1759 return 0;
1760 }
1761
1762 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1763 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1764
1765 ddata->cfg.syss_mask = val;
1766
1767 return 0;
1768 }
1769
1770 /*
1771 * Many child device drivers need to have fck and opt clocks available
1772 * to get the clock rate for device internal configuration etc.
1773 */
1774 static int sysc_child_add_named_clock(struct sysc *ddata,
1775 struct device *child,
1776 const char *name)
1777 {
1778 struct clk *clk;
1779 struct clk_lookup *l;
1780 int error = 0;
1781
1782 if (!name)
1783 return 0;
1784
1785 clk = clk_get(child, name);
1786 if (!IS_ERR(clk)) {
1787 clk_put(clk);
1788
1789 return -EEXIST;
1790 }
1791
1792 clk = clk_get(ddata->dev, name);
1793 if (IS_ERR(clk))
1794 return -ENODEV;
1795
1796 l = clkdev_create(clk, name, dev_name(child));
1797 if (!l)
1798 error = -ENOMEM;
1799
1800 clk_put(clk);
1801
1802 return error;
1803 }
1804
1805 static int sysc_child_add_clocks(struct sysc *ddata,
1806 struct device *child)
1807 {
1808 int i, error;
1809
1810 for (i = 0; i < ddata->nr_clocks; i++) {
1811 error = sysc_child_add_named_clock(ddata,
1812 child,
1813 ddata->clock_roles[i]);
1814 if (error && error != -EEXIST) {
1815 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1816 ddata->clock_roles[i], error);
1817
1818 return error;
1819 }
1820 }
1821
1822 return 0;
1823 }
1824
1825 static struct device_type sysc_device_type = {
1826 };
1827
1828 static struct sysc *sysc_child_to_parent(struct device *dev)
1829 {
1830 struct device *parent = dev->parent;
1831
1832 if (!parent || parent->type != &sysc_device_type)
1833 return NULL;
1834
1835 return dev_get_drvdata(parent);
1836 }
1837
1838 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1839 {
1840 struct sysc *ddata;
1841 int error;
1842
1843 ddata = sysc_child_to_parent(dev);
1844
1845 error = pm_generic_runtime_suspend(dev);
1846 if (error)
1847 return error;
1848
1849 if (!ddata->enabled)
1850 return 0;
1851
1852 return sysc_runtime_suspend(ddata->dev);
1853 }
1854
1855 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1856 {
1857 struct sysc *ddata;
1858 int error;
1859
1860 ddata = sysc_child_to_parent(dev);
1861
1862 if (!ddata->enabled) {
1863 error = sysc_runtime_resume(ddata->dev);
1864 if (error < 0)
1865 dev_err(ddata->dev,
1866 "%s error: %i\n", __func__, error);
1867 }
1868
1869 return pm_generic_runtime_resume(dev);
1870 }
1871
1872 #ifdef CONFIG_PM_SLEEP
1873 static int sysc_child_suspend_noirq(struct device *dev)
1874 {
1875 struct sysc *ddata;
1876 int error;
1877
1878 ddata = sysc_child_to_parent(dev);
1879
1880 dev_dbg(ddata->dev, "%s %s\n", __func__,
1881 ddata->name ? ddata->name : "");
1882
1883 error = pm_generic_suspend_noirq(dev);
1884 if (error) {
1885 dev_err(dev, "%s error at %i: %i\n",
1886 __func__, __LINE__, error);
1887
1888 return error;
1889 }
1890
1891 if (!pm_runtime_status_suspended(dev)) {
1892 error = pm_generic_runtime_suspend(dev);
1893 if (error) {
1894 dev_dbg(dev, "%s busy at %i: %i\n",
1895 __func__, __LINE__, error);
1896
1897 return 0;
1898 }
1899
1900 error = sysc_runtime_suspend(ddata->dev);
1901 if (error) {
1902 dev_err(dev, "%s error at %i: %i\n",
1903 __func__, __LINE__, error);
1904
1905 return error;
1906 }
1907
1908 ddata->child_needs_resume = true;
1909 }
1910
1911 return 0;
1912 }
1913
1914 static int sysc_child_resume_noirq(struct device *dev)
1915 {
1916 struct sysc *ddata;
1917 int error;
1918
1919 ddata = sysc_child_to_parent(dev);
1920
1921 dev_dbg(ddata->dev, "%s %s\n", __func__,
1922 ddata->name ? ddata->name : "");
1923
1924 if (ddata->child_needs_resume) {
1925 ddata->child_needs_resume = false;
1926
1927 error = sysc_runtime_resume(ddata->dev);
1928 if (error)
1929 dev_err(ddata->dev,
1930 "%s runtime resume error: %i\n",
1931 __func__, error);
1932
1933 error = pm_generic_runtime_resume(dev);
1934 if (error)
1935 dev_err(ddata->dev,
1936 "%s generic runtime resume: %i\n",
1937 __func__, error);
1938 }
1939
1940 return pm_generic_resume_noirq(dev);
1941 }
1942 #endif
1943
1944 static struct dev_pm_domain sysc_child_pm_domain = {
1945 .ops = {
1946 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1947 sysc_child_runtime_resume,
1948 NULL)
1949 USE_PLATFORM_PM_SLEEP_OPS
1950 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1951 sysc_child_resume_noirq)
1952 }
1953 };
1954
1955 /**
1956 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1957 * @ddata: device driver data
1958 * @child: child device driver
1959 *
1960 * Allow idle for child devices as done with _od_runtime_suspend().
1961 * Otherwise many child devices will not idle because of the permanent
1962 * parent usecount set in pm_runtime_irq_safe().
1963 *
1964 * Note that the long term solution is to just modify the child device
1965 * drivers to not set pm_runtime_irq_safe() and then this can be just
1966 * dropped.
1967 */
1968 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1969 {
1970 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1971 dev_pm_domain_set(child, &sysc_child_pm_domain);
1972 }
1973
1974 static int sysc_notifier_call(struct notifier_block *nb,
1975 unsigned long event, void *device)
1976 {
1977 struct device *dev = device;
1978 struct sysc *ddata;
1979 int error;
1980
1981 ddata = sysc_child_to_parent(dev);
1982 if (!ddata)
1983 return NOTIFY_DONE;
1984
1985 switch (event) {
1986 case BUS_NOTIFY_ADD_DEVICE:
1987 error = sysc_child_add_clocks(ddata, dev);
1988 if (error)
1989 return error;
1990 sysc_legacy_idle_quirk(ddata, dev);
1991 break;
1992 default:
1993 break;
1994 }
1995
1996 return NOTIFY_DONE;
1997 }
1998
1999 static struct notifier_block sysc_nb = {
2000 .notifier_call = sysc_notifier_call,
2001 };
2002
2003 /* Device tree configured quirks */
2004 struct sysc_dts_quirk {
2005 const char *name;
2006 u32 mask;
2007 };
2008
2009 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2010 { .name = "ti,no-idle-on-init",
2011 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2012 { .name = "ti,no-reset-on-init",
2013 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2014 { .name = "ti,no-idle",
2015 .mask = SYSC_QUIRK_NO_IDLE, },
2016 };
2017
2018 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2019 bool is_child)
2020 {
2021 const struct property *prop;
2022 int i, len;
2023
2024 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2025 const char *name = sysc_dts_quirks[i].name;
2026
2027 prop = of_get_property(np, name, &len);
2028 if (!prop)
2029 continue;
2030
2031 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2032 if (is_child) {
2033 dev_warn(ddata->dev,
2034 "dts flag should be at module level for %s\n",
2035 name);
2036 }
2037 }
2038 }
2039
2040 static int sysc_init_dts_quirks(struct sysc *ddata)
2041 {
2042 struct device_node *np = ddata->dev->of_node;
2043 int error;
2044 u32 val;
2045
2046 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2047
2048 sysc_parse_dts_quirks(ddata, np, false);
2049 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2050 if (!error) {
2051 if (val > 255) {
2052 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2053 val);
2054 }
2055
2056 ddata->cfg.srst_udelay = (u8)val;
2057 }
2058
2059 return 0;
2060 }
2061
2062 static void sysc_unprepare(struct sysc *ddata)
2063 {
2064 int i;
2065
2066 if (!ddata->clocks)
2067 return;
2068
2069 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2070 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2071 clk_unprepare(ddata->clocks[i]);
2072 }
2073 }
2074
2075 /*
2076 * Common sysc register bits found on omap2, also known as type1
2077 */
2078 static const struct sysc_regbits sysc_regbits_omap2 = {
2079 .dmadisable_shift = -ENODEV,
2080 .midle_shift = 12,
2081 .sidle_shift = 3,
2082 .clkact_shift = 8,
2083 .emufree_shift = 5,
2084 .enwkup_shift = 2,
2085 .srst_shift = 1,
2086 .autoidle_shift = 0,
2087 };
2088
2089 static const struct sysc_capabilities sysc_omap2 = {
2090 .type = TI_SYSC_OMAP2,
2091 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2092 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2093 SYSC_OMAP2_AUTOIDLE,
2094 .regbits = &sysc_regbits_omap2,
2095 };
2096
2097 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2098 static const struct sysc_capabilities sysc_omap2_timer = {
2099 .type = TI_SYSC_OMAP2_TIMER,
2100 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2101 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2102 SYSC_OMAP2_AUTOIDLE,
2103 .regbits = &sysc_regbits_omap2,
2104 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2105 };
2106
2107 /*
2108 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2109 * with different sidle position
2110 */
2111 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2112 .dmadisable_shift = -ENODEV,
2113 .midle_shift = -ENODEV,
2114 .sidle_shift = 4,
2115 .clkact_shift = -ENODEV,
2116 .enwkup_shift = -ENODEV,
2117 .srst_shift = 1,
2118 .autoidle_shift = 0,
2119 .emufree_shift = -ENODEV,
2120 };
2121
2122 static const struct sysc_capabilities sysc_omap3_sham = {
2123 .type = TI_SYSC_OMAP3_SHAM,
2124 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2125 .regbits = &sysc_regbits_omap3_sham,
2126 };
2127
2128 /*
2129 * AES register bits found on omap3 and later, a variant of
2130 * sysc_regbits_omap2 with different sidle position
2131 */
2132 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2133 .dmadisable_shift = -ENODEV,
2134 .midle_shift = -ENODEV,
2135 .sidle_shift = 6,
2136 .clkact_shift = -ENODEV,
2137 .enwkup_shift = -ENODEV,
2138 .srst_shift = 1,
2139 .autoidle_shift = 0,
2140 .emufree_shift = -ENODEV,
2141 };
2142
2143 static const struct sysc_capabilities sysc_omap3_aes = {
2144 .type = TI_SYSC_OMAP3_AES,
2145 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2146 .regbits = &sysc_regbits_omap3_aes,
2147 };
2148
2149 /*
2150 * Common sysc register bits found on omap4, also known as type2
2151 */
2152 static const struct sysc_regbits sysc_regbits_omap4 = {
2153 .dmadisable_shift = 16,
2154 .midle_shift = 4,
2155 .sidle_shift = 2,
2156 .clkact_shift = -ENODEV,
2157 .enwkup_shift = -ENODEV,
2158 .emufree_shift = 1,
2159 .srst_shift = 0,
2160 .autoidle_shift = -ENODEV,
2161 };
2162
2163 static const struct sysc_capabilities sysc_omap4 = {
2164 .type = TI_SYSC_OMAP4,
2165 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2166 SYSC_OMAP4_SOFTRESET,
2167 .regbits = &sysc_regbits_omap4,
2168 };
2169
2170 static const struct sysc_capabilities sysc_omap4_timer = {
2171 .type = TI_SYSC_OMAP4_TIMER,
2172 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2173 SYSC_OMAP4_SOFTRESET,
2174 .regbits = &sysc_regbits_omap4,
2175 };
2176
2177 /*
2178 * Common sysc register bits found on omap4, also known as type3
2179 */
2180 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2181 .dmadisable_shift = -ENODEV,
2182 .midle_shift = 2,
2183 .sidle_shift = 0,
2184 .clkact_shift = -ENODEV,
2185 .enwkup_shift = -ENODEV,
2186 .srst_shift = -ENODEV,
2187 .emufree_shift = -ENODEV,
2188 .autoidle_shift = -ENODEV,
2189 };
2190
2191 static const struct sysc_capabilities sysc_omap4_simple = {
2192 .type = TI_SYSC_OMAP4_SIMPLE,
2193 .regbits = &sysc_regbits_omap4_simple,
2194 };
2195
2196 /*
2197 * SmartReflex sysc found on omap34xx
2198 */
2199 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2200 .dmadisable_shift = -ENODEV,
2201 .midle_shift = -ENODEV,
2202 .sidle_shift = -ENODEV,
2203 .clkact_shift = 20,
2204 .enwkup_shift = -ENODEV,
2205 .srst_shift = -ENODEV,
2206 .emufree_shift = -ENODEV,
2207 .autoidle_shift = -ENODEV,
2208 };
2209
2210 static const struct sysc_capabilities sysc_34xx_sr = {
2211 .type = TI_SYSC_OMAP34XX_SR,
2212 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2213 .regbits = &sysc_regbits_omap34xx_sr,
2214 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2215 SYSC_QUIRK_LEGACY_IDLE,
2216 };
2217
2218 /*
2219 * SmartReflex sysc found on omap36xx and later
2220 */
2221 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2222 .dmadisable_shift = -ENODEV,
2223 .midle_shift = -ENODEV,
2224 .sidle_shift = 24,
2225 .clkact_shift = -ENODEV,
2226 .enwkup_shift = 26,
2227 .srst_shift = -ENODEV,
2228 .emufree_shift = -ENODEV,
2229 .autoidle_shift = -ENODEV,
2230 };
2231
2232 static const struct sysc_capabilities sysc_36xx_sr = {
2233 .type = TI_SYSC_OMAP36XX_SR,
2234 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2235 .regbits = &sysc_regbits_omap36xx_sr,
2236 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2237 };
2238
2239 static const struct sysc_capabilities sysc_omap4_sr = {
2240 .type = TI_SYSC_OMAP4_SR,
2241 .regbits = &sysc_regbits_omap36xx_sr,
2242 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2243 };
2244
2245 /*
2246 * McASP register bits found on omap4 and later
2247 */
2248 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2249 .dmadisable_shift = -ENODEV,
2250 .midle_shift = -ENODEV,
2251 .sidle_shift = 0,
2252 .clkact_shift = -ENODEV,
2253 .enwkup_shift = -ENODEV,
2254 .srst_shift = -ENODEV,
2255 .emufree_shift = -ENODEV,
2256 .autoidle_shift = -ENODEV,
2257 };
2258
2259 static const struct sysc_capabilities sysc_omap4_mcasp = {
2260 .type = TI_SYSC_OMAP4_MCASP,
2261 .regbits = &sysc_regbits_omap4_mcasp,
2262 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2263 };
2264
2265 /*
2266 * McASP found on dra7 and later
2267 */
2268 static const struct sysc_capabilities sysc_dra7_mcasp = {
2269 .type = TI_SYSC_OMAP4_SIMPLE,
2270 .regbits = &sysc_regbits_omap4_simple,
2271 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2272 };
2273
2274 /*
2275 * FS USB host found on omap4 and later
2276 */
2277 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2278 .dmadisable_shift = -ENODEV,
2279 .midle_shift = -ENODEV,
2280 .sidle_shift = 24,
2281 .clkact_shift = -ENODEV,
2282 .enwkup_shift = 26,
2283 .srst_shift = -ENODEV,
2284 .emufree_shift = -ENODEV,
2285 .autoidle_shift = -ENODEV,
2286 };
2287
2288 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2289 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2290 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2291 .regbits = &sysc_regbits_omap4_usb_host_fs,
2292 };
2293
2294 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2295 .dmadisable_shift = -ENODEV,
2296 .midle_shift = -ENODEV,
2297 .sidle_shift = -ENODEV,
2298 .clkact_shift = -ENODEV,
2299 .enwkup_shift = 4,
2300 .srst_shift = 0,
2301 .emufree_shift = -ENODEV,
2302 .autoidle_shift = -ENODEV,
2303 };
2304
2305 static const struct sysc_capabilities sysc_dra7_mcan = {
2306 .type = TI_SYSC_DRA7_MCAN,
2307 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2308 .regbits = &sysc_regbits_dra7_mcan,
2309 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2310 };
2311
2312 static int sysc_init_pdata(struct sysc *ddata)
2313 {
2314 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2315 struct ti_sysc_module_data *mdata;
2316
2317 if (!pdata)
2318 return 0;
2319
2320 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2321 if (!mdata)
2322 return -ENOMEM;
2323
2324 if (ddata->legacy_mode) {
2325 mdata->name = ddata->legacy_mode;
2326 mdata->module_pa = ddata->module_pa;
2327 mdata->module_size = ddata->module_size;
2328 mdata->offsets = ddata->offsets;
2329 mdata->nr_offsets = SYSC_MAX_REGS;
2330 mdata->cap = ddata->cap;
2331 mdata->cfg = &ddata->cfg;
2332 }
2333
2334 ddata->mdata = mdata;
2335
2336 return 0;
2337 }
2338
2339 static int sysc_init_match(struct sysc *ddata)
2340 {
2341 const struct sysc_capabilities *cap;
2342
2343 cap = of_device_get_match_data(ddata->dev);
2344 if (!cap)
2345 return -EINVAL;
2346
2347 ddata->cap = cap;
2348 if (ddata->cap)
2349 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2350
2351 return 0;
2352 }
2353
2354 static void ti_sysc_idle(struct work_struct *work)
2355 {
2356 struct sysc *ddata;
2357
2358 ddata = container_of(work, struct sysc, idle_work.work);
2359
2360 /*
2361 * One time decrement of clock usage counts if left on from init.
2362 * Note that we disable opt clocks unconditionally in this case
2363 * as they are enabled unconditionally during init without
2364 * considering sysc_opt_clks_needed() at that point.
2365 */
2366 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2367 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2368 sysc_disable_main_clocks(ddata);
2369 sysc_disable_opt_clocks(ddata);
2370 sysc_clkdm_allow_idle(ddata);
2371 }
2372
2373 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2374 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2375 return;
2376
2377 /*
2378 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2379 * and SYSC_QUIRK_NO_RESET_ON_INIT
2380 */
2381 if (pm_runtime_active(ddata->dev))
2382 pm_runtime_put_sync(ddata->dev);
2383 }
2384
2385 static const struct of_device_id sysc_match_table[] = {
2386 { .compatible = "simple-bus", },
2387 { /* sentinel */ },
2388 };
2389
2390 static int sysc_probe(struct platform_device *pdev)
2391 {
2392 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2393 struct sysc *ddata;
2394 int error;
2395
2396 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2397 if (!ddata)
2398 return -ENOMEM;
2399
2400 ddata->dev = &pdev->dev;
2401 platform_set_drvdata(pdev, ddata);
2402
2403 error = sysc_init_match(ddata);
2404 if (error)
2405 return error;
2406
2407 error = sysc_init_dts_quirks(ddata);
2408 if (error)
2409 return error;
2410
2411 error = sysc_map_and_check_registers(ddata);
2412 if (error)
2413 return error;
2414
2415 error = sysc_init_sysc_mask(ddata);
2416 if (error)
2417 return error;
2418
2419 error = sysc_init_idlemodes(ddata);
2420 if (error)
2421 return error;
2422
2423 error = sysc_init_syss_mask(ddata);
2424 if (error)
2425 return error;
2426
2427 error = sysc_init_pdata(ddata);
2428 if (error)
2429 return error;
2430
2431 sysc_init_early_quirks(ddata);
2432
2433 error = sysc_get_clocks(ddata);
2434 if (error)
2435 return error;
2436
2437 error = sysc_init_resets(ddata);
2438 if (error)
2439 goto unprepare;
2440
2441 error = sysc_init_module(ddata);
2442 if (error)
2443 goto unprepare;
2444
2445 pm_runtime_enable(ddata->dev);
2446 error = pm_runtime_get_sync(ddata->dev);
2447 if (error < 0) {
2448 pm_runtime_put_noidle(ddata->dev);
2449 pm_runtime_disable(ddata->dev);
2450 goto unprepare;
2451 }
2452
2453 /* Balance reset counts */
2454 if (ddata->rsts)
2455 reset_control_assert(ddata->rsts);
2456
2457 sysc_show_registers(ddata);
2458
2459 ddata->dev->type = &sysc_device_type;
2460 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2461 pdata ? pdata->auxdata : NULL,
2462 ddata->dev);
2463 if (error)
2464 goto err;
2465
2466 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2467
2468 /* At least earlycon won't survive without deferred idle */
2469 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2470 SYSC_QUIRK_NO_IDLE_ON_INIT |
2471 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2472 schedule_delayed_work(&ddata->idle_work, 3000);
2473 } else {
2474 pm_runtime_put(&pdev->dev);
2475 }
2476
2477 return 0;
2478
2479 err:
2480 pm_runtime_put_sync(&pdev->dev);
2481 pm_runtime_disable(&pdev->dev);
2482 unprepare:
2483 sysc_unprepare(ddata);
2484
2485 return error;
2486 }
2487
2488 static int sysc_remove(struct platform_device *pdev)
2489 {
2490 struct sysc *ddata = platform_get_drvdata(pdev);
2491 int error;
2492
2493 cancel_delayed_work_sync(&ddata->idle_work);
2494
2495 error = pm_runtime_get_sync(ddata->dev);
2496 if (error < 0) {
2497 pm_runtime_put_noidle(ddata->dev);
2498 pm_runtime_disable(ddata->dev);
2499 goto unprepare;
2500 }
2501
2502 of_platform_depopulate(&pdev->dev);
2503
2504 pm_runtime_put_sync(&pdev->dev);
2505 pm_runtime_disable(&pdev->dev);
2506 reset_control_assert(ddata->rsts);
2507
2508 unprepare:
2509 sysc_unprepare(ddata);
2510
2511 return 0;
2512 }
2513
2514 static const struct of_device_id sysc_match[] = {
2515 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2516 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2517 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2518 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2519 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2520 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2521 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2522 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2523 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2524 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2525 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2526 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2527 { .compatible = "ti,sysc-usb-host-fs",
2528 .data = &sysc_omap4_usb_host_fs, },
2529 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2530 { },
2531 };
2532 MODULE_DEVICE_TABLE(of, sysc_match);
2533
2534 static struct platform_driver sysc_driver = {
2535 .probe = sysc_probe,
2536 .remove = sysc_remove,
2537 .driver = {
2538 .name = "ti-sysc",
2539 .of_match_table = sysc_match,
2540 .pm = &sysc_pm_ops,
2541 },
2542 };
2543
2544 static int __init sysc_init(void)
2545 {
2546 bus_register_notifier(&platform_bus_type, &sysc_nb);
2547
2548 return platform_driver_register(&sysc_driver);
2549 }
2550 module_init(sysc_init);
2551
2552 static void __exit sysc_exit(void)
2553 {
2554 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2555 platform_driver_unregister(&sysc_driver);
2556 }
2557 module_exit(sysc_exit);
2558
2559 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2560 MODULE_LICENSE("GPL v2");
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