1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/list.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20 #include <linux/iopoll.h>
22 #include <linux/platform_data/ti-sysc.h>
24 #include <dt-bindings/bus/ti-sysc.h>
26 #define DIS_ISP BIT(2)
27 #define DIS_IVA BIT(1)
28 #define DIS_SGX BIT(0)
30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
51 struct list_head node
;
54 struct sysc_soc_info
{
55 unsigned long general_purpose
:1;
57 struct mutex list_lock
; /* disabled modules list lock */
58 struct list_head disabled_modules
;
75 static struct sysc_soc_info
*sysc_soc
;
76 static const char * const reg_names
[] = { "rev", "sysc", "syss", };
77 static const char * const clock_names
[SYSC_MAX_CLOCKS
] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
82 #define SYSC_IDLEMODE_MASK 3
83 #define SYSC_CLOCKACTIVITY_MASK 3
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
92 * @mdata: ti-sysc to hwmod translation data for a module
93 * @clocks: clocks used by the interconnect target module
94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
96 * @rsts: resets used by the interconnect target module
97 * @legacy_mode: configured for legacy mode if set
98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
100 * @cookie: data used by legacy platform callbacks
101 * @name: name if available
102 * @revision: interconnect target module revision
103 * @enabled: sysc runtime enabled status
104 * @needs_resume: runtime resume needed on resume from suspend
105 * @child_needs_resume: runtime resume needed for child on resume from suspend
106 * @disable_on_idle: status flag used for disabling modules with resets
107 * @idle_work: work structure used to perform delayed idle on a module
108 * @pre_reset_quirk: module specific pre-reset quirk
109 * @post_reset_quirk: module specific post-reset quirk
110 * @reset_done_quirk: module specific reset done quirk
111 * @module_enable_quirk: module specific enable quirk
112 * @module_disable_quirk: module specific disable quirk
113 * @module_unlock_quirk: module specific sysconfig unlock quirk
114 * @module_lock_quirk: module specific sysconfig lock quirk
120 void __iomem
*module_va
;
121 int offsets
[SYSC_MAX_REGS
];
122 struct ti_sysc_module_data
*mdata
;
124 const char **clock_roles
;
126 struct reset_control
*rsts
;
127 const char *legacy_mode
;
128 const struct sysc_capabilities
*cap
;
129 struct sysc_config cfg
;
130 struct ti_sysc_cookie cookie
;
133 unsigned int enabled
:1;
134 unsigned int needs_resume
:1;
135 unsigned int child_needs_resume
:1;
136 struct delayed_work idle_work
;
137 void (*pre_reset_quirk
)(struct sysc
*sysc
);
138 void (*post_reset_quirk
)(struct sysc
*sysc
);
139 void (*reset_done_quirk
)(struct sysc
*sysc
);
140 void (*module_enable_quirk
)(struct sysc
*sysc
);
141 void (*module_disable_quirk
)(struct sysc
*sysc
);
142 void (*module_unlock_quirk
)(struct sysc
*sysc
);
143 void (*module_lock_quirk
)(struct sysc
*sysc
);
146 static void sysc_parse_dts_quirks(struct sysc
*ddata
, struct device_node
*np
,
149 static void sysc_write(struct sysc
*ddata
, int offset
, u32 value
)
151 if (ddata
->cfg
.quirks
& SYSC_QUIRK_16BIT
) {
152 writew_relaxed(value
& 0xffff, ddata
->module_va
+ offset
);
154 /* Only i2c revision has LO and HI register with stride of 4 */
155 if (ddata
->offsets
[SYSC_REVISION
] >= 0 &&
156 offset
== ddata
->offsets
[SYSC_REVISION
]) {
157 u16 hi
= value
>> 16;
159 writew_relaxed(hi
, ddata
->module_va
+ offset
+ 4);
165 writel_relaxed(value
, ddata
->module_va
+ offset
);
168 static u32
sysc_read(struct sysc
*ddata
, int offset
)
170 if (ddata
->cfg
.quirks
& SYSC_QUIRK_16BIT
) {
173 val
= readw_relaxed(ddata
->module_va
+ offset
);
175 /* Only i2c revision has LO and HI register with stride of 4 */
176 if (ddata
->offsets
[SYSC_REVISION
] >= 0 &&
177 offset
== ddata
->offsets
[SYSC_REVISION
]) {
178 u16 tmp
= readw_relaxed(ddata
->module_va
+ offset
+ 4);
186 return readl_relaxed(ddata
->module_va
+ offset
);
189 static bool sysc_opt_clks_needed(struct sysc
*ddata
)
191 return !!(ddata
->cfg
.quirks
& SYSC_QUIRK_OPT_CLKS_NEEDED
);
194 static u32
sysc_read_revision(struct sysc
*ddata
)
196 int offset
= ddata
->offsets
[SYSC_REVISION
];
201 return sysc_read(ddata
, offset
);
204 static u32
sysc_read_sysconfig(struct sysc
*ddata
)
206 int offset
= ddata
->offsets
[SYSC_SYSCONFIG
];
211 return sysc_read(ddata
, offset
);
214 static u32
sysc_read_sysstatus(struct sysc
*ddata
)
216 int offset
= ddata
->offsets
[SYSC_SYSSTATUS
];
221 return sysc_read(ddata
, offset
);
224 /* Poll on reset status */
225 static int sysc_wait_softreset(struct sysc
*ddata
)
227 u32 sysc_mask
, syss_done
, rstval
;
228 int syss_offset
, error
= 0;
230 syss_offset
= ddata
->offsets
[SYSC_SYSSTATUS
];
231 sysc_mask
= BIT(ddata
->cap
->regbits
->srst_shift
);
233 if (ddata
->cfg
.quirks
& SYSS_QUIRK_RESETDONE_INVERTED
)
236 syss_done
= ddata
->cfg
.syss_mask
;
238 if (syss_offset
>= 0) {
239 error
= readx_poll_timeout(sysc_read_sysstatus
, ddata
, rstval
,
240 (rstval
& ddata
->cfg
.syss_mask
) ==
242 100, MAX_MODULE_SOFTRESET_WAIT
);
244 } else if (ddata
->cfg
.quirks
& SYSC_QUIRK_RESET_STATUS
) {
245 error
= readx_poll_timeout(sysc_read_sysconfig
, ddata
, rstval
,
246 !(rstval
& sysc_mask
),
247 100, MAX_MODULE_SOFTRESET_WAIT
);
253 static int sysc_add_named_clock_from_child(struct sysc
*ddata
,
255 const char *optfck_name
)
257 struct device_node
*np
= ddata
->dev
->of_node
;
258 struct device_node
*child
;
259 struct clk_lookup
*cl
;
268 /* Does the clock alias already exist? */
269 clock
= of_clk_get_by_name(np
, n
);
270 if (!IS_ERR(clock
)) {
276 child
= of_get_next_available_child(np
, NULL
);
280 clock
= devm_get_clk_from_child(ddata
->dev
, child
, name
);
282 return PTR_ERR(clock
);
285 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
286 * limit for clk_get(). If cl ever needs to be freed, it should be done
287 * with clkdev_drop().
289 cl
= kcalloc(1, sizeof(*cl
), GFP_KERNEL
);
294 cl
->dev_id
= dev_name(ddata
->dev
);
303 static int sysc_init_ext_opt_clock(struct sysc
*ddata
, const char *name
)
305 const char *optfck_name
;
308 if (ddata
->nr_clocks
< SYSC_OPTFCK0
)
309 index
= SYSC_OPTFCK0
;
311 index
= ddata
->nr_clocks
;
316 optfck_name
= clock_names
[index
];
318 error
= sysc_add_named_clock_from_child(ddata
, name
, optfck_name
);
322 ddata
->clock_roles
[index
] = optfck_name
;
328 static int sysc_get_one_clock(struct sysc
*ddata
, const char *name
)
330 int error
, i
, index
= -ENODEV
;
332 if (!strncmp(clock_names
[SYSC_FCK
], name
, 3))
334 else if (!strncmp(clock_names
[SYSC_ICK
], name
, 3))
338 for (i
= SYSC_OPTFCK0
; i
< SYSC_MAX_CLOCKS
; i
++) {
339 if (!ddata
->clocks
[i
]) {
347 dev_err(ddata
->dev
, "clock %s not added\n", name
);
351 ddata
->clocks
[index
] = devm_clk_get(ddata
->dev
, name
);
352 if (IS_ERR(ddata
->clocks
[index
])) {
353 dev_err(ddata
->dev
, "clock get error for %s: %li\n",
354 name
, PTR_ERR(ddata
->clocks
[index
]));
356 return PTR_ERR(ddata
->clocks
[index
]);
359 error
= clk_prepare(ddata
->clocks
[index
]);
361 dev_err(ddata
->dev
, "clock prepare error for %s: %i\n",
370 static int sysc_get_clocks(struct sysc
*ddata
)
372 struct device_node
*np
= ddata
->dev
->of_node
;
373 struct property
*prop
;
375 int nr_fck
= 0, nr_ick
= 0, i
, error
= 0;
377 ddata
->clock_roles
= devm_kcalloc(ddata
->dev
,
379 sizeof(*ddata
->clock_roles
),
381 if (!ddata
->clock_roles
)
384 of_property_for_each_string(np
, "clock-names", prop
, name
) {
385 if (!strncmp(clock_names
[SYSC_FCK
], name
, 3))
387 if (!strncmp(clock_names
[SYSC_ICK
], name
, 3))
389 ddata
->clock_roles
[ddata
->nr_clocks
] = name
;
393 if (ddata
->nr_clocks
< 1)
396 if ((ddata
->cfg
.quirks
& SYSC_QUIRK_EXT_OPT_CLOCK
)) {
397 error
= sysc_init_ext_opt_clock(ddata
, NULL
);
402 if (ddata
->nr_clocks
> SYSC_MAX_CLOCKS
) {
403 dev_err(ddata
->dev
, "too many clocks for %pOF\n", np
);
408 if (nr_fck
> 1 || nr_ick
> 1) {
409 dev_err(ddata
->dev
, "max one fck and ick for %pOF\n", np
);
414 /* Always add a slot for main clocks fck and ick even if unused */
420 ddata
->clocks
= devm_kcalloc(ddata
->dev
,
421 ddata
->nr_clocks
, sizeof(*ddata
->clocks
),
426 for (i
= 0; i
< SYSC_MAX_CLOCKS
; i
++) {
427 const char *name
= ddata
->clock_roles
[i
];
432 error
= sysc_get_one_clock(ddata
, name
);
440 static int sysc_enable_main_clocks(struct sysc
*ddata
)
448 for (i
= 0; i
< SYSC_OPTFCK0
; i
++) {
449 clock
= ddata
->clocks
[i
];
451 /* Main clocks may not have ick */
452 if (IS_ERR_OR_NULL(clock
))
455 error
= clk_enable(clock
);
463 for (i
--; i
>= 0; i
--) {
464 clock
= ddata
->clocks
[i
];
466 /* Main clocks may not have ick */
467 if (IS_ERR_OR_NULL(clock
))
476 static void sysc_disable_main_clocks(struct sysc
*ddata
)
484 for (i
= 0; i
< SYSC_OPTFCK0
; i
++) {
485 clock
= ddata
->clocks
[i
];
486 if (IS_ERR_OR_NULL(clock
))
493 static int sysc_enable_opt_clocks(struct sysc
*ddata
)
498 if (!ddata
->clocks
|| ddata
->nr_clocks
< SYSC_OPTFCK0
+ 1)
501 for (i
= SYSC_OPTFCK0
; i
< SYSC_MAX_CLOCKS
; i
++) {
502 clock
= ddata
->clocks
[i
];
504 /* Assume no holes for opt clocks */
505 if (IS_ERR_OR_NULL(clock
))
508 error
= clk_enable(clock
);
516 for (i
--; i
>= 0; i
--) {
517 clock
= ddata
->clocks
[i
];
518 if (IS_ERR_OR_NULL(clock
))
527 static void sysc_disable_opt_clocks(struct sysc
*ddata
)
532 if (!ddata
->clocks
|| ddata
->nr_clocks
< SYSC_OPTFCK0
+ 1)
535 for (i
= SYSC_OPTFCK0
; i
< SYSC_MAX_CLOCKS
; i
++) {
536 clock
= ddata
->clocks
[i
];
538 /* Assume no holes for opt clocks */
539 if (IS_ERR_OR_NULL(clock
))
546 static void sysc_clkdm_deny_idle(struct sysc
*ddata
)
548 struct ti_sysc_platform_data
*pdata
;
550 if (ddata
->legacy_mode
|| (ddata
->cfg
.quirks
& SYSC_QUIRK_CLKDM_NOAUTO
))
553 pdata
= dev_get_platdata(ddata
->dev
);
554 if (pdata
&& pdata
->clkdm_deny_idle
)
555 pdata
->clkdm_deny_idle(ddata
->dev
, &ddata
->cookie
);
558 static void sysc_clkdm_allow_idle(struct sysc
*ddata
)
560 struct ti_sysc_platform_data
*pdata
;
562 if (ddata
->legacy_mode
|| (ddata
->cfg
.quirks
& SYSC_QUIRK_CLKDM_NOAUTO
))
565 pdata
= dev_get_platdata(ddata
->dev
);
566 if (pdata
&& pdata
->clkdm_allow_idle
)
567 pdata
->clkdm_allow_idle(ddata
->dev
, &ddata
->cookie
);
571 * sysc_init_resets - init rstctrl reset line if configured
572 * @ddata: device driver data
574 * See sysc_rstctrl_reset_deassert().
576 static int sysc_init_resets(struct sysc
*ddata
)
579 devm_reset_control_get_optional_shared(ddata
->dev
, "rstctrl");
581 return PTR_ERR_OR_ZERO(ddata
->rsts
);
585 * sysc_parse_and_check_child_range - parses module IO region from ranges
586 * @ddata: device driver data
588 * In general we only need rev, syss, and sysc registers and not the whole
589 * module range. But we do want the offsets for these registers from the
590 * module base. This allows us to check them against the legacy hwmod
591 * platform data. Let's also check the ranges are configured properly.
593 static int sysc_parse_and_check_child_range(struct sysc
*ddata
)
595 struct device_node
*np
= ddata
->dev
->of_node
;
596 const __be32
*ranges
;
597 u32 nr_addr
, nr_size
;
600 ranges
= of_get_property(np
, "ranges", &len
);
602 dev_err(ddata
->dev
, "missing ranges for %pOF\n", np
);
607 len
/= sizeof(*ranges
);
610 dev_err(ddata
->dev
, "incomplete ranges for %pOF\n", np
);
615 error
= of_property_read_u32(np
, "#address-cells", &nr_addr
);
619 error
= of_property_read_u32(np
, "#size-cells", &nr_size
);
623 if (nr_addr
!= 1 || nr_size
!= 1) {
624 dev_err(ddata
->dev
, "invalid ranges for %pOF\n", np
);
630 ddata
->module_pa
= of_translate_address(np
, ranges
++);
631 ddata
->module_size
= be32_to_cpup(ranges
);
636 static struct device_node
*stdout_path
;
638 static void sysc_init_stdout_path(struct sysc
*ddata
)
640 struct device_node
*np
= NULL
;
643 if (IS_ERR(stdout_path
))
649 np
= of_find_node_by_path("/chosen");
653 uart
= of_get_property(np
, "stdout-path", NULL
);
657 np
= of_find_node_by_path(uart
);
666 stdout_path
= ERR_PTR(-ENODEV
);
669 static void sysc_check_quirk_stdout(struct sysc
*ddata
,
670 struct device_node
*np
)
672 sysc_init_stdout_path(ddata
);
673 if (np
!= stdout_path
)
676 ddata
->cfg
.quirks
|= SYSC_QUIRK_NO_IDLE_ON_INIT
|
677 SYSC_QUIRK_NO_RESET_ON_INIT
;
681 * sysc_check_one_child - check child configuration
682 * @ddata: device driver data
683 * @np: child device node
685 * Let's avoid messy situations where we have new interconnect target
686 * node but children have "ti,hwmods". These belong to the interconnect
687 * target node and are managed by this driver.
689 static void sysc_check_one_child(struct sysc
*ddata
,
690 struct device_node
*np
)
694 name
= of_get_property(np
, "ti,hwmods", NULL
);
695 if (name
&& !of_device_is_compatible(np
, "ti,sysc"))
696 dev_warn(ddata
->dev
, "really a child ti,hwmods property?");
698 sysc_check_quirk_stdout(ddata
, np
);
699 sysc_parse_dts_quirks(ddata
, np
, true);
702 static void sysc_check_children(struct sysc
*ddata
)
704 struct device_node
*child
;
706 for_each_child_of_node(ddata
->dev
->of_node
, child
)
707 sysc_check_one_child(ddata
, child
);
711 * So far only I2C uses 16-bit read access with clockactivity with revision
712 * in two registers with stride of 4. We can detect this based on the rev
713 * register size to configure things far enough to be able to properly read
714 * the revision register.
716 static void sysc_check_quirk_16bit(struct sysc
*ddata
, struct resource
*res
)
718 if (resource_size(res
) == 8)
719 ddata
->cfg
.quirks
|= SYSC_QUIRK_16BIT
| SYSC_QUIRK_USE_CLOCKACT
;
723 * sysc_parse_one - parses the interconnect target module registers
724 * @ddata: device driver data
725 * @reg: register to parse
727 static int sysc_parse_one(struct sysc
*ddata
, enum sysc_registers reg
)
729 struct resource
*res
;
736 name
= reg_names
[reg
];
742 res
= platform_get_resource_byname(to_platform_device(ddata
->dev
),
743 IORESOURCE_MEM
, name
);
745 ddata
->offsets
[reg
] = -ENODEV
;
750 ddata
->offsets
[reg
] = res
->start
- ddata
->module_pa
;
751 if (reg
== SYSC_REVISION
)
752 sysc_check_quirk_16bit(ddata
, res
);
757 static int sysc_parse_registers(struct sysc
*ddata
)
761 for (i
= 0; i
< SYSC_MAX_REGS
; i
++) {
762 error
= sysc_parse_one(ddata
, i
);
771 * sysc_check_registers - check for misconfigured register overlaps
772 * @ddata: device driver data
774 static int sysc_check_registers(struct sysc
*ddata
)
776 int i
, j
, nr_regs
= 0, nr_matches
= 0;
778 for (i
= 0; i
< SYSC_MAX_REGS
; i
++) {
779 if (ddata
->offsets
[i
] < 0)
782 if (ddata
->offsets
[i
] > (ddata
->module_size
- 4)) {
783 dev_err(ddata
->dev
, "register outside module range");
788 for (j
= 0; j
< SYSC_MAX_REGS
; j
++) {
789 if (ddata
->offsets
[j
] < 0)
792 if (ddata
->offsets
[i
] == ddata
->offsets
[j
])
798 if (nr_matches
> nr_regs
) {
799 dev_err(ddata
->dev
, "overlapping registers: (%i/%i)",
800 nr_regs
, nr_matches
);
809 * syc_ioremap - ioremap register space for the interconnect target module
810 * @ddata: device driver data
812 * Note that the interconnect target module registers can be anywhere
813 * within the interconnect target module range. For example, SGX has
814 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
815 * has them at offset 0x1200 in the CPSW_WR child. Usually the
816 * the interconnect target module registers are at the beginning of
817 * the module range though.
819 static int sysc_ioremap(struct sysc
*ddata
)
823 if (ddata
->offsets
[SYSC_REVISION
] < 0 &&
824 ddata
->offsets
[SYSC_SYSCONFIG
] < 0 &&
825 ddata
->offsets
[SYSC_SYSSTATUS
] < 0) {
826 size
= ddata
->module_size
;
828 size
= max3(ddata
->offsets
[SYSC_REVISION
],
829 ddata
->offsets
[SYSC_SYSCONFIG
],
830 ddata
->offsets
[SYSC_SYSSTATUS
]);
835 if ((size
+ sizeof(u32
)) > ddata
->module_size
)
836 size
= ddata
->module_size
;
839 ddata
->module_va
= devm_ioremap(ddata
->dev
,
842 if (!ddata
->module_va
)
849 * sysc_map_and_check_registers - ioremap and check device registers
850 * @ddata: device driver data
852 static int sysc_map_and_check_registers(struct sysc
*ddata
)
856 error
= sysc_parse_and_check_child_range(ddata
);
860 sysc_check_children(ddata
);
862 error
= sysc_parse_registers(ddata
);
866 error
= sysc_ioremap(ddata
);
870 error
= sysc_check_registers(ddata
);
878 * sysc_show_rev - read and show interconnect target module revision
879 * @bufp: buffer to print the information to
880 * @ddata: device driver data
882 static int sysc_show_rev(char *bufp
, struct sysc
*ddata
)
886 if (ddata
->offsets
[SYSC_REVISION
] < 0)
887 return sprintf(bufp
, ":NA");
889 len
= sprintf(bufp
, ":%08x", ddata
->revision
);
894 static int sysc_show_reg(struct sysc
*ddata
,
895 char *bufp
, enum sysc_registers reg
)
897 if (ddata
->offsets
[reg
] < 0)
898 return sprintf(bufp
, ":NA");
900 return sprintf(bufp
, ":%x", ddata
->offsets
[reg
]);
903 static int sysc_show_name(char *bufp
, struct sysc
*ddata
)
908 return sprintf(bufp
, ":%s", ddata
->name
);
912 * sysc_show_registers - show information about interconnect target module
913 * @ddata: device driver data
915 static void sysc_show_registers(struct sysc
*ddata
)
921 for (i
= 0; i
< SYSC_MAX_REGS
; i
++)
922 bufp
+= sysc_show_reg(ddata
, bufp
, i
);
924 bufp
+= sysc_show_rev(bufp
, ddata
);
925 bufp
+= sysc_show_name(bufp
, ddata
);
927 dev_dbg(ddata
->dev
, "%llx:%x%s\n",
928 ddata
->module_pa
, ddata
->module_size
,
933 * sysc_write_sysconfig - handle sysconfig quirks for register write
934 * @ddata: device driver data
935 * @value: register value
937 static void sysc_write_sysconfig(struct sysc
*ddata
, u32 value
)
939 if (ddata
->module_unlock_quirk
)
940 ddata
->module_unlock_quirk(ddata
);
942 sysc_write(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
], value
);
944 if (ddata
->module_lock_quirk
)
945 ddata
->module_lock_quirk(ddata
);
948 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
949 #define SYSC_CLOCACT_ICK 2
951 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
952 static int sysc_enable_module(struct device
*dev
)
955 const struct sysc_regbits
*regbits
;
956 u32 reg
, idlemodes
, best_mode
;
959 ddata
= dev_get_drvdata(dev
);
962 * Some modules like DSS reset automatically on idle. Enable optional
963 * reset clocks and wait for OCP softreset to complete.
965 if (ddata
->cfg
.quirks
& SYSC_QUIRK_OPT_CLKS_IN_RESET
) {
966 error
= sysc_enable_opt_clocks(ddata
);
969 "Optional clocks failed for enable: %i\n",
974 error
= sysc_wait_softreset(ddata
);
976 dev_warn(ddata
->dev
, "OCP softreset timed out\n");
977 if (ddata
->cfg
.quirks
& SYSC_QUIRK_OPT_CLKS_IN_RESET
)
978 sysc_disable_opt_clocks(ddata
);
981 * Some subsystem private interconnects, like DSS top level module,
982 * need only the automatic OCP softreset handling with no sysconfig
983 * register bits to configure.
985 if (ddata
->offsets
[SYSC_SYSCONFIG
] == -ENODEV
)
988 regbits
= ddata
->cap
->regbits
;
989 reg
= sysc_read(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
]);
992 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
993 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
994 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
996 if (regbits
->clkact_shift
>= 0 &&
997 (ddata
->cfg
.quirks
& SYSC_QUIRK_USE_CLOCKACT
))
998 reg
|= SYSC_CLOCACT_ICK
<< regbits
->clkact_shift
;
1000 /* Set SIDLE mode */
1001 idlemodes
= ddata
->cfg
.sidlemodes
;
1002 if (!idlemodes
|| regbits
->sidle_shift
< 0)
1005 if (ddata
->cfg
.quirks
& (SYSC_QUIRK_SWSUP_SIDLE
|
1006 SYSC_QUIRK_SWSUP_SIDLE_ACT
)) {
1007 best_mode
= SYSC_IDLE_NO
;
1009 best_mode
= fls(ddata
->cfg
.sidlemodes
) - 1;
1010 if (best_mode
> SYSC_IDLE_MASK
) {
1011 dev_err(dev
, "%s: invalid sidlemode\n", __func__
);
1016 if (regbits
->enwkup_shift
>= 0 &&
1017 ddata
->cfg
.sysc_val
& BIT(regbits
->enwkup_shift
))
1018 reg
|= BIT(regbits
->enwkup_shift
);
1021 reg
&= ~(SYSC_IDLE_MASK
<< regbits
->sidle_shift
);
1022 reg
|= best_mode
<< regbits
->sidle_shift
;
1023 sysc_write_sysconfig(ddata
, reg
);
1026 /* Set MIDLE mode */
1027 idlemodes
= ddata
->cfg
.midlemodes
;
1028 if (!idlemodes
|| regbits
->midle_shift
< 0)
1031 best_mode
= fls(ddata
->cfg
.midlemodes
) - 1;
1032 if (best_mode
> SYSC_IDLE_MASK
) {
1033 dev_err(dev
, "%s: invalid midlemode\n", __func__
);
1037 if (ddata
->cfg
.quirks
& SYSC_QUIRK_SWSUP_MSTANDBY
)
1038 best_mode
= SYSC_IDLE_NO
;
1040 reg
&= ~(SYSC_IDLE_MASK
<< regbits
->midle_shift
);
1041 reg
|= best_mode
<< regbits
->midle_shift
;
1042 sysc_write_sysconfig(ddata
, reg
);
1045 /* Autoidle bit must enabled separately if available */
1046 if (regbits
->autoidle_shift
>= 0 &&
1047 ddata
->cfg
.sysc_val
& BIT(regbits
->autoidle_shift
)) {
1048 reg
|= 1 << regbits
->autoidle_shift
;
1049 sysc_write_sysconfig(ddata
, reg
);
1052 /* Flush posted write */
1053 sysc_read(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
]);
1055 if (ddata
->module_enable_quirk
)
1056 ddata
->module_enable_quirk(ddata
);
1061 static int sysc_best_idle_mode(u32 idlemodes
, u32
*best_mode
)
1063 if (idlemodes
& BIT(SYSC_IDLE_SMART_WKUP
))
1064 *best_mode
= SYSC_IDLE_SMART_WKUP
;
1065 else if (idlemodes
& BIT(SYSC_IDLE_SMART
))
1066 *best_mode
= SYSC_IDLE_SMART
;
1067 else if (idlemodes
& BIT(SYSC_IDLE_FORCE
))
1068 *best_mode
= SYSC_IDLE_FORCE
;
1075 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1076 static int sysc_disable_module(struct device
*dev
)
1079 const struct sysc_regbits
*regbits
;
1080 u32 reg
, idlemodes
, best_mode
;
1083 ddata
= dev_get_drvdata(dev
);
1084 if (ddata
->offsets
[SYSC_SYSCONFIG
] == -ENODEV
)
1087 if (ddata
->module_disable_quirk
)
1088 ddata
->module_disable_quirk(ddata
);
1090 regbits
= ddata
->cap
->regbits
;
1091 reg
= sysc_read(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
]);
1093 /* Set MIDLE mode */
1094 idlemodes
= ddata
->cfg
.midlemodes
;
1095 if (!idlemodes
|| regbits
->midle_shift
< 0)
1098 ret
= sysc_best_idle_mode(idlemodes
, &best_mode
);
1100 dev_err(dev
, "%s: invalid midlemode\n", __func__
);
1104 if (ddata
->cfg
.quirks
& (SYSC_QUIRK_SWSUP_MSTANDBY
) ||
1105 ddata
->cfg
.quirks
& (SYSC_QUIRK_FORCE_MSTANDBY
))
1106 best_mode
= SYSC_IDLE_FORCE
;
1108 reg
&= ~(SYSC_IDLE_MASK
<< regbits
->midle_shift
);
1109 reg
|= best_mode
<< regbits
->midle_shift
;
1110 sysc_write_sysconfig(ddata
, reg
);
1113 /* Set SIDLE mode */
1114 idlemodes
= ddata
->cfg
.sidlemodes
;
1115 if (!idlemodes
|| regbits
->sidle_shift
< 0)
1118 if (ddata
->cfg
.quirks
& SYSC_QUIRK_SWSUP_SIDLE
) {
1119 best_mode
= SYSC_IDLE_FORCE
;
1121 ret
= sysc_best_idle_mode(idlemodes
, &best_mode
);
1123 dev_err(dev
, "%s: invalid sidlemode\n", __func__
);
1128 reg
&= ~(SYSC_IDLE_MASK
<< regbits
->sidle_shift
);
1129 reg
|= best_mode
<< regbits
->sidle_shift
;
1130 if (regbits
->autoidle_shift
>= 0 &&
1131 ddata
->cfg
.sysc_val
& BIT(regbits
->autoidle_shift
))
1132 reg
|= 1 << regbits
->autoidle_shift
;
1133 sysc_write_sysconfig(ddata
, reg
);
1135 /* Flush posted write */
1136 sysc_read(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
]);
1141 static int __maybe_unused
sysc_runtime_suspend_legacy(struct device
*dev
,
1144 struct ti_sysc_platform_data
*pdata
;
1147 pdata
= dev_get_platdata(ddata
->dev
);
1151 if (!pdata
->idle_module
)
1154 error
= pdata
->idle_module(dev
, &ddata
->cookie
);
1156 dev_err(dev
, "%s: could not idle: %i\n",
1159 reset_control_assert(ddata
->rsts
);
1164 static int __maybe_unused
sysc_runtime_resume_legacy(struct device
*dev
,
1167 struct ti_sysc_platform_data
*pdata
;
1170 pdata
= dev_get_platdata(ddata
->dev
);
1174 if (!pdata
->enable_module
)
1177 error
= pdata
->enable_module(dev
, &ddata
->cookie
);
1179 dev_err(dev
, "%s: could not enable: %i\n",
1182 reset_control_deassert(ddata
->rsts
);
1187 static int __maybe_unused
sysc_runtime_suspend(struct device
*dev
)
1192 ddata
= dev_get_drvdata(dev
);
1194 if (!ddata
->enabled
)
1197 sysc_clkdm_deny_idle(ddata
);
1199 if (ddata
->legacy_mode
) {
1200 error
= sysc_runtime_suspend_legacy(dev
, ddata
);
1202 goto err_allow_idle
;
1204 error
= sysc_disable_module(dev
);
1206 goto err_allow_idle
;
1209 sysc_disable_main_clocks(ddata
);
1211 if (sysc_opt_clks_needed(ddata
))
1212 sysc_disable_opt_clocks(ddata
);
1214 ddata
->enabled
= false;
1217 reset_control_assert(ddata
->rsts
);
1219 sysc_clkdm_allow_idle(ddata
);
1224 static int __maybe_unused
sysc_runtime_resume(struct device
*dev
)
1229 ddata
= dev_get_drvdata(dev
);
1235 sysc_clkdm_deny_idle(ddata
);
1237 if (sysc_opt_clks_needed(ddata
)) {
1238 error
= sysc_enable_opt_clocks(ddata
);
1240 goto err_allow_idle
;
1243 error
= sysc_enable_main_clocks(ddata
);
1245 goto err_opt_clocks
;
1247 reset_control_deassert(ddata
->rsts
);
1249 if (ddata
->legacy_mode
) {
1250 error
= sysc_runtime_resume_legacy(dev
, ddata
);
1252 goto err_main_clocks
;
1254 error
= sysc_enable_module(dev
);
1256 goto err_main_clocks
;
1259 ddata
->enabled
= true;
1261 sysc_clkdm_allow_idle(ddata
);
1266 sysc_disable_main_clocks(ddata
);
1268 if (sysc_opt_clks_needed(ddata
))
1269 sysc_disable_opt_clocks(ddata
);
1271 sysc_clkdm_allow_idle(ddata
);
1276 static int __maybe_unused
sysc_noirq_suspend(struct device
*dev
)
1280 ddata
= dev_get_drvdata(dev
);
1282 if (ddata
->cfg
.quirks
& SYSC_QUIRK_LEGACY_IDLE
)
1285 return pm_runtime_force_suspend(dev
);
1288 static int __maybe_unused
sysc_noirq_resume(struct device
*dev
)
1292 ddata
= dev_get_drvdata(dev
);
1294 if (ddata
->cfg
.quirks
& SYSC_QUIRK_LEGACY_IDLE
)
1297 return pm_runtime_force_resume(dev
);
1300 static const struct dev_pm_ops sysc_pm_ops
= {
1301 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend
, sysc_noirq_resume
)
1302 SET_RUNTIME_PM_OPS(sysc_runtime_suspend
,
1303 sysc_runtime_resume
,
1307 /* Module revision register based quirks */
1308 struct sysc_revision_quirk
{
1319 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1320 optrev_val, optrevmask, optquirkmask) \
1322 .name = (optname), \
1323 .base = (optbase), \
1324 .rev_offset = (optrev), \
1325 .sysc_offset = (optsysc), \
1326 .syss_offset = (optsyss), \
1327 .revision = (optrev_val), \
1328 .revision_mask = (optrevmask), \
1329 .quirks = (optquirkmask), \
1332 static const struct sysc_revision_quirk sysc_revision_quirks
[] = {
1333 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1334 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1335 SYSC_QUIRK_LEGACY_IDLE
| SYSC_QUIRK_OPT_CLKS_IN_RESET
),
1336 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1337 SYSC_QUIRK_LEGACY_IDLE
),
1338 SYSC_QUIRK("smartreflex", 0, -ENODEV
, 0x24, -ENODEV
, 0x00000000, 0xffffffff,
1339 SYSC_QUIRK_LEGACY_IDLE
),
1340 SYSC_QUIRK("smartreflex", 0, -ENODEV
, 0x38, -ENODEV
, 0x00000000, 0xffffffff,
1341 SYSC_QUIRK_LEGACY_IDLE
),
1342 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1343 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_LEGACY_IDLE
),
1344 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1345 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_LEGACY_IDLE
),
1346 /* Uarts on omap4 and later */
1347 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1348 SYSC_QUIRK_SWSUP_SIDLE_ACT
| SYSC_QUIRK_LEGACY_IDLE
),
1349 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1350 SYSC_QUIRK_SWSUP_SIDLE_ACT
| SYSC_QUIRK_LEGACY_IDLE
),
1352 /* Quirks that need to be set based on the module address */
1353 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV
, 0x50000800, 0xffffffff,
1354 SYSC_QUIRK_EXT_OPT_CLOCK
| SYSC_QUIRK_NO_RESET_ON_INIT
|
1355 SYSC_QUIRK_SWSUP_SIDLE
),
1357 /* Quirks that need to be set based on detected module */
1358 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV
, 0x40000000, 0xffffffff,
1359 SYSC_MODULE_QUIRK_AESS
),
1360 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV
, -ENODEV
, 0xa3170504, 0xffffffff,
1361 SYSC_QUIRK_CLKDM_NOAUTO
),
1362 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1363 SYSC_QUIRK_OPT_CLKS_IN_RESET
| SYSC_MODULE_QUIRK_DSS_RESET
),
1364 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV
, 0x14, 0x00000040, 0xffffffff,
1365 SYSC_QUIRK_OPT_CLKS_IN_RESET
| SYSC_MODULE_QUIRK_DSS_RESET
),
1366 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV
, 0x14, 0x00000061, 0xffffffff,
1367 SYSC_QUIRK_OPT_CLKS_IN_RESET
| SYSC_MODULE_QUIRK_DSS_RESET
),
1368 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV
, 0x500a0200, 0xffffffff,
1369 SYSC_QUIRK_CLKDM_NOAUTO
),
1370 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV
, 0x500a0200, 0xffffffff,
1371 SYSC_QUIRK_CLKDM_NOAUTO
),
1372 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV
, 0x50030200, 0xffffffff,
1373 SYSC_QUIRK_OPT_CLKS_NEEDED
),
1374 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1375 SYSC_MODULE_QUIRK_HDQ1W
),
1376 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1377 SYSC_MODULE_QUIRK_HDQ1W
),
1378 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1379 SYSC_MODULE_QUIRK_I2C
),
1380 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1381 SYSC_MODULE_QUIRK_I2C
),
1382 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1383 SYSC_MODULE_QUIRK_I2C
),
1384 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1385 SYSC_MODULE_QUIRK_I2C
),
1386 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV
, -ENODEV
, 0x00010201, 0xffffffff, 0),
1387 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV
, 0x40000000 , 0xffffffff,
1388 SYSC_MODULE_QUIRK_SGX
),
1389 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV
, 0x4f201000, 0xffffffff,
1390 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_SWSUP_MSTANDBY
),
1391 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV
, 0x4eb01908, 0xffff00f0,
1392 SYSC_MODULE_QUIRK_RTC_UNLOCK
),
1393 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV
, 0x40006c00, 0xffffefff,
1394 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_SWSUP_MSTANDBY
),
1395 SYSC_QUIRK("tptc", 0, 0, -ENODEV
, -ENODEV
, 0x40007c00, 0xffffffff,
1396 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_SWSUP_MSTANDBY
),
1397 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1398 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_SWSUP_MSTANDBY
),
1399 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV
, 0x4ea2080d, 0xffffffff,
1400 SYSC_QUIRK_SWSUP_SIDLE
| SYSC_QUIRK_SWSUP_MSTANDBY
),
1401 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1402 SYSC_MODULE_QUIRK_WDT
),
1403 /* PRUSS on am3, am4 and am5 */
1404 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV
, 0x47000000, 0xff000000,
1405 SYSC_MODULE_QUIRK_PRUSS
),
1406 /* Watchdog on am3 and am4 */
1407 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1408 SYSC_MODULE_QUIRK_WDT
| SYSC_QUIRK_SWSUP_SIDLE
),
1411 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV
, 0x47300001, 0xffffffff, 0),
1412 SYSC_QUIRK("atl", 0, 0, -ENODEV
, -ENODEV
, 0x0a070100, 0xffffffff, 0),
1413 SYSC_QUIRK("cm", 0, 0, -ENODEV
, -ENODEV
, 0x40000301, 0xffffffff, 0),
1414 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV
, 0x40000900, 0xffffffff, 0),
1415 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1417 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV
, -ENODEV
, 0xa3170504, 0xffffffff, 0),
1418 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV
, -ENODEV
, 0x4edb1902, 0xffffffff, 0),
1419 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1420 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1421 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1422 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV
, 0x50010000, 0xffffffff, 0),
1423 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1424 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1425 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1426 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1427 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV
, 0x500a0200, 0xffffffff, 0),
1428 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1429 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1430 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV
, 0x47400001, 0xffffffff, 0),
1431 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV
, 0, 0, 0),
1432 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV
, 0x40000000 , 0xffffffff, 0),
1433 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV
, 0x50031d00, 0xffffffff, 0),
1434 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1435 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV
, 0x40000101, 0xffffffff, 0),
1436 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV
, 0x44306302, 0xffffffff, 0),
1437 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV
, 0x44307b02, 0xffffffff, 0),
1438 SYSC_QUIRK("mcbsp", 0, -ENODEV
, 0x8c, -ENODEV
, 0, 0, 0),
1439 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV
, 0x40300a0b, 0xffff00ff, 0),
1440 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1441 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV
, 0x00000400, 0xffffffff, 0),
1442 SYSC_QUIRK("m3", 0, 0, -ENODEV
, -ENODEV
, 0x5f580105, 0x0fff0f00, 0),
1443 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1444 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV
, -ENODEV
, 0x50060007, 0xffffffff, 0),
1445 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV
, 0x4fff0800, 0xffffffff, 0),
1446 SYSC_QUIRK("padconf", 0, 0, -ENODEV
, -ENODEV
, 0x40001100, 0xffffffff, 0),
1447 SYSC_QUIRK("prcm", 0, 0, -ENODEV
, -ENODEV
, 0x40000100, 0xffffffff, 0),
1448 SYSC_QUIRK("prcm", 0, 0, -ENODEV
, -ENODEV
, 0x00004102, 0xffffffff, 0),
1449 SYSC_QUIRK("prcm", 0, 0, -ENODEV
, -ENODEV
, 0x40000400, 0xffffffff, 0),
1450 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1451 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1452 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV
, 0x40000900, 0xffffffff, 0),
1453 SYSC_QUIRK("scm", 0, 0, -ENODEV
, -ENODEV
, 0x4e8b0100, 0xffffffff, 0),
1454 SYSC_QUIRK("scm", 0, 0, -ENODEV
, -ENODEV
, 0x4f000100, 0xffffffff, 0),
1455 SYSC_QUIRK("scm", 0, 0, -ENODEV
, -ENODEV
, 0x40000900, 0xffffffff, 0),
1456 SYSC_QUIRK("scrm", 0, 0, -ENODEV
, -ENODEV
, 0x00000010, 0xffffffff, 0),
1457 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV
, 0x40202301, 0xffff0ff0, 0),
1458 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1459 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1460 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV
, 0x40000902, 0xffffffff, 0),
1461 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV
, 0x40002903, 0xffffffff, 0),
1462 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV
, 0x50020000, 0xffffffff, 0),
1463 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV
, 0x00000020, 0xffffffff, 0),
1464 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1465 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1466 /* Some timers on omap4 and later */
1467 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV
, 0x50002100, 0xffffffff, 0),
1468 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV
, 0x4fff1301, 0xffff00ff, 0),
1469 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV
, 0x00000040, 0xffffffff, 0),
1470 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV
, 0x00000011, 0xffffffff, 0),
1471 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV
, 0x00000060, 0xffffffff, 0),
1472 SYSC_QUIRK("tpcc", 0, 0, -ENODEV
, -ENODEV
, 0x40014c00, 0xffffffff, 0),
1473 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1474 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1475 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1476 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV
, 0x50700101, 0xffffffff, 0),
1477 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV
, -ENODEV
, 0x00000002, 0xffffffff, 0),
1478 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV
, 0x4d001200, 0xffffffff, 0),
1483 * Early quirks based on module base and register offsets only that are
1484 * needed before the module revision can be read
1486 static void sysc_init_early_quirks(struct sysc
*ddata
)
1488 const struct sysc_revision_quirk
*q
;
1491 for (i
= 0; i
< ARRAY_SIZE(sysc_revision_quirks
); i
++) {
1492 q
= &sysc_revision_quirks
[i
];
1497 if (q
->base
!= ddata
->module_pa
)
1500 if (q
->rev_offset
!= ddata
->offsets
[SYSC_REVISION
])
1503 if (q
->sysc_offset
!= ddata
->offsets
[SYSC_SYSCONFIG
])
1506 if (q
->syss_offset
!= ddata
->offsets
[SYSC_SYSSTATUS
])
1509 ddata
->name
= q
->name
;
1510 ddata
->cfg
.quirks
|= q
->quirks
;
1514 /* Quirks that also consider the revision register value */
1515 static void sysc_init_revision_quirks(struct sysc
*ddata
)
1517 const struct sysc_revision_quirk
*q
;
1520 for (i
= 0; i
< ARRAY_SIZE(sysc_revision_quirks
); i
++) {
1521 q
= &sysc_revision_quirks
[i
];
1523 if (q
->base
&& q
->base
!= ddata
->module_pa
)
1526 if (q
->rev_offset
!= ddata
->offsets
[SYSC_REVISION
])
1529 if (q
->sysc_offset
!= ddata
->offsets
[SYSC_SYSCONFIG
])
1532 if (q
->syss_offset
!= ddata
->offsets
[SYSC_SYSSTATUS
])
1535 if (q
->revision
== ddata
->revision
||
1536 (q
->revision
& q
->revision_mask
) ==
1537 (ddata
->revision
& q
->revision_mask
)) {
1538 ddata
->name
= q
->name
;
1539 ddata
->cfg
.quirks
|= q
->quirks
;
1545 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1546 * enabled DSS interrupts. Eventually we may be able to do this on
1547 * dispc init rather than top-level DSS init.
1549 static u32
sysc_quirk_dispc(struct sysc
*ddata
, int dispc_offset
,
1552 bool lcd_en
, digit_en
, lcd2_en
= false, lcd3_en
= false;
1553 const int lcd_en_mask
= BIT(0), digit_en_mask
= BIT(1);
1555 bool framedonetv_irq
= true;
1556 u32 val
, irq_mask
= 0;
1558 switch (sysc_soc
->soc
) {
1559 case SOC_2420
... SOC_3630
:
1561 framedonetv_irq
= false;
1563 case SOC_4430
... SOC_4470
:
1572 framedonetv_irq
= false;
1579 /* Remap the whole module range to be able to reset dispc outputs */
1580 devm_iounmap(ddata
->dev
, ddata
->module_va
);
1581 ddata
->module_va
= devm_ioremap(ddata
->dev
,
1583 ddata
->module_size
);
1584 if (!ddata
->module_va
)
1588 val
= sysc_read(ddata
, dispc_offset
+ 0x40);
1589 lcd_en
= val
& lcd_en_mask
;
1590 digit_en
= val
& digit_en_mask
;
1592 irq_mask
|= BIT(0); /* FRAMEDONE */
1594 if (framedonetv_irq
)
1595 irq_mask
|= BIT(24); /* FRAMEDONETV */
1597 irq_mask
|= BIT(2) | BIT(3); /* EVSYNC bits */
1599 if (disable
& (lcd_en
| digit_en
))
1600 sysc_write(ddata
, dispc_offset
+ 0x40,
1601 val
& ~(lcd_en_mask
| digit_en_mask
));
1603 if (manager_count
<= 2)
1606 /* DISPC_CONTROL2 */
1607 val
= sysc_read(ddata
, dispc_offset
+ 0x238);
1608 lcd2_en
= val
& lcd_en_mask
;
1610 irq_mask
|= BIT(22); /* FRAMEDONE2 */
1611 if (disable
&& lcd2_en
)
1612 sysc_write(ddata
, dispc_offset
+ 0x238,
1613 val
& ~lcd_en_mask
);
1615 if (manager_count
<= 3)
1618 /* DISPC_CONTROL3 */
1619 val
= sysc_read(ddata
, dispc_offset
+ 0x848);
1620 lcd3_en
= val
& lcd_en_mask
;
1622 irq_mask
|= BIT(30); /* FRAMEDONE3 */
1623 if (disable
&& lcd3_en
)
1624 sysc_write(ddata
, dispc_offset
+ 0x848,
1625 val
& ~lcd_en_mask
);
1630 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1631 static void sysc_pre_reset_quirk_dss(struct sysc
*ddata
)
1633 const int dispc_offset
= 0x1000;
1637 /* Get enabled outputs */
1638 irq_mask
= sysc_quirk_dispc(ddata
, dispc_offset
, false);
1642 /* Clear IRQSTATUS */
1643 sysc_write(ddata
, dispc_offset
+ 0x18, irq_mask
);
1645 /* Disable outputs */
1646 val
= sysc_quirk_dispc(ddata
, dispc_offset
, true);
1648 /* Poll IRQSTATUS */
1649 error
= readl_poll_timeout(ddata
->module_va
+ dispc_offset
+ 0x18,
1650 val
, val
!= irq_mask
, 100, 50);
1652 dev_warn(ddata
->dev
, "%s: timed out %08x !+ %08x\n",
1653 __func__
, val
, irq_mask
);
1655 if (sysc_soc
->soc
== SOC_3430
) {
1656 /* Clear DSS_SDI_CONTROL */
1657 sysc_write(ddata
, 0x44, 0);
1659 /* Clear DSS_PLL_CONTROL */
1660 sysc_write(ddata
, 0x48, 0);
1663 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1664 sysc_write(ddata
, 0x40, 0);
1667 /* 1-wire needs module's internal clocks enabled for reset */
1668 static void sysc_pre_reset_quirk_hdq1w(struct sysc
*ddata
)
1670 int offset
= 0x0c; /* HDQ_CTRL_STATUS */
1673 val
= sysc_read(ddata
, offset
);
1675 sysc_write(ddata
, offset
, val
);
1678 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1679 static void sysc_module_enable_quirk_aess(struct sysc
*ddata
)
1681 int offset
= 0x7c; /* AESS_AUTO_GATING_ENABLE */
1683 sysc_write(ddata
, offset
, 1);
1686 /* I2C needs to be disabled for reset */
1687 static void sysc_clk_quirk_i2c(struct sysc
*ddata
, bool enable
)
1692 /* I2C_CON, omap2/3 is different from omap4 and later */
1693 if ((ddata
->revision
& 0xffffff00) == 0x001f0000)
1699 val
= sysc_read(ddata
, offset
);
1704 sysc_write(ddata
, offset
, val
);
1707 static void sysc_pre_reset_quirk_i2c(struct sysc
*ddata
)
1709 sysc_clk_quirk_i2c(ddata
, false);
1712 static void sysc_post_reset_quirk_i2c(struct sysc
*ddata
)
1714 sysc_clk_quirk_i2c(ddata
, true);
1717 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1718 static void sysc_quirk_rtc(struct sysc
*ddata
, bool lock
)
1720 u32 val
, kick0_val
= 0, kick1_val
= 0;
1721 unsigned long flags
;
1725 kick0_val
= 0x83e70b13;
1726 kick1_val
= 0x95a4f1e0;
1729 local_irq_save(flags
);
1730 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1731 error
= readl_poll_timeout(ddata
->module_va
+ 0x44, val
,
1732 !(val
& BIT(0)), 100, 50);
1734 dev_warn(ddata
->dev
, "rtc busy timeout\n");
1735 /* Now we have ~15 microseconds to read/write various registers */
1736 sysc_write(ddata
, 0x6c, kick0_val
);
1737 sysc_write(ddata
, 0x70, kick1_val
);
1738 local_irq_restore(flags
);
1741 static void sysc_module_unlock_quirk_rtc(struct sysc
*ddata
)
1743 sysc_quirk_rtc(ddata
, false);
1746 static void sysc_module_lock_quirk_rtc(struct sysc
*ddata
)
1748 sysc_quirk_rtc(ddata
, true);
1751 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1752 static void sysc_module_enable_quirk_sgx(struct sysc
*ddata
)
1754 int offset
= 0xff08; /* OCP_DEBUG_CONFIG */
1755 u32 val
= BIT(31); /* THALIA_INT_BYPASS */
1757 sysc_write(ddata
, offset
, val
);
1760 /* Watchdog timer needs a disable sequence after reset */
1761 static void sysc_reset_done_quirk_wdt(struct sysc
*ddata
)
1763 int wps
, spr
, error
;
1769 sysc_write(ddata
, spr
, 0xaaaa);
1770 error
= readl_poll_timeout(ddata
->module_va
+ wps
, val
,
1772 MAX_MODULE_SOFTRESET_WAIT
);
1774 dev_warn(ddata
->dev
, "wdt disable step1 failed\n");
1776 sysc_write(ddata
, spr
, 0x5555);
1777 error
= readl_poll_timeout(ddata
->module_va
+ wps
, val
,
1779 MAX_MODULE_SOFTRESET_WAIT
);
1781 dev_warn(ddata
->dev
, "wdt disable step2 failed\n");
1784 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1785 static void sysc_module_disable_quirk_pruss(struct sysc
*ddata
)
1789 reg
= sysc_read(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
]);
1790 reg
|= SYSC_PRUSS_STANDBY_INIT
;
1791 sysc_write(ddata
, ddata
->offsets
[SYSC_SYSCONFIG
], reg
);
1794 static void sysc_init_module_quirks(struct sysc
*ddata
)
1796 if (ddata
->legacy_mode
|| !ddata
->name
)
1799 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_HDQ1W
) {
1800 ddata
->pre_reset_quirk
= sysc_pre_reset_quirk_hdq1w
;
1805 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_I2C
) {
1806 ddata
->pre_reset_quirk
= sysc_pre_reset_quirk_i2c
;
1807 ddata
->post_reset_quirk
= sysc_post_reset_quirk_i2c
;
1812 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_AESS
)
1813 ddata
->module_enable_quirk
= sysc_module_enable_quirk_aess
;
1815 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_DSS_RESET
)
1816 ddata
->pre_reset_quirk
= sysc_pre_reset_quirk_dss
;
1818 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_RTC_UNLOCK
) {
1819 ddata
->module_unlock_quirk
= sysc_module_unlock_quirk_rtc
;
1820 ddata
->module_lock_quirk
= sysc_module_lock_quirk_rtc
;
1825 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_SGX
)
1826 ddata
->module_enable_quirk
= sysc_module_enable_quirk_sgx
;
1828 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_WDT
) {
1829 ddata
->reset_done_quirk
= sysc_reset_done_quirk_wdt
;
1830 ddata
->module_disable_quirk
= sysc_reset_done_quirk_wdt
;
1833 if (ddata
->cfg
.quirks
& SYSC_MODULE_QUIRK_PRUSS
)
1834 ddata
->module_disable_quirk
= sysc_module_disable_quirk_pruss
;
1837 static int sysc_clockdomain_init(struct sysc
*ddata
)
1839 struct ti_sysc_platform_data
*pdata
= dev_get_platdata(ddata
->dev
);
1840 struct clk
*fck
= NULL
, *ick
= NULL
;
1843 if (!pdata
|| !pdata
->init_clockdomain
)
1846 switch (ddata
->nr_clocks
) {
1848 ick
= ddata
->clocks
[SYSC_ICK
];
1851 fck
= ddata
->clocks
[SYSC_FCK
];
1857 error
= pdata
->init_clockdomain(ddata
->dev
, fck
, ick
, &ddata
->cookie
);
1858 if (!error
|| error
== -ENODEV
)
1865 * Note that pdata->init_module() typically does a reset first. After
1866 * pdata->init_module() is done, PM runtime can be used for the interconnect
1869 static int sysc_legacy_init(struct sysc
*ddata
)
1871 struct ti_sysc_platform_data
*pdata
= dev_get_platdata(ddata
->dev
);
1874 if (!pdata
|| !pdata
->init_module
)
1877 error
= pdata
->init_module(ddata
->dev
, ddata
->mdata
, &ddata
->cookie
);
1878 if (error
== -EEXIST
)
1885 * Note that the caller must ensure the interconnect target module is enabled
1886 * before calling reset. Otherwise reset will not complete.
1888 static int sysc_reset(struct sysc
*ddata
)
1890 int sysc_offset
, sysc_val
, error
;
1893 sysc_offset
= ddata
->offsets
[SYSC_SYSCONFIG
];
1895 if (ddata
->legacy_mode
||
1896 ddata
->cap
->regbits
->srst_shift
< 0 ||
1897 ddata
->cfg
.quirks
& SYSC_QUIRK_NO_RESET_ON_INIT
)
1900 sysc_mask
= BIT(ddata
->cap
->regbits
->srst_shift
);
1902 if (ddata
->pre_reset_quirk
)
1903 ddata
->pre_reset_quirk(ddata
);
1905 if (sysc_offset
>= 0) {
1906 sysc_val
= sysc_read_sysconfig(ddata
);
1907 sysc_val
|= sysc_mask
;
1908 sysc_write(ddata
, sysc_offset
, sysc_val
);
1911 if (ddata
->cfg
.srst_udelay
)
1912 usleep_range(ddata
->cfg
.srst_udelay
,
1913 ddata
->cfg
.srst_udelay
* 2);
1915 if (ddata
->post_reset_quirk
)
1916 ddata
->post_reset_quirk(ddata
);
1918 error
= sysc_wait_softreset(ddata
);
1920 dev_warn(ddata
->dev
, "OCP softreset timed out\n");
1922 if (ddata
->reset_done_quirk
)
1923 ddata
->reset_done_quirk(ddata
);
1929 * At this point the module is configured enough to read the revision but
1930 * module may not be completely configured yet to use PM runtime. Enable
1931 * all clocks directly during init to configure the quirks needed for PM
1932 * runtime based on the revision register.
1934 static int sysc_init_module(struct sysc
*ddata
)
1938 error
= sysc_clockdomain_init(ddata
);
1942 sysc_clkdm_deny_idle(ddata
);
1945 * Always enable clocks. The bootloader may or may not have enabled
1946 * the related clocks.
1948 error
= sysc_enable_opt_clocks(ddata
);
1952 error
= sysc_enable_main_clocks(ddata
);
1954 goto err_opt_clocks
;
1956 if (!(ddata
->cfg
.quirks
& SYSC_QUIRK_NO_RESET_ON_INIT
)) {
1957 error
= reset_control_deassert(ddata
->rsts
);
1959 goto err_main_clocks
;
1962 ddata
->revision
= sysc_read_revision(ddata
);
1963 sysc_init_revision_quirks(ddata
);
1964 sysc_init_module_quirks(ddata
);
1966 if (ddata
->legacy_mode
) {
1967 error
= sysc_legacy_init(ddata
);
1972 if (!ddata
->legacy_mode
) {
1973 error
= sysc_enable_module(ddata
->dev
);
1978 error
= sysc_reset(ddata
);
1980 dev_err(ddata
->dev
, "Reset failed with %d\n", error
);
1982 if (error
&& !ddata
->legacy_mode
)
1983 sysc_disable_module(ddata
->dev
);
1986 if (error
&& !(ddata
->cfg
.quirks
& SYSC_QUIRK_NO_RESET_ON_INIT
))
1987 reset_control_assert(ddata
->rsts
);
1991 sysc_disable_main_clocks(ddata
);
1993 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1995 sysc_disable_opt_clocks(ddata
);
1996 sysc_clkdm_allow_idle(ddata
);
2002 static int sysc_init_sysc_mask(struct sysc
*ddata
)
2004 struct device_node
*np
= ddata
->dev
->of_node
;
2008 error
= of_property_read_u32(np
, "ti,sysc-mask", &val
);
2012 ddata
->cfg
.sysc_val
= val
& ddata
->cap
->sysc_mask
;
2017 static int sysc_init_idlemode(struct sysc
*ddata
, u8
*idlemodes
,
2020 struct device_node
*np
= ddata
->dev
->of_node
;
2021 struct property
*prop
;
2025 of_property_for_each_u32(np
, name
, prop
, p
, val
) {
2026 if (val
>= SYSC_NR_IDLEMODES
) {
2027 dev_err(ddata
->dev
, "invalid idlemode: %i\n", val
);
2030 *idlemodes
|= (1 << val
);
2036 static int sysc_init_idlemodes(struct sysc
*ddata
)
2040 error
= sysc_init_idlemode(ddata
, &ddata
->cfg
.midlemodes
,
2045 error
= sysc_init_idlemode(ddata
, &ddata
->cfg
.sidlemodes
,
2054 * Only some devices on omap4 and later have SYSCONFIG reset done
2055 * bit. We can detect this if there is no SYSSTATUS at all, or the
2056 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2057 * have multiple bits for the child devices like OHCI and EHCI.
2058 * Depends on SYSC being parsed first.
2060 static int sysc_init_syss_mask(struct sysc
*ddata
)
2062 struct device_node
*np
= ddata
->dev
->of_node
;
2066 error
= of_property_read_u32(np
, "ti,syss-mask", &val
);
2068 if ((ddata
->cap
->type
== TI_SYSC_OMAP4
||
2069 ddata
->cap
->type
== TI_SYSC_OMAP4_TIMER
) &&
2070 (ddata
->cfg
.sysc_val
& SYSC_OMAP4_SOFTRESET
))
2071 ddata
->cfg
.quirks
|= SYSC_QUIRK_RESET_STATUS
;
2076 if (!(val
& 1) && (ddata
->cfg
.sysc_val
& SYSC_OMAP4_SOFTRESET
))
2077 ddata
->cfg
.quirks
|= SYSC_QUIRK_RESET_STATUS
;
2079 ddata
->cfg
.syss_mask
= val
;
2085 * Many child device drivers need to have fck and opt clocks available
2086 * to get the clock rate for device internal configuration etc.
2088 static int sysc_child_add_named_clock(struct sysc
*ddata
,
2089 struct device
*child
,
2093 struct clk_lookup
*l
;
2099 clk
= clk_get(child
, name
);
2105 clk
= clk_get(ddata
->dev
, name
);
2109 l
= clkdev_create(clk
, name
, dev_name(child
));
2118 static int sysc_child_add_clocks(struct sysc
*ddata
,
2119 struct device
*child
)
2123 for (i
= 0; i
< ddata
->nr_clocks
; i
++) {
2124 error
= sysc_child_add_named_clock(ddata
,
2126 ddata
->clock_roles
[i
]);
2127 if (error
&& error
!= -EEXIST
) {
2128 dev_err(ddata
->dev
, "could not add child clock %s: %i\n",
2129 ddata
->clock_roles
[i
], error
);
2138 static struct device_type sysc_device_type
= {
2141 static struct sysc
*sysc_child_to_parent(struct device
*dev
)
2143 struct device
*parent
= dev
->parent
;
2145 if (!parent
|| parent
->type
!= &sysc_device_type
)
2148 return dev_get_drvdata(parent
);
2151 static int __maybe_unused
sysc_child_runtime_suspend(struct device
*dev
)
2156 ddata
= sysc_child_to_parent(dev
);
2158 error
= pm_generic_runtime_suspend(dev
);
2162 if (!ddata
->enabled
)
2165 return sysc_runtime_suspend(ddata
->dev
);
2168 static int __maybe_unused
sysc_child_runtime_resume(struct device
*dev
)
2173 ddata
= sysc_child_to_parent(dev
);
2175 if (!ddata
->enabled
) {
2176 error
= sysc_runtime_resume(ddata
->dev
);
2179 "%s error: %i\n", __func__
, error
);
2182 return pm_generic_runtime_resume(dev
);
2185 #ifdef CONFIG_PM_SLEEP
2186 static int sysc_child_suspend_noirq(struct device
*dev
)
2191 ddata
= sysc_child_to_parent(dev
);
2193 dev_dbg(ddata
->dev
, "%s %s\n", __func__
,
2194 ddata
->name
? ddata
->name
: "");
2196 error
= pm_generic_suspend_noirq(dev
);
2198 dev_err(dev
, "%s error at %i: %i\n",
2199 __func__
, __LINE__
, error
);
2204 if (!pm_runtime_status_suspended(dev
)) {
2205 error
= pm_generic_runtime_suspend(dev
);
2207 dev_dbg(dev
, "%s busy at %i: %i\n",
2208 __func__
, __LINE__
, error
);
2213 error
= sysc_runtime_suspend(ddata
->dev
);
2215 dev_err(dev
, "%s error at %i: %i\n",
2216 __func__
, __LINE__
, error
);
2221 ddata
->child_needs_resume
= true;
2227 static int sysc_child_resume_noirq(struct device
*dev
)
2232 ddata
= sysc_child_to_parent(dev
);
2234 dev_dbg(ddata
->dev
, "%s %s\n", __func__
,
2235 ddata
->name
? ddata
->name
: "");
2237 if (ddata
->child_needs_resume
) {
2238 ddata
->child_needs_resume
= false;
2240 error
= sysc_runtime_resume(ddata
->dev
);
2243 "%s runtime resume error: %i\n",
2246 error
= pm_generic_runtime_resume(dev
);
2249 "%s generic runtime resume: %i\n",
2253 return pm_generic_resume_noirq(dev
);
2257 static struct dev_pm_domain sysc_child_pm_domain
= {
2259 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend
,
2260 sysc_child_runtime_resume
,
2262 USE_PLATFORM_PM_SLEEP_OPS
2263 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq
,
2264 sysc_child_resume_noirq
)
2269 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2270 * @ddata: device driver data
2271 * @child: child device driver
2273 * Allow idle for child devices as done with _od_runtime_suspend().
2274 * Otherwise many child devices will not idle because of the permanent
2275 * parent usecount set in pm_runtime_irq_safe().
2277 * Note that the long term solution is to just modify the child device
2278 * drivers to not set pm_runtime_irq_safe() and then this can be just
2281 static void sysc_legacy_idle_quirk(struct sysc
*ddata
, struct device
*child
)
2283 if (ddata
->cfg
.quirks
& SYSC_QUIRK_LEGACY_IDLE
)
2284 dev_pm_domain_set(child
, &sysc_child_pm_domain
);
2287 static int sysc_notifier_call(struct notifier_block
*nb
,
2288 unsigned long event
, void *device
)
2290 struct device
*dev
= device
;
2294 ddata
= sysc_child_to_parent(dev
);
2299 case BUS_NOTIFY_ADD_DEVICE
:
2300 error
= sysc_child_add_clocks(ddata
, dev
);
2303 sysc_legacy_idle_quirk(ddata
, dev
);
2312 static struct notifier_block sysc_nb
= {
2313 .notifier_call
= sysc_notifier_call
,
2316 /* Device tree configured quirks */
2317 struct sysc_dts_quirk
{
2322 static const struct sysc_dts_quirk sysc_dts_quirks
[] = {
2323 { .name
= "ti,no-idle-on-init",
2324 .mask
= SYSC_QUIRK_NO_IDLE_ON_INIT
, },
2325 { .name
= "ti,no-reset-on-init",
2326 .mask
= SYSC_QUIRK_NO_RESET_ON_INIT
, },
2327 { .name
= "ti,no-idle",
2328 .mask
= SYSC_QUIRK_NO_IDLE
, },
2331 static void sysc_parse_dts_quirks(struct sysc
*ddata
, struct device_node
*np
,
2334 const struct property
*prop
;
2337 for (i
= 0; i
< ARRAY_SIZE(sysc_dts_quirks
); i
++) {
2338 const char *name
= sysc_dts_quirks
[i
].name
;
2340 prop
= of_get_property(np
, name
, &len
);
2344 ddata
->cfg
.quirks
|= sysc_dts_quirks
[i
].mask
;
2346 dev_warn(ddata
->dev
,
2347 "dts flag should be at module level for %s\n",
2353 static int sysc_init_dts_quirks(struct sysc
*ddata
)
2355 struct device_node
*np
= ddata
->dev
->of_node
;
2359 ddata
->legacy_mode
= of_get_property(np
, "ti,hwmods", NULL
);
2361 sysc_parse_dts_quirks(ddata
, np
, false);
2362 error
= of_property_read_u32(np
, "ti,sysc-delay-us", &val
);
2365 dev_warn(ddata
->dev
, "bad ti,sysc-delay-us: %i\n",
2369 ddata
->cfg
.srst_udelay
= (u8
)val
;
2375 static void sysc_unprepare(struct sysc
*ddata
)
2382 for (i
= 0; i
< SYSC_MAX_CLOCKS
; i
++) {
2383 if (!IS_ERR_OR_NULL(ddata
->clocks
[i
]))
2384 clk_unprepare(ddata
->clocks
[i
]);
2389 * Common sysc register bits found on omap2, also known as type1
2391 static const struct sysc_regbits sysc_regbits_omap2
= {
2392 .dmadisable_shift
= -ENODEV
,
2399 .autoidle_shift
= 0,
2402 static const struct sysc_capabilities sysc_omap2
= {
2403 .type
= TI_SYSC_OMAP2
,
2404 .sysc_mask
= SYSC_OMAP2_CLOCKACTIVITY
| SYSC_OMAP2_EMUFREE
|
2405 SYSC_OMAP2_ENAWAKEUP
| SYSC_OMAP2_SOFTRESET
|
2406 SYSC_OMAP2_AUTOIDLE
,
2407 .regbits
= &sysc_regbits_omap2
,
2410 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2411 static const struct sysc_capabilities sysc_omap2_timer
= {
2412 .type
= TI_SYSC_OMAP2_TIMER
,
2413 .sysc_mask
= SYSC_OMAP2_CLOCKACTIVITY
| SYSC_OMAP2_EMUFREE
|
2414 SYSC_OMAP2_ENAWAKEUP
| SYSC_OMAP2_SOFTRESET
|
2415 SYSC_OMAP2_AUTOIDLE
,
2416 .regbits
= &sysc_regbits_omap2
,
2417 .mod_quirks
= SYSC_QUIRK_USE_CLOCKACT
,
2421 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2422 * with different sidle position
2424 static const struct sysc_regbits sysc_regbits_omap3_sham
= {
2425 .dmadisable_shift
= -ENODEV
,
2426 .midle_shift
= -ENODEV
,
2428 .clkact_shift
= -ENODEV
,
2429 .enwkup_shift
= -ENODEV
,
2431 .autoidle_shift
= 0,
2432 .emufree_shift
= -ENODEV
,
2435 static const struct sysc_capabilities sysc_omap3_sham
= {
2436 .type
= TI_SYSC_OMAP3_SHAM
,
2437 .sysc_mask
= SYSC_OMAP2_SOFTRESET
| SYSC_OMAP2_AUTOIDLE
,
2438 .regbits
= &sysc_regbits_omap3_sham
,
2442 * AES register bits found on omap3 and later, a variant of
2443 * sysc_regbits_omap2 with different sidle position
2445 static const struct sysc_regbits sysc_regbits_omap3_aes
= {
2446 .dmadisable_shift
= -ENODEV
,
2447 .midle_shift
= -ENODEV
,
2449 .clkact_shift
= -ENODEV
,
2450 .enwkup_shift
= -ENODEV
,
2452 .autoidle_shift
= 0,
2453 .emufree_shift
= -ENODEV
,
2456 static const struct sysc_capabilities sysc_omap3_aes
= {
2457 .type
= TI_SYSC_OMAP3_AES
,
2458 .sysc_mask
= SYSC_OMAP2_SOFTRESET
| SYSC_OMAP2_AUTOIDLE
,
2459 .regbits
= &sysc_regbits_omap3_aes
,
2463 * Common sysc register bits found on omap4, also known as type2
2465 static const struct sysc_regbits sysc_regbits_omap4
= {
2466 .dmadisable_shift
= 16,
2469 .clkact_shift
= -ENODEV
,
2470 .enwkup_shift
= -ENODEV
,
2473 .autoidle_shift
= -ENODEV
,
2476 static const struct sysc_capabilities sysc_omap4
= {
2477 .type
= TI_SYSC_OMAP4
,
2478 .sysc_mask
= SYSC_OMAP4_DMADISABLE
| SYSC_OMAP4_FREEEMU
|
2479 SYSC_OMAP4_SOFTRESET
,
2480 .regbits
= &sysc_regbits_omap4
,
2483 static const struct sysc_capabilities sysc_omap4_timer
= {
2484 .type
= TI_SYSC_OMAP4_TIMER
,
2485 .sysc_mask
= SYSC_OMAP4_DMADISABLE
| SYSC_OMAP4_FREEEMU
|
2486 SYSC_OMAP4_SOFTRESET
,
2487 .regbits
= &sysc_regbits_omap4
,
2491 * Common sysc register bits found on omap4, also known as type3
2493 static const struct sysc_regbits sysc_regbits_omap4_simple
= {
2494 .dmadisable_shift
= -ENODEV
,
2497 .clkact_shift
= -ENODEV
,
2498 .enwkup_shift
= -ENODEV
,
2499 .srst_shift
= -ENODEV
,
2500 .emufree_shift
= -ENODEV
,
2501 .autoidle_shift
= -ENODEV
,
2504 static const struct sysc_capabilities sysc_omap4_simple
= {
2505 .type
= TI_SYSC_OMAP4_SIMPLE
,
2506 .regbits
= &sysc_regbits_omap4_simple
,
2510 * SmartReflex sysc found on omap34xx
2512 static const struct sysc_regbits sysc_regbits_omap34xx_sr
= {
2513 .dmadisable_shift
= -ENODEV
,
2514 .midle_shift
= -ENODEV
,
2515 .sidle_shift
= -ENODEV
,
2517 .enwkup_shift
= -ENODEV
,
2518 .srst_shift
= -ENODEV
,
2519 .emufree_shift
= -ENODEV
,
2520 .autoidle_shift
= -ENODEV
,
2523 static const struct sysc_capabilities sysc_34xx_sr
= {
2524 .type
= TI_SYSC_OMAP34XX_SR
,
2525 .sysc_mask
= SYSC_OMAP2_CLOCKACTIVITY
,
2526 .regbits
= &sysc_regbits_omap34xx_sr
,
2527 .mod_quirks
= SYSC_QUIRK_USE_CLOCKACT
| SYSC_QUIRK_UNCACHED
|
2528 SYSC_QUIRK_LEGACY_IDLE
,
2532 * SmartReflex sysc found on omap36xx and later
2534 static const struct sysc_regbits sysc_regbits_omap36xx_sr
= {
2535 .dmadisable_shift
= -ENODEV
,
2536 .midle_shift
= -ENODEV
,
2538 .clkact_shift
= -ENODEV
,
2540 .srst_shift
= -ENODEV
,
2541 .emufree_shift
= -ENODEV
,
2542 .autoidle_shift
= -ENODEV
,
2545 static const struct sysc_capabilities sysc_36xx_sr
= {
2546 .type
= TI_SYSC_OMAP36XX_SR
,
2547 .sysc_mask
= SYSC_OMAP3_SR_ENAWAKEUP
,
2548 .regbits
= &sysc_regbits_omap36xx_sr
,
2549 .mod_quirks
= SYSC_QUIRK_UNCACHED
| SYSC_QUIRK_LEGACY_IDLE
,
2552 static const struct sysc_capabilities sysc_omap4_sr
= {
2553 .type
= TI_SYSC_OMAP4_SR
,
2554 .regbits
= &sysc_regbits_omap36xx_sr
,
2555 .mod_quirks
= SYSC_QUIRK_LEGACY_IDLE
,
2559 * McASP register bits found on omap4 and later
2561 static const struct sysc_regbits sysc_regbits_omap4_mcasp
= {
2562 .dmadisable_shift
= -ENODEV
,
2563 .midle_shift
= -ENODEV
,
2565 .clkact_shift
= -ENODEV
,
2566 .enwkup_shift
= -ENODEV
,
2567 .srst_shift
= -ENODEV
,
2568 .emufree_shift
= -ENODEV
,
2569 .autoidle_shift
= -ENODEV
,
2572 static const struct sysc_capabilities sysc_omap4_mcasp
= {
2573 .type
= TI_SYSC_OMAP4_MCASP
,
2574 .regbits
= &sysc_regbits_omap4_mcasp
,
2575 .mod_quirks
= SYSC_QUIRK_OPT_CLKS_NEEDED
,
2579 * McASP found on dra7 and later
2581 static const struct sysc_capabilities sysc_dra7_mcasp
= {
2582 .type
= TI_SYSC_OMAP4_SIMPLE
,
2583 .regbits
= &sysc_regbits_omap4_simple
,
2584 .mod_quirks
= SYSC_QUIRK_OPT_CLKS_NEEDED
,
2588 * FS USB host found on omap4 and later
2590 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs
= {
2591 .dmadisable_shift
= -ENODEV
,
2592 .midle_shift
= -ENODEV
,
2594 .clkact_shift
= -ENODEV
,
2596 .srst_shift
= -ENODEV
,
2597 .emufree_shift
= -ENODEV
,
2598 .autoidle_shift
= -ENODEV
,
2601 static const struct sysc_capabilities sysc_omap4_usb_host_fs
= {
2602 .type
= TI_SYSC_OMAP4_USB_HOST_FS
,
2603 .sysc_mask
= SYSC_OMAP2_ENAWAKEUP
,
2604 .regbits
= &sysc_regbits_omap4_usb_host_fs
,
2607 static const struct sysc_regbits sysc_regbits_dra7_mcan
= {
2608 .dmadisable_shift
= -ENODEV
,
2609 .midle_shift
= -ENODEV
,
2610 .sidle_shift
= -ENODEV
,
2611 .clkact_shift
= -ENODEV
,
2614 .emufree_shift
= -ENODEV
,
2615 .autoidle_shift
= -ENODEV
,
2618 static const struct sysc_capabilities sysc_dra7_mcan
= {
2619 .type
= TI_SYSC_DRA7_MCAN
,
2620 .sysc_mask
= SYSC_DRA7_MCAN_ENAWAKEUP
| SYSC_OMAP4_SOFTRESET
,
2621 .regbits
= &sysc_regbits_dra7_mcan
,
2622 .mod_quirks
= SYSS_QUIRK_RESETDONE_INVERTED
,
2626 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2628 static const struct sysc_capabilities sysc_pruss
= {
2629 .type
= TI_SYSC_PRUSS
,
2630 .sysc_mask
= SYSC_PRUSS_STANDBY_INIT
| SYSC_PRUSS_SUB_MWAIT
,
2631 .regbits
= &sysc_regbits_omap4_simple
,
2632 .mod_quirks
= SYSC_MODULE_QUIRK_PRUSS
,
2635 static int sysc_init_pdata(struct sysc
*ddata
)
2637 struct ti_sysc_platform_data
*pdata
= dev_get_platdata(ddata
->dev
);
2638 struct ti_sysc_module_data
*mdata
;
2643 mdata
= devm_kzalloc(ddata
->dev
, sizeof(*mdata
), GFP_KERNEL
);
2647 if (ddata
->legacy_mode
) {
2648 mdata
->name
= ddata
->legacy_mode
;
2649 mdata
->module_pa
= ddata
->module_pa
;
2650 mdata
->module_size
= ddata
->module_size
;
2651 mdata
->offsets
= ddata
->offsets
;
2652 mdata
->nr_offsets
= SYSC_MAX_REGS
;
2653 mdata
->cap
= ddata
->cap
;
2654 mdata
->cfg
= &ddata
->cfg
;
2657 ddata
->mdata
= mdata
;
2662 static int sysc_init_match(struct sysc
*ddata
)
2664 const struct sysc_capabilities
*cap
;
2666 cap
= of_device_get_match_data(ddata
->dev
);
2672 ddata
->cfg
.quirks
|= ddata
->cap
->mod_quirks
;
2677 static void ti_sysc_idle(struct work_struct
*work
)
2681 ddata
= container_of(work
, struct sysc
, idle_work
.work
);
2684 * One time decrement of clock usage counts if left on from init.
2685 * Note that we disable opt clocks unconditionally in this case
2686 * as they are enabled unconditionally during init without
2687 * considering sysc_opt_clks_needed() at that point.
2689 if (ddata
->cfg
.quirks
& (SYSC_QUIRK_NO_IDLE
|
2690 SYSC_QUIRK_NO_IDLE_ON_INIT
)) {
2691 sysc_disable_main_clocks(ddata
);
2692 sysc_disable_opt_clocks(ddata
);
2693 sysc_clkdm_allow_idle(ddata
);
2696 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2697 if (ddata
->cfg
.quirks
& SYSC_QUIRK_NO_IDLE
)
2701 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2702 * and SYSC_QUIRK_NO_RESET_ON_INIT
2704 if (pm_runtime_active(ddata
->dev
))
2705 pm_runtime_put_sync(ddata
->dev
);
2709 * SoC model and features detection. Only needed for SoCs that need
2710 * special handling for quirks, no need to list others.
2712 static const struct soc_device_attribute sysc_soc_match
[] = {
2713 SOC_FLAG("OMAP242*", SOC_2420
),
2714 SOC_FLAG("OMAP243*", SOC_2430
),
2715 SOC_FLAG("OMAP3[45]*", SOC_3430
),
2716 SOC_FLAG("OMAP3[67]*", SOC_3630
),
2717 SOC_FLAG("OMAP443*", SOC_4430
),
2718 SOC_FLAG("OMAP446*", SOC_4460
),
2719 SOC_FLAG("OMAP447*", SOC_4470
),
2720 SOC_FLAG("OMAP54*", SOC_5430
),
2721 SOC_FLAG("AM433", SOC_AM3
),
2722 SOC_FLAG("AM43*", SOC_AM4
),
2723 SOC_FLAG("DRA7*", SOC_DRA7
),
2729 * List of SoCs variants with disabled features. By default we assume all
2730 * devices in the device tree are available so no need to list those SoCs.
2732 static const struct soc_device_attribute sysc_soc_feat_match
[] = {
2733 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2734 SOC_FLAG("AM3505", DIS_SGX
),
2735 SOC_FLAG("OMAP3525", DIS_SGX
),
2736 SOC_FLAG("OMAP3515", DIS_IVA
| DIS_SGX
),
2737 SOC_FLAG("OMAP3503", DIS_ISP
| DIS_IVA
| DIS_SGX
),
2739 /* OMAP3630/DM3730 variants with some accelerators disabled */
2740 SOC_FLAG("AM3703", DIS_IVA
| DIS_SGX
),
2741 SOC_FLAG("DM3725", DIS_SGX
),
2742 SOC_FLAG("OMAP3611", DIS_ISP
| DIS_IVA
| DIS_SGX
),
2743 SOC_FLAG("OMAP3615/AM3715", DIS_IVA
),
2744 SOC_FLAG("OMAP3621", DIS_ISP
),
2749 static int sysc_add_disabled(unsigned long base
)
2751 struct sysc_address
*disabled_module
;
2753 disabled_module
= kzalloc(sizeof(*disabled_module
), GFP_KERNEL
);
2754 if (!disabled_module
)
2757 disabled_module
->base
= base
;
2759 mutex_lock(&sysc_soc
->list_lock
);
2760 list_add(&disabled_module
->node
, &sysc_soc
->disabled_modules
);
2761 mutex_unlock(&sysc_soc
->list_lock
);
2767 * One time init to detect the booted SoC and disable unavailable features.
2768 * Note that we initialize static data shared across all ti-sysc instances
2769 * so ddata is only used for SoC type. This can be called from module_init
2770 * once we no longer need to rely on platform data.
2772 static int sysc_init_soc(struct sysc
*ddata
)
2774 const struct soc_device_attribute
*match
;
2775 struct ti_sysc_platform_data
*pdata
;
2776 unsigned long features
= 0;
2781 sysc_soc
= kzalloc(sizeof(*sysc_soc
), GFP_KERNEL
);
2785 mutex_init(&sysc_soc
->list_lock
);
2786 INIT_LIST_HEAD(&sysc_soc
->disabled_modules
);
2787 sysc_soc
->general_purpose
= true;
2789 pdata
= dev_get_platdata(ddata
->dev
);
2790 if (pdata
&& pdata
->soc_type_gp
)
2791 sysc_soc
->general_purpose
= pdata
->soc_type_gp();
2793 match
= soc_device_match(sysc_soc_match
);
2794 if (match
&& match
->data
)
2795 sysc_soc
->soc
= (int)match
->data
;
2797 /* Ignore devices that are not available on HS and EMU SoCs */
2798 if (!sysc_soc
->general_purpose
) {
2799 switch (sysc_soc
->soc
) {
2800 case SOC_3430
... SOC_3630
:
2801 sysc_add_disabled(0x48304000); /* timer12 */
2808 match
= soc_device_match(sysc_soc_feat_match
);
2813 features
= (unsigned long)match
->data
;
2816 * Add disabled devices to the list based on the module base.
2817 * Note that this must be done before we attempt to access the
2818 * device and have module revision checks working.
2820 if (features
& DIS_ISP
)
2821 sysc_add_disabled(0x480bd400);
2822 if (features
& DIS_IVA
)
2823 sysc_add_disabled(0x5d000000);
2824 if (features
& DIS_SGX
)
2825 sysc_add_disabled(0x50000000);
2830 static void sysc_cleanup_soc(void)
2832 struct sysc_address
*disabled_module
;
2833 struct list_head
*pos
, *tmp
;
2838 mutex_lock(&sysc_soc
->list_lock
);
2839 list_for_each_safe(pos
, tmp
, &sysc_soc
->disabled_modules
) {
2840 disabled_module
= list_entry(pos
, struct sysc_address
, node
);
2842 kfree(disabled_module
);
2844 mutex_unlock(&sysc_soc
->list_lock
);
2847 static int sysc_check_disabled_devices(struct sysc
*ddata
)
2849 struct sysc_address
*disabled_module
;
2850 struct list_head
*pos
;
2853 mutex_lock(&sysc_soc
->list_lock
);
2854 list_for_each(pos
, &sysc_soc
->disabled_modules
) {
2855 disabled_module
= list_entry(pos
, struct sysc_address
, node
);
2856 if (ddata
->module_pa
== disabled_module
->base
) {
2857 dev_dbg(ddata
->dev
, "module disabled for this SoC\n");
2862 mutex_unlock(&sysc_soc
->list_lock
);
2867 static const struct of_device_id sysc_match_table
[] = {
2868 { .compatible
= "simple-bus", },
2872 static int sysc_probe(struct platform_device
*pdev
)
2874 struct ti_sysc_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
2878 ddata
= devm_kzalloc(&pdev
->dev
, sizeof(*ddata
), GFP_KERNEL
);
2882 ddata
->dev
= &pdev
->dev
;
2883 platform_set_drvdata(pdev
, ddata
);
2885 error
= sysc_init_soc(ddata
);
2889 error
= sysc_init_match(ddata
);
2893 error
= sysc_init_dts_quirks(ddata
);
2897 error
= sysc_map_and_check_registers(ddata
);
2901 error
= sysc_init_sysc_mask(ddata
);
2905 error
= sysc_init_idlemodes(ddata
);
2909 error
= sysc_init_syss_mask(ddata
);
2913 error
= sysc_init_pdata(ddata
);
2917 sysc_init_early_quirks(ddata
);
2919 error
= sysc_check_disabled_devices(ddata
);
2923 error
= sysc_get_clocks(ddata
);
2927 error
= sysc_init_resets(ddata
);
2931 error
= sysc_init_module(ddata
);
2935 pm_runtime_enable(ddata
->dev
);
2936 error
= pm_runtime_get_sync(ddata
->dev
);
2938 pm_runtime_put_noidle(ddata
->dev
);
2939 pm_runtime_disable(ddata
->dev
);
2943 /* Balance use counts as PM runtime should have enabled these all */
2944 if (!(ddata
->cfg
.quirks
& SYSC_QUIRK_NO_RESET_ON_INIT
))
2945 reset_control_assert(ddata
->rsts
);
2947 if (!(ddata
->cfg
.quirks
&
2948 (SYSC_QUIRK_NO_IDLE
| SYSC_QUIRK_NO_IDLE_ON_INIT
))) {
2949 sysc_disable_main_clocks(ddata
);
2950 sysc_disable_opt_clocks(ddata
);
2951 sysc_clkdm_allow_idle(ddata
);
2954 sysc_show_registers(ddata
);
2956 ddata
->dev
->type
= &sysc_device_type
;
2957 error
= of_platform_populate(ddata
->dev
->of_node
, sysc_match_table
,
2958 pdata
? pdata
->auxdata
: NULL
,
2963 INIT_DELAYED_WORK(&ddata
->idle_work
, ti_sysc_idle
);
2965 /* At least earlycon won't survive without deferred idle */
2966 if (ddata
->cfg
.quirks
& (SYSC_QUIRK_NO_IDLE
|
2967 SYSC_QUIRK_NO_IDLE_ON_INIT
|
2968 SYSC_QUIRK_NO_RESET_ON_INIT
)) {
2969 schedule_delayed_work(&ddata
->idle_work
, 3000);
2971 pm_runtime_put(&pdev
->dev
);
2977 pm_runtime_put_sync(&pdev
->dev
);
2978 pm_runtime_disable(&pdev
->dev
);
2980 sysc_unprepare(ddata
);
2985 static int sysc_remove(struct platform_device
*pdev
)
2987 struct sysc
*ddata
= platform_get_drvdata(pdev
);
2990 cancel_delayed_work_sync(&ddata
->idle_work
);
2992 error
= pm_runtime_get_sync(ddata
->dev
);
2994 pm_runtime_put_noidle(ddata
->dev
);
2995 pm_runtime_disable(ddata
->dev
);
2999 of_platform_depopulate(&pdev
->dev
);
3001 pm_runtime_put_sync(&pdev
->dev
);
3002 pm_runtime_disable(&pdev
->dev
);
3003 reset_control_assert(ddata
->rsts
);
3006 sysc_unprepare(ddata
);
3011 static const struct of_device_id sysc_match
[] = {
3012 { .compatible
= "ti,sysc-omap2", .data
= &sysc_omap2
, },
3013 { .compatible
= "ti,sysc-omap2-timer", .data
= &sysc_omap2_timer
, },
3014 { .compatible
= "ti,sysc-omap4", .data
= &sysc_omap4
, },
3015 { .compatible
= "ti,sysc-omap4-timer", .data
= &sysc_omap4_timer
, },
3016 { .compatible
= "ti,sysc-omap4-simple", .data
= &sysc_omap4_simple
, },
3017 { .compatible
= "ti,sysc-omap3430-sr", .data
= &sysc_34xx_sr
, },
3018 { .compatible
= "ti,sysc-omap3630-sr", .data
= &sysc_36xx_sr
, },
3019 { .compatible
= "ti,sysc-omap4-sr", .data
= &sysc_omap4_sr
, },
3020 { .compatible
= "ti,sysc-omap3-sham", .data
= &sysc_omap3_sham
, },
3021 { .compatible
= "ti,sysc-omap-aes", .data
= &sysc_omap3_aes
, },
3022 { .compatible
= "ti,sysc-mcasp", .data
= &sysc_omap4_mcasp
, },
3023 { .compatible
= "ti,sysc-dra7-mcasp", .data
= &sysc_dra7_mcasp
, },
3024 { .compatible
= "ti,sysc-usb-host-fs",
3025 .data
= &sysc_omap4_usb_host_fs
, },
3026 { .compatible
= "ti,sysc-dra7-mcan", .data
= &sysc_dra7_mcan
, },
3027 { .compatible
= "ti,sysc-pruss", .data
= &sysc_pruss
, },
3030 MODULE_DEVICE_TABLE(of
, sysc_match
);
3032 static struct platform_driver sysc_driver
= {
3033 .probe
= sysc_probe
,
3034 .remove
= sysc_remove
,
3037 .of_match_table
= sysc_match
,
3042 static int __init
sysc_init(void)
3044 bus_register_notifier(&platform_bus_type
, &sysc_nb
);
3046 return platform_driver_register(&sysc_driver
);
3048 module_init(sysc_init
);
3050 static void __exit
sysc_exit(void)
3052 bus_unregister_notifier(&platform_bus_type
, &sysc_nb
);
3053 platform_driver_unregister(&sysc_driver
);
3056 module_exit(sysc_exit
);
3058 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3059 MODULE_LICENSE("GPL v2");