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[thirdparty/kernel/stable.git] / drivers / bus / ti-sysc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/cpu_pm.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21 #include <linux/timekeeping.h>
22 #include <linux/iopoll.h>
23
24 #include <linux/platform_data/ti-sysc.h>
25
26 #include <dt-bindings/bus/ti-sysc.h>
27
28 #define DIS_ISP BIT(2)
29 #define DIS_IVA BIT(1)
30 #define DIS_SGX BIT(0)
31
32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
33
34 #define MAX_MODULE_SOFTRESET_WAIT 10000
35
36 enum sysc_soc {
37 SOC_UNKNOWN,
38 SOC_2420,
39 SOC_2430,
40 SOC_3430,
41 SOC_3630,
42 SOC_4430,
43 SOC_4460,
44 SOC_4470,
45 SOC_5430,
46 SOC_AM3,
47 SOC_AM4,
48 SOC_DRA7,
49 };
50
51 struct sysc_address {
52 unsigned long base;
53 struct list_head node;
54 };
55
56 struct sysc_module {
57 struct sysc *ddata;
58 struct list_head node;
59 };
60
61 struct sysc_soc_info {
62 unsigned long general_purpose:1;
63 enum sysc_soc soc;
64 struct mutex list_lock; /* disabled and restored modules list lock */
65 struct list_head disabled_modules;
66 struct list_head restored_modules;
67 struct notifier_block nb;
68 };
69
70 enum sysc_clocks {
71 SYSC_FCK,
72 SYSC_ICK,
73 SYSC_OPTFCK0,
74 SYSC_OPTFCK1,
75 SYSC_OPTFCK2,
76 SYSC_OPTFCK3,
77 SYSC_OPTFCK4,
78 SYSC_OPTFCK5,
79 SYSC_OPTFCK6,
80 SYSC_OPTFCK7,
81 SYSC_MAX_CLOCKS,
82 };
83
84 static struct sysc_soc_info *sysc_soc;
85 static const char * const reg_names[] = { "rev", "sysc", "syss", };
86 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
88 "opt5", "opt6", "opt7",
89 };
90
91 #define SYSC_IDLEMODE_MASK 3
92 #define SYSC_CLOCKACTIVITY_MASK 3
93
94 /**
95 * struct sysc - TI sysc interconnect target module registers and capabilities
96 * @dev: struct device pointer
97 * @module_pa: physical address of the interconnect target module
98 * @module_size: size of the interconnect target module
99 * @module_va: virtual address of the interconnect target module
100 * @offsets: register offsets from module base
101 * @mdata: ti-sysc to hwmod translation data for a module
102 * @clocks: clocks used by the interconnect target module
103 * @clock_roles: clock role names for the found clocks
104 * @nr_clocks: number of clocks used by the interconnect target module
105 * @rsts: resets used by the interconnect target module
106 * @legacy_mode: configured for legacy mode if set
107 * @cap: interconnect target module capabilities
108 * @cfg: interconnect target module configuration
109 * @cookie: data used by legacy platform callbacks
110 * @name: name if available
111 * @revision: interconnect target module revision
112 * @sysconfig: saved sysconfig register value
113 * @reserved: target module is reserved and already in use
114 * @enabled: sysc runtime enabled status
115 * @needs_resume: runtime resume needed on resume from suspend
116 * @child_needs_resume: runtime resume needed for child on resume from suspend
117 * @disable_on_idle: status flag used for disabling modules with resets
118 * @idle_work: work structure used to perform delayed idle on a module
119 * @pre_reset_quirk: module specific pre-reset quirk
120 * @post_reset_quirk: module specific post-reset quirk
121 * @reset_done_quirk: module specific reset done quirk
122 * @module_enable_quirk: module specific enable quirk
123 * @module_disable_quirk: module specific disable quirk
124 * @module_unlock_quirk: module specific sysconfig unlock quirk
125 * @module_lock_quirk: module specific sysconfig lock quirk
126 */
127 struct sysc {
128 struct device *dev;
129 u64 module_pa;
130 u32 module_size;
131 void __iomem *module_va;
132 int offsets[SYSC_MAX_REGS];
133 struct ti_sysc_module_data *mdata;
134 struct clk **clocks;
135 const char **clock_roles;
136 int nr_clocks;
137 struct reset_control *rsts;
138 const char *legacy_mode;
139 const struct sysc_capabilities *cap;
140 struct sysc_config cfg;
141 struct ti_sysc_cookie cookie;
142 const char *name;
143 u32 revision;
144 u32 sysconfig;
145 unsigned int reserved:1;
146 unsigned int enabled:1;
147 unsigned int needs_resume:1;
148 unsigned int child_needs_resume:1;
149 struct delayed_work idle_work;
150 void (*pre_reset_quirk)(struct sysc *sysc);
151 void (*post_reset_quirk)(struct sysc *sysc);
152 void (*reset_done_quirk)(struct sysc *sysc);
153 void (*module_enable_quirk)(struct sysc *sysc);
154 void (*module_disable_quirk)(struct sysc *sysc);
155 void (*module_unlock_quirk)(struct sysc *sysc);
156 void (*module_lock_quirk)(struct sysc *sysc);
157 };
158
159 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
160 bool is_child);
161 static int sysc_reset(struct sysc *ddata);
162
163 static void sysc_write(struct sysc *ddata, int offset, u32 value)
164 {
165 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
166 writew_relaxed(value & 0xffff, ddata->module_va + offset);
167
168 /* Only i2c revision has LO and HI register with stride of 4 */
169 if (ddata->offsets[SYSC_REVISION] >= 0 &&
170 offset == ddata->offsets[SYSC_REVISION]) {
171 u16 hi = value >> 16;
172
173 writew_relaxed(hi, ddata->module_va + offset + 4);
174 }
175
176 return;
177 }
178
179 writel_relaxed(value, ddata->module_va + offset);
180 }
181
182 static u32 sysc_read(struct sysc *ddata, int offset)
183 {
184 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
185 u32 val;
186
187 val = readw_relaxed(ddata->module_va + offset);
188
189 /* Only i2c revision has LO and HI register with stride of 4 */
190 if (ddata->offsets[SYSC_REVISION] >= 0 &&
191 offset == ddata->offsets[SYSC_REVISION]) {
192 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
193
194 val |= tmp << 16;
195 }
196
197 return val;
198 }
199
200 return readl_relaxed(ddata->module_va + offset);
201 }
202
203 static bool sysc_opt_clks_needed(struct sysc *ddata)
204 {
205 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
206 }
207
208 static u32 sysc_read_revision(struct sysc *ddata)
209 {
210 int offset = ddata->offsets[SYSC_REVISION];
211
212 if (offset < 0)
213 return 0;
214
215 return sysc_read(ddata, offset);
216 }
217
218 static u32 sysc_read_sysconfig(struct sysc *ddata)
219 {
220 int offset = ddata->offsets[SYSC_SYSCONFIG];
221
222 if (offset < 0)
223 return 0;
224
225 return sysc_read(ddata, offset);
226 }
227
228 static u32 sysc_read_sysstatus(struct sysc *ddata)
229 {
230 int offset = ddata->offsets[SYSC_SYSSTATUS];
231
232 if (offset < 0)
233 return 0;
234
235 return sysc_read(ddata, offset);
236 }
237
238 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
239 {
240 int error, retries;
241 u32 syss_done, rstval;
242
243 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
244 syss_done = 0;
245 else
246 syss_done = ddata->cfg.syss_mask;
247
248 if (likely(!timekeeping_suspended)) {
249 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
250 rstval, (rstval & ddata->cfg.syss_mask) ==
251 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
252 } else {
253 retries = MAX_MODULE_SOFTRESET_WAIT;
254 while (retries--) {
255 rstval = sysc_read_sysstatus(ddata);
256 if ((rstval & ddata->cfg.syss_mask) == syss_done)
257 return 0;
258 udelay(2); /* Account for udelay flakeyness */
259 }
260 error = -ETIMEDOUT;
261 }
262
263 return error;
264 }
265
266 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
267 {
268 int error, retries;
269 u32 sysc_mask, rstval;
270
271 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
272
273 if (likely(!timekeeping_suspended)) {
274 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
275 rstval, !(rstval & sysc_mask),
276 100, MAX_MODULE_SOFTRESET_WAIT);
277 } else {
278 retries = MAX_MODULE_SOFTRESET_WAIT;
279 while (retries--) {
280 rstval = sysc_read_sysconfig(ddata);
281 if (!(rstval & sysc_mask))
282 return 0;
283 udelay(2); /* Account for udelay flakeyness */
284 }
285 error = -ETIMEDOUT;
286 }
287
288 return error;
289 }
290
291 /* Poll on reset status */
292 static int sysc_wait_softreset(struct sysc *ddata)
293 {
294 int syss_offset, error = 0;
295
296 if (ddata->cap->regbits->srst_shift < 0)
297 return 0;
298
299 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
300
301 if (syss_offset >= 0)
302 error = sysc_poll_reset_sysstatus(ddata);
303 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
304 error = sysc_poll_reset_sysconfig(ddata);
305
306 return error;
307 }
308
309 static int sysc_add_named_clock_from_child(struct sysc *ddata,
310 const char *name,
311 const char *optfck_name)
312 {
313 struct device_node *np = ddata->dev->of_node;
314 struct device_node *child;
315 struct clk_lookup *cl;
316 struct clk *clock;
317 const char *n;
318
319 if (name)
320 n = name;
321 else
322 n = optfck_name;
323
324 /* Does the clock alias already exist? */
325 clock = of_clk_get_by_name(np, n);
326 if (!IS_ERR(clock)) {
327 clk_put(clock);
328
329 return 0;
330 }
331
332 child = of_get_next_available_child(np, NULL);
333 if (!child)
334 return -ENODEV;
335
336 clock = devm_get_clk_from_child(ddata->dev, child, name);
337 if (IS_ERR(clock))
338 return PTR_ERR(clock);
339
340 /*
341 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
342 * limit for clk_get(). If cl ever needs to be freed, it should be done
343 * with clkdev_drop().
344 */
345 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
346 if (!cl)
347 return -ENOMEM;
348
349 cl->con_id = n;
350 cl->dev_id = dev_name(ddata->dev);
351 cl->clk = clock;
352 clkdev_add(cl);
353
354 clk_put(clock);
355
356 return 0;
357 }
358
359 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
360 {
361 const char *optfck_name;
362 int error, index;
363
364 if (ddata->nr_clocks < SYSC_OPTFCK0)
365 index = SYSC_OPTFCK0;
366 else
367 index = ddata->nr_clocks;
368
369 if (name)
370 optfck_name = name;
371 else
372 optfck_name = clock_names[index];
373
374 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
375 if (error)
376 return error;
377
378 ddata->clock_roles[index] = optfck_name;
379 ddata->nr_clocks++;
380
381 return 0;
382 }
383
384 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
385 {
386 int error, i, index = -ENODEV;
387
388 if (!strncmp(clock_names[SYSC_FCK], name, 3))
389 index = SYSC_FCK;
390 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
391 index = SYSC_ICK;
392
393 if (index < 0) {
394 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
395 if (!ddata->clocks[i]) {
396 index = i;
397 break;
398 }
399 }
400 }
401
402 if (index < 0) {
403 dev_err(ddata->dev, "clock %s not added\n", name);
404 return index;
405 }
406
407 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
408 if (IS_ERR(ddata->clocks[index])) {
409 dev_err(ddata->dev, "clock get error for %s: %li\n",
410 name, PTR_ERR(ddata->clocks[index]));
411
412 return PTR_ERR(ddata->clocks[index]);
413 }
414
415 error = clk_prepare(ddata->clocks[index]);
416 if (error) {
417 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
418 name, error);
419
420 return error;
421 }
422
423 return 0;
424 }
425
426 static int sysc_get_clocks(struct sysc *ddata)
427 {
428 struct device_node *np = ddata->dev->of_node;
429 struct property *prop;
430 const char *name;
431 int nr_fck = 0, nr_ick = 0, i, error = 0;
432
433 ddata->clock_roles = devm_kcalloc(ddata->dev,
434 SYSC_MAX_CLOCKS,
435 sizeof(*ddata->clock_roles),
436 GFP_KERNEL);
437 if (!ddata->clock_roles)
438 return -ENOMEM;
439
440 of_property_for_each_string(np, "clock-names", prop, name) {
441 if (!strncmp(clock_names[SYSC_FCK], name, 3))
442 nr_fck++;
443 if (!strncmp(clock_names[SYSC_ICK], name, 3))
444 nr_ick++;
445 ddata->clock_roles[ddata->nr_clocks] = name;
446 ddata->nr_clocks++;
447 }
448
449 if (ddata->nr_clocks < 1)
450 return 0;
451
452 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
453 error = sysc_init_ext_opt_clock(ddata, NULL);
454 if (error)
455 return error;
456 }
457
458 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
459 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
460
461 return -EINVAL;
462 }
463
464 if (nr_fck > 1 || nr_ick > 1) {
465 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
466
467 return -EINVAL;
468 }
469
470 /* Always add a slot for main clocks fck and ick even if unused */
471 if (!nr_fck)
472 ddata->nr_clocks++;
473 if (!nr_ick)
474 ddata->nr_clocks++;
475
476 ddata->clocks = devm_kcalloc(ddata->dev,
477 ddata->nr_clocks, sizeof(*ddata->clocks),
478 GFP_KERNEL);
479 if (!ddata->clocks)
480 return -ENOMEM;
481
482 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
483 const char *name = ddata->clock_roles[i];
484
485 if (!name)
486 continue;
487
488 error = sysc_get_one_clock(ddata, name);
489 if (error)
490 return error;
491 }
492
493 return 0;
494 }
495
496 static int sysc_enable_main_clocks(struct sysc *ddata)
497 {
498 struct clk *clock;
499 int i, error;
500
501 if (!ddata->clocks)
502 return 0;
503
504 for (i = 0; i < SYSC_OPTFCK0; i++) {
505 clock = ddata->clocks[i];
506
507 /* Main clocks may not have ick */
508 if (IS_ERR_OR_NULL(clock))
509 continue;
510
511 error = clk_enable(clock);
512 if (error)
513 goto err_disable;
514 }
515
516 return 0;
517
518 err_disable:
519 for (i--; i >= 0; i--) {
520 clock = ddata->clocks[i];
521
522 /* Main clocks may not have ick */
523 if (IS_ERR_OR_NULL(clock))
524 continue;
525
526 clk_disable(clock);
527 }
528
529 return error;
530 }
531
532 static void sysc_disable_main_clocks(struct sysc *ddata)
533 {
534 struct clk *clock;
535 int i;
536
537 if (!ddata->clocks)
538 return;
539
540 for (i = 0; i < SYSC_OPTFCK0; i++) {
541 clock = ddata->clocks[i];
542 if (IS_ERR_OR_NULL(clock))
543 continue;
544
545 clk_disable(clock);
546 }
547 }
548
549 static int sysc_enable_opt_clocks(struct sysc *ddata)
550 {
551 struct clk *clock;
552 int i, error;
553
554 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
555 return 0;
556
557 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
558 clock = ddata->clocks[i];
559
560 /* Assume no holes for opt clocks */
561 if (IS_ERR_OR_NULL(clock))
562 return 0;
563
564 error = clk_enable(clock);
565 if (error)
566 goto err_disable;
567 }
568
569 return 0;
570
571 err_disable:
572 for (i--; i >= 0; i--) {
573 clock = ddata->clocks[i];
574 if (IS_ERR_OR_NULL(clock))
575 continue;
576
577 clk_disable(clock);
578 }
579
580 return error;
581 }
582
583 static void sysc_disable_opt_clocks(struct sysc *ddata)
584 {
585 struct clk *clock;
586 int i;
587
588 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
589 return;
590
591 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
592 clock = ddata->clocks[i];
593
594 /* Assume no holes for opt clocks */
595 if (IS_ERR_OR_NULL(clock))
596 return;
597
598 clk_disable(clock);
599 }
600 }
601
602 static void sysc_clkdm_deny_idle(struct sysc *ddata)
603 {
604 struct ti_sysc_platform_data *pdata;
605
606 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
607 return;
608
609 pdata = dev_get_platdata(ddata->dev);
610 if (pdata && pdata->clkdm_deny_idle)
611 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
612 }
613
614 static void sysc_clkdm_allow_idle(struct sysc *ddata)
615 {
616 struct ti_sysc_platform_data *pdata;
617
618 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
619 return;
620
621 pdata = dev_get_platdata(ddata->dev);
622 if (pdata && pdata->clkdm_allow_idle)
623 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
624 }
625
626 /**
627 * sysc_init_resets - init rstctrl reset line if configured
628 * @ddata: device driver data
629 *
630 * See sysc_rstctrl_reset_deassert().
631 */
632 static int sysc_init_resets(struct sysc *ddata)
633 {
634 ddata->rsts =
635 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
636
637 return PTR_ERR_OR_ZERO(ddata->rsts);
638 }
639
640 /**
641 * sysc_parse_and_check_child_range - parses module IO region from ranges
642 * @ddata: device driver data
643 *
644 * In general we only need rev, syss, and sysc registers and not the whole
645 * module range. But we do want the offsets for these registers from the
646 * module base. This allows us to check them against the legacy hwmod
647 * platform data. Let's also check the ranges are configured properly.
648 */
649 static int sysc_parse_and_check_child_range(struct sysc *ddata)
650 {
651 struct device_node *np = ddata->dev->of_node;
652 struct of_range_parser parser;
653 struct of_range range;
654 int error;
655
656 error = of_range_parser_init(&parser, np);
657 if (error)
658 return error;
659
660 for_each_of_range(&parser, &range) {
661 ddata->module_pa = range.cpu_addr;
662 ddata->module_size = range.size;
663 break;
664 }
665
666 return 0;
667 }
668
669 /* Interconnect instances to probe before l4_per instances */
670 static struct resource early_bus_ranges[] = {
671 /* am3/4 l4_wkup */
672 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
673 /* omap4/5 and dra7 l4_cfg */
674 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
675 /* omap4 l4_wkup */
676 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
677 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
678 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
679 };
680
681 static atomic_t sysc_defer = ATOMIC_INIT(10);
682
683 /**
684 * sysc_defer_non_critical - defer non_critical interconnect probing
685 * @ddata: device driver data
686 *
687 * We want to probe l4_cfg and l4_wkup interconnect instances before any
688 * l4_per instances as l4_per instances depend on resources on l4_cfg and
689 * l4_wkup interconnects.
690 */
691 static int sysc_defer_non_critical(struct sysc *ddata)
692 {
693 struct resource *res;
694 int i;
695
696 if (!atomic_read(&sysc_defer))
697 return 0;
698
699 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
700 res = &early_bus_ranges[i];
701 if (ddata->module_pa >= res->start &&
702 ddata->module_pa <= res->end) {
703 atomic_set(&sysc_defer, 0);
704
705 return 0;
706 }
707 }
708
709 atomic_dec_if_positive(&sysc_defer);
710
711 return -EPROBE_DEFER;
712 }
713
714 static struct device_node *stdout_path;
715
716 static void sysc_init_stdout_path(struct sysc *ddata)
717 {
718 struct device_node *np = NULL;
719 const char *uart;
720
721 if (IS_ERR(stdout_path))
722 return;
723
724 if (stdout_path)
725 return;
726
727 np = of_find_node_by_path("/chosen");
728 if (!np)
729 goto err;
730
731 uart = of_get_property(np, "stdout-path", NULL);
732 if (!uart)
733 goto err;
734
735 np = of_find_node_by_path(uart);
736 if (!np)
737 goto err;
738
739 stdout_path = np;
740
741 return;
742
743 err:
744 stdout_path = ERR_PTR(-ENODEV);
745 }
746
747 static void sysc_check_quirk_stdout(struct sysc *ddata,
748 struct device_node *np)
749 {
750 sysc_init_stdout_path(ddata);
751 if (np != stdout_path)
752 return;
753
754 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
755 SYSC_QUIRK_NO_RESET_ON_INIT;
756 }
757
758 /**
759 * sysc_check_one_child - check child configuration
760 * @ddata: device driver data
761 * @np: child device node
762 *
763 * Let's avoid messy situations where we have new interconnect target
764 * node but children have "ti,hwmods". These belong to the interconnect
765 * target node and are managed by this driver.
766 */
767 static void sysc_check_one_child(struct sysc *ddata,
768 struct device_node *np)
769 {
770 const char *name;
771
772 name = of_get_property(np, "ti,hwmods", NULL);
773 if (name && !of_device_is_compatible(np, "ti,sysc"))
774 dev_warn(ddata->dev, "really a child ti,hwmods property?");
775
776 sysc_check_quirk_stdout(ddata, np);
777 sysc_parse_dts_quirks(ddata, np, true);
778 }
779
780 static void sysc_check_children(struct sysc *ddata)
781 {
782 struct device_node *child;
783
784 for_each_child_of_node(ddata->dev->of_node, child)
785 sysc_check_one_child(ddata, child);
786 }
787
788 /*
789 * So far only I2C uses 16-bit read access with clockactivity with revision
790 * in two registers with stride of 4. We can detect this based on the rev
791 * register size to configure things far enough to be able to properly read
792 * the revision register.
793 */
794 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
795 {
796 if (resource_size(res) == 8)
797 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
798 }
799
800 /**
801 * sysc_parse_one - parses the interconnect target module registers
802 * @ddata: device driver data
803 * @reg: register to parse
804 */
805 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
806 {
807 struct resource *res;
808 const char *name;
809
810 switch (reg) {
811 case SYSC_REVISION:
812 case SYSC_SYSCONFIG:
813 case SYSC_SYSSTATUS:
814 name = reg_names[reg];
815 break;
816 default:
817 return -EINVAL;
818 }
819
820 res = platform_get_resource_byname(to_platform_device(ddata->dev),
821 IORESOURCE_MEM, name);
822 if (!res) {
823 ddata->offsets[reg] = -ENODEV;
824
825 return 0;
826 }
827
828 ddata->offsets[reg] = res->start - ddata->module_pa;
829 if (reg == SYSC_REVISION)
830 sysc_check_quirk_16bit(ddata, res);
831
832 return 0;
833 }
834
835 static int sysc_parse_registers(struct sysc *ddata)
836 {
837 int i, error;
838
839 for (i = 0; i < SYSC_MAX_REGS; i++) {
840 error = sysc_parse_one(ddata, i);
841 if (error)
842 return error;
843 }
844
845 return 0;
846 }
847
848 /**
849 * sysc_check_registers - check for misconfigured register overlaps
850 * @ddata: device driver data
851 */
852 static int sysc_check_registers(struct sysc *ddata)
853 {
854 int i, j, nr_regs = 0, nr_matches = 0;
855
856 for (i = 0; i < SYSC_MAX_REGS; i++) {
857 if (ddata->offsets[i] < 0)
858 continue;
859
860 if (ddata->offsets[i] > (ddata->module_size - 4)) {
861 dev_err(ddata->dev, "register outside module range");
862
863 return -EINVAL;
864 }
865
866 for (j = 0; j < SYSC_MAX_REGS; j++) {
867 if (ddata->offsets[j] < 0)
868 continue;
869
870 if (ddata->offsets[i] == ddata->offsets[j])
871 nr_matches++;
872 }
873 nr_regs++;
874 }
875
876 if (nr_matches > nr_regs) {
877 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
878 nr_regs, nr_matches);
879
880 return -EINVAL;
881 }
882
883 return 0;
884 }
885
886 /**
887 * sysc_ioremap - ioremap register space for the interconnect target module
888 * @ddata: device driver data
889 *
890 * Note that the interconnect target module registers can be anywhere
891 * within the interconnect target module range. For example, SGX has
892 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
893 * has them at offset 0x1200 in the CPSW_WR child. Usually the
894 * interconnect target module registers are at the beginning of
895 * the module range though.
896 */
897 static int sysc_ioremap(struct sysc *ddata)
898 {
899 int size;
900
901 if (ddata->offsets[SYSC_REVISION] < 0 &&
902 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
903 ddata->offsets[SYSC_SYSSTATUS] < 0) {
904 size = ddata->module_size;
905 } else {
906 size = max3(ddata->offsets[SYSC_REVISION],
907 ddata->offsets[SYSC_SYSCONFIG],
908 ddata->offsets[SYSC_SYSSTATUS]);
909
910 if (size < SZ_1K)
911 size = SZ_1K;
912
913 if ((size + sizeof(u32)) > ddata->module_size)
914 size = ddata->module_size;
915 }
916
917 ddata->module_va = devm_ioremap(ddata->dev,
918 ddata->module_pa,
919 size + sizeof(u32));
920 if (!ddata->module_va)
921 return -EIO;
922
923 return 0;
924 }
925
926 /**
927 * sysc_map_and_check_registers - ioremap and check device registers
928 * @ddata: device driver data
929 */
930 static int sysc_map_and_check_registers(struct sysc *ddata)
931 {
932 struct device_node *np = ddata->dev->of_node;
933 int error;
934
935 error = sysc_parse_and_check_child_range(ddata);
936 if (error)
937 return error;
938
939 error = sysc_defer_non_critical(ddata);
940 if (error)
941 return error;
942
943 sysc_check_children(ddata);
944
945 if (!of_property_present(np, "reg"))
946 return 0;
947
948 error = sysc_parse_registers(ddata);
949 if (error)
950 return error;
951
952 error = sysc_ioremap(ddata);
953 if (error)
954 return error;
955
956 error = sysc_check_registers(ddata);
957 if (error)
958 return error;
959
960 return 0;
961 }
962
963 /**
964 * sysc_show_rev - read and show interconnect target module revision
965 * @bufp: buffer to print the information to
966 * @ddata: device driver data
967 */
968 static int sysc_show_rev(char *bufp, struct sysc *ddata)
969 {
970 int len;
971
972 if (ddata->offsets[SYSC_REVISION] < 0)
973 return sprintf(bufp, ":NA");
974
975 len = sprintf(bufp, ":%08x", ddata->revision);
976
977 return len;
978 }
979
980 static int sysc_show_reg(struct sysc *ddata,
981 char *bufp, enum sysc_registers reg)
982 {
983 if (ddata->offsets[reg] < 0)
984 return sprintf(bufp, ":NA");
985
986 return sprintf(bufp, ":%x", ddata->offsets[reg]);
987 }
988
989 static int sysc_show_name(char *bufp, struct sysc *ddata)
990 {
991 if (!ddata->name)
992 return 0;
993
994 return sprintf(bufp, ":%s", ddata->name);
995 }
996
997 /**
998 * sysc_show_registers - show information about interconnect target module
999 * @ddata: device driver data
1000 */
1001 static void sysc_show_registers(struct sysc *ddata)
1002 {
1003 char buf[128];
1004 char *bufp = buf;
1005 int i;
1006
1007 for (i = 0; i < SYSC_MAX_REGS; i++)
1008 bufp += sysc_show_reg(ddata, bufp, i);
1009
1010 bufp += sysc_show_rev(bufp, ddata);
1011 bufp += sysc_show_name(bufp, ddata);
1012
1013 dev_dbg(ddata->dev, "%llx:%x%s\n",
1014 ddata->module_pa, ddata->module_size,
1015 buf);
1016 }
1017
1018 /**
1019 * sysc_write_sysconfig - handle sysconfig quirks for register write
1020 * @ddata: device driver data
1021 * @value: register value
1022 */
1023 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1024 {
1025 if (ddata->module_unlock_quirk)
1026 ddata->module_unlock_quirk(ddata);
1027
1028 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1029
1030 if (ddata->module_lock_quirk)
1031 ddata->module_lock_quirk(ddata);
1032 }
1033
1034 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1035 #define SYSC_CLOCACT_ICK 2
1036
1037 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1038 static int sysc_enable_module(struct device *dev)
1039 {
1040 struct sysc *ddata;
1041 const struct sysc_regbits *regbits;
1042 u32 reg, idlemodes, best_mode;
1043 int error;
1044
1045 ddata = dev_get_drvdata(dev);
1046
1047 /*
1048 * Some modules like DSS reset automatically on idle. Enable optional
1049 * reset clocks and wait for OCP softreset to complete.
1050 */
1051 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1052 error = sysc_enable_opt_clocks(ddata);
1053 if (error) {
1054 dev_err(ddata->dev,
1055 "Optional clocks failed for enable: %i\n",
1056 error);
1057 return error;
1058 }
1059 }
1060 /*
1061 * Some modules like i2c and hdq1w have unusable reset status unless
1062 * the module reset quirk is enabled. Skip status check on enable.
1063 */
1064 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1065 error = sysc_wait_softreset(ddata);
1066 if (error)
1067 dev_warn(ddata->dev, "OCP softreset timed out\n");
1068 }
1069 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1070 sysc_disable_opt_clocks(ddata);
1071
1072 /*
1073 * Some subsystem private interconnects, like DSS top level module,
1074 * need only the automatic OCP softreset handling with no sysconfig
1075 * register bits to configure.
1076 */
1077 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1078 return 0;
1079
1080 regbits = ddata->cap->regbits;
1081 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1082
1083 /*
1084 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1085 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1086 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1087 */
1088 if (regbits->clkact_shift >= 0 &&
1089 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1090 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1091
1092 /* Set SIDLE mode */
1093 idlemodes = ddata->cfg.sidlemodes;
1094 if (!idlemodes || regbits->sidle_shift < 0)
1095 goto set_midle;
1096
1097 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1098 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1099 best_mode = SYSC_IDLE_NO;
1100 } else {
1101 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1102 if (best_mode > SYSC_IDLE_MASK) {
1103 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1104 return -EINVAL;
1105 }
1106
1107 /* Set WAKEUP */
1108 if (regbits->enwkup_shift >= 0 &&
1109 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1110 reg |= BIT(regbits->enwkup_shift);
1111 }
1112
1113 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1114 reg |= best_mode << regbits->sidle_shift;
1115 sysc_write_sysconfig(ddata, reg);
1116
1117 set_midle:
1118 /* Set MIDLE mode */
1119 idlemodes = ddata->cfg.midlemodes;
1120 if (!idlemodes || regbits->midle_shift < 0)
1121 goto set_autoidle;
1122
1123 best_mode = fls(ddata->cfg.midlemodes) - 1;
1124 if (best_mode > SYSC_IDLE_MASK) {
1125 dev_err(dev, "%s: invalid midlemode\n", __func__);
1126 error = -EINVAL;
1127 goto save_context;
1128 }
1129
1130 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1131 best_mode = SYSC_IDLE_NO;
1132
1133 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1134 reg |= best_mode << regbits->midle_shift;
1135 sysc_write_sysconfig(ddata, reg);
1136
1137 set_autoidle:
1138 /* Autoidle bit must enabled separately if available */
1139 if (regbits->autoidle_shift >= 0 &&
1140 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1141 reg |= 1 << regbits->autoidle_shift;
1142 sysc_write_sysconfig(ddata, reg);
1143 }
1144
1145 error = 0;
1146
1147 save_context:
1148 /* Save context and flush posted write */
1149 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1150
1151 if (ddata->module_enable_quirk)
1152 ddata->module_enable_quirk(ddata);
1153
1154 return error;
1155 }
1156
1157 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1158 {
1159 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1160 *best_mode = SYSC_IDLE_SMART_WKUP;
1161 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1162 *best_mode = SYSC_IDLE_SMART;
1163 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1164 *best_mode = SYSC_IDLE_FORCE;
1165 else
1166 return -EINVAL;
1167
1168 return 0;
1169 }
1170
1171 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1172 static int sysc_disable_module(struct device *dev)
1173 {
1174 struct sysc *ddata;
1175 const struct sysc_regbits *regbits;
1176 u32 reg, idlemodes, best_mode;
1177 int ret;
1178
1179 ddata = dev_get_drvdata(dev);
1180 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1181 return 0;
1182
1183 if (ddata->module_disable_quirk)
1184 ddata->module_disable_quirk(ddata);
1185
1186 regbits = ddata->cap->regbits;
1187 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1188
1189 /* Set MIDLE mode */
1190 idlemodes = ddata->cfg.midlemodes;
1191 if (!idlemodes || regbits->midle_shift < 0)
1192 goto set_sidle;
1193
1194 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1195 if (ret) {
1196 dev_err(dev, "%s: invalid midlemode\n", __func__);
1197 return ret;
1198 }
1199
1200 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1201 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1202 best_mode = SYSC_IDLE_FORCE;
1203
1204 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1205 reg |= best_mode << regbits->midle_shift;
1206 sysc_write_sysconfig(ddata, reg);
1207
1208 set_sidle:
1209 /* Set SIDLE mode */
1210 idlemodes = ddata->cfg.sidlemodes;
1211 if (!idlemodes || regbits->sidle_shift < 0) {
1212 ret = 0;
1213 goto save_context;
1214 }
1215
1216 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1217 best_mode = SYSC_IDLE_FORCE;
1218 } else {
1219 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1220 if (ret) {
1221 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1222 ret = -EINVAL;
1223 goto save_context;
1224 }
1225 }
1226
1227 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1228 reg |= best_mode << regbits->sidle_shift;
1229 if (regbits->autoidle_shift >= 0 &&
1230 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1231 reg |= 1 << regbits->autoidle_shift;
1232 sysc_write_sysconfig(ddata, reg);
1233
1234 ret = 0;
1235
1236 save_context:
1237 /* Save context and flush posted write */
1238 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1239
1240 return ret;
1241 }
1242
1243 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1244 struct sysc *ddata)
1245 {
1246 struct ti_sysc_platform_data *pdata;
1247 int error;
1248
1249 pdata = dev_get_platdata(ddata->dev);
1250 if (!pdata)
1251 return 0;
1252
1253 if (!pdata->idle_module)
1254 return -ENODEV;
1255
1256 error = pdata->idle_module(dev, &ddata->cookie);
1257 if (error)
1258 dev_err(dev, "%s: could not idle: %i\n",
1259 __func__, error);
1260
1261 reset_control_assert(ddata->rsts);
1262
1263 return 0;
1264 }
1265
1266 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1267 struct sysc *ddata)
1268 {
1269 struct ti_sysc_platform_data *pdata;
1270 int error;
1271
1272 pdata = dev_get_platdata(ddata->dev);
1273 if (!pdata)
1274 return 0;
1275
1276 if (!pdata->enable_module)
1277 return -ENODEV;
1278
1279 error = pdata->enable_module(dev, &ddata->cookie);
1280 if (error)
1281 dev_err(dev, "%s: could not enable: %i\n",
1282 __func__, error);
1283
1284 reset_control_deassert(ddata->rsts);
1285
1286 return 0;
1287 }
1288
1289 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1290 {
1291 struct sysc *ddata;
1292 int error = 0;
1293
1294 ddata = dev_get_drvdata(dev);
1295
1296 if (!ddata->enabled)
1297 return 0;
1298
1299 sysc_clkdm_deny_idle(ddata);
1300
1301 if (ddata->legacy_mode) {
1302 error = sysc_runtime_suspend_legacy(dev, ddata);
1303 if (error)
1304 goto err_allow_idle;
1305 } else {
1306 error = sysc_disable_module(dev);
1307 if (error)
1308 goto err_allow_idle;
1309 }
1310
1311 sysc_disable_main_clocks(ddata);
1312
1313 if (sysc_opt_clks_needed(ddata))
1314 sysc_disable_opt_clocks(ddata);
1315
1316 ddata->enabled = false;
1317
1318 err_allow_idle:
1319 sysc_clkdm_allow_idle(ddata);
1320
1321 reset_control_assert(ddata->rsts);
1322
1323 return error;
1324 }
1325
1326 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1327 {
1328 struct sysc *ddata;
1329 int error = 0;
1330
1331 ddata = dev_get_drvdata(dev);
1332
1333 if (ddata->enabled)
1334 return 0;
1335
1336
1337 sysc_clkdm_deny_idle(ddata);
1338
1339 if (sysc_opt_clks_needed(ddata)) {
1340 error = sysc_enable_opt_clocks(ddata);
1341 if (error)
1342 goto err_allow_idle;
1343 }
1344
1345 error = sysc_enable_main_clocks(ddata);
1346 if (error)
1347 goto err_opt_clocks;
1348
1349 reset_control_deassert(ddata->rsts);
1350
1351 if (ddata->legacy_mode) {
1352 error = sysc_runtime_resume_legacy(dev, ddata);
1353 if (error)
1354 goto err_main_clocks;
1355 } else {
1356 error = sysc_enable_module(dev);
1357 if (error)
1358 goto err_main_clocks;
1359 }
1360
1361 ddata->enabled = true;
1362
1363 sysc_clkdm_allow_idle(ddata);
1364
1365 return 0;
1366
1367 err_main_clocks:
1368 sysc_disable_main_clocks(ddata);
1369 err_opt_clocks:
1370 if (sysc_opt_clks_needed(ddata))
1371 sysc_disable_opt_clocks(ddata);
1372 err_allow_idle:
1373 sysc_clkdm_allow_idle(ddata);
1374
1375 return error;
1376 }
1377
1378 /*
1379 * Checks if device context was lost. Assumes the sysconfig register value
1380 * after lost context is different from the configured value. Only works for
1381 * enabled devices.
1382 *
1383 * Eventually we may want to also add support to using the context lost
1384 * registers that some SoCs have.
1385 */
1386 static int sysc_check_context(struct sysc *ddata)
1387 {
1388 u32 reg;
1389
1390 if (!ddata->enabled)
1391 return -ENODATA;
1392
1393 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1394 if (reg == ddata->sysconfig)
1395 return 0;
1396
1397 return -EACCES;
1398 }
1399
1400 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1401 {
1402 struct device *dev = ddata->dev;
1403 int error;
1404
1405 if (ddata->enabled) {
1406 /* Nothing to do if enabled and context not lost */
1407 error = sysc_check_context(ddata);
1408 if (!error)
1409 return 0;
1410
1411 /* Disable target module if it is enabled */
1412 error = sysc_runtime_suspend(dev);
1413 if (error)
1414 dev_warn(dev, "reinit suspend failed: %i\n", error);
1415 }
1416
1417 /* Enable target module */
1418 error = sysc_runtime_resume(dev);
1419 if (error)
1420 dev_warn(dev, "reinit resume failed: %i\n", error);
1421
1422 /* Some modules like am335x gpmc need reset and restore of sysconfig */
1423 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) {
1424 error = sysc_reset(ddata);
1425 if (error)
1426 dev_warn(dev, "reinit reset failed: %i\n", error);
1427
1428 sysc_write_sysconfig(ddata, ddata->sysconfig);
1429 }
1430
1431 if (leave_enabled)
1432 return error;
1433
1434 /* Disable target module if no leave_enabled was set */
1435 error = sysc_runtime_suspend(dev);
1436 if (error)
1437 dev_warn(dev, "reinit suspend failed: %i\n", error);
1438
1439 return error;
1440 }
1441
1442 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1443 {
1444 struct sysc *ddata;
1445
1446 ddata = dev_get_drvdata(dev);
1447
1448 if (ddata->cfg.quirks &
1449 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1450 return 0;
1451
1452 if (!ddata->enabled)
1453 return 0;
1454
1455 ddata->needs_resume = 1;
1456
1457 return sysc_runtime_suspend(dev);
1458 }
1459
1460 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1461 {
1462 struct sysc *ddata;
1463 int error = 0;
1464
1465 ddata = dev_get_drvdata(dev);
1466
1467 if (ddata->cfg.quirks &
1468 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1469 return 0;
1470
1471 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1472 error = sysc_reinit_module(ddata, ddata->needs_resume);
1473 if (error)
1474 dev_warn(dev, "noirq_resume failed: %i\n", error);
1475 } else if (ddata->needs_resume) {
1476 error = sysc_runtime_resume(dev);
1477 if (error)
1478 dev_warn(dev, "noirq_resume failed: %i\n", error);
1479 }
1480
1481 ddata->needs_resume = 0;
1482
1483 return error;
1484 }
1485
1486 static const struct dev_pm_ops sysc_pm_ops = {
1487 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1488 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1489 sysc_runtime_resume,
1490 NULL)
1491 };
1492
1493 /* Module revision register based quirks */
1494 struct sysc_revision_quirk {
1495 const char *name;
1496 u32 base;
1497 int rev_offset;
1498 int sysc_offset;
1499 int syss_offset;
1500 u32 revision;
1501 u32 revision_mask;
1502 u32 quirks;
1503 };
1504
1505 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1506 optrev_val, optrevmask, optquirkmask) \
1507 { \
1508 .name = (optname), \
1509 .base = (optbase), \
1510 .rev_offset = (optrev), \
1511 .sysc_offset = (optsysc), \
1512 .syss_offset = (optsyss), \
1513 .revision = (optrev_val), \
1514 .revision_mask = (optrevmask), \
1515 .quirks = (optquirkmask), \
1516 }
1517
1518 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1519 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1520 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1521 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1522 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1523 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1524 /* Uarts on omap4 and later */
1525 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1526 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1527 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1528 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1529 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
1530 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1531
1532 /* Quirks that need to be set based on the module address */
1533 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1534 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1535 SYSC_QUIRK_SWSUP_SIDLE),
1536
1537 /* Quirks that need to be set based on detected module */
1538 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1539 SYSC_MODULE_QUIRK_AESS),
1540 /* Errata i893 handling for dra7 dcan1 and 2 */
1541 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1542 SYSC_QUIRK_CLKDM_NOAUTO),
1543 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1544 SYSC_QUIRK_CLKDM_NOAUTO),
1545 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1546 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1547 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1548 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1549 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1550 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1551 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1552 SYSC_QUIRK_CLKDM_NOAUTO),
1553 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1554 SYSC_QUIRK_CLKDM_NOAUTO),
1555 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1556 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1557 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1558 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST |
1559 SYSC_QUIRK_GPMC_DEBUG),
1560 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1561 SYSC_QUIRK_OPT_CLKS_NEEDED),
1562 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1563 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1564 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1565 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1566 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1567 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1568 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1569 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1570 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1571 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1572 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1573 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1574 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1575 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1576 SYSC_MODULE_QUIRK_SGX),
1577 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1578 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1579 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1580 SYSC_QUIRK_SWSUP_SIDLE),
1581 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1582 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1583 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1584 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1585 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1586 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1587 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1588 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1589 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1590 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1591 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1592 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1593 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033,
1594 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1595 SYSC_MODULE_QUIRK_OTG),
1596 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040,
1597 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1598 SYSC_MODULE_QUIRK_OTG),
1599 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1600 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1601 SYSC_MODULE_QUIRK_OTG),
1602 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1603 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1604 SYSC_QUIRK_REINIT_ON_CTX_LOST),
1605 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1606 SYSC_MODULE_QUIRK_WDT),
1607 /* PRUSS on am3, am4 and am5 */
1608 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1609 SYSC_MODULE_QUIRK_PRUSS),
1610 /* Watchdog on am3 and am4 */
1611 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1612 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1613
1614 #ifdef DEBUG
1615 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1616 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1617 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1618 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1619 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1620 0xffff00f0, 0),
1621 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1622 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1623 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1624 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1625 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1626 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1627 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1628 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1629 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1630 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1631 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1632 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1633 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1634 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1635 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1636 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1637 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1638 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1639 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1640 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1641 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1642 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1643 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1644 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1645 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1646 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1647 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1648 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1649 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1650 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1651 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1652 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1653 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1654 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1655 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1656 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1657 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1658 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1659 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1660 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1661 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1662 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1663 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1664 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1665 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1666 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1667 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1668 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1669 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0),
1670 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1671 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1672 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1673 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1674 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1675 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1676 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1677 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1678 /* Some timers on omap4 and later */
1679 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1680 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1681 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1682 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1683 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1684 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1685 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1686 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1687 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1688 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1689 #endif
1690 };
1691
1692 /*
1693 * Early quirks based on module base and register offsets only that are
1694 * needed before the module revision can be read
1695 */
1696 static void sysc_init_early_quirks(struct sysc *ddata)
1697 {
1698 const struct sysc_revision_quirk *q;
1699 int i;
1700
1701 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1702 q = &sysc_revision_quirks[i];
1703
1704 if (!q->base)
1705 continue;
1706
1707 if (q->base != ddata->module_pa)
1708 continue;
1709
1710 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1711 continue;
1712
1713 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1714 continue;
1715
1716 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1717 continue;
1718
1719 ddata->name = q->name;
1720 ddata->cfg.quirks |= q->quirks;
1721 }
1722 }
1723
1724 /* Quirks that also consider the revision register value */
1725 static void sysc_init_revision_quirks(struct sysc *ddata)
1726 {
1727 const struct sysc_revision_quirk *q;
1728 int i;
1729
1730 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1731 q = &sysc_revision_quirks[i];
1732
1733 if (q->base && q->base != ddata->module_pa)
1734 continue;
1735
1736 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1737 continue;
1738
1739 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1740 continue;
1741
1742 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1743 continue;
1744
1745 if (q->revision == ddata->revision ||
1746 (q->revision & q->revision_mask) ==
1747 (ddata->revision & q->revision_mask)) {
1748 ddata->name = q->name;
1749 ddata->cfg.quirks |= q->quirks;
1750 }
1751 }
1752 }
1753
1754 /*
1755 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1756 * enabled DSS interrupts. Eventually we may be able to do this on
1757 * dispc init rather than top-level DSS init.
1758 */
1759 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1760 bool disable)
1761 {
1762 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1763 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1764 int manager_count;
1765 bool framedonetv_irq = true;
1766 u32 val, irq_mask = 0;
1767
1768 switch (sysc_soc->soc) {
1769 case SOC_2420 ... SOC_3630:
1770 manager_count = 2;
1771 framedonetv_irq = false;
1772 break;
1773 case SOC_4430 ... SOC_4470:
1774 manager_count = 3;
1775 break;
1776 case SOC_5430:
1777 case SOC_DRA7:
1778 manager_count = 4;
1779 break;
1780 case SOC_AM4:
1781 manager_count = 1;
1782 framedonetv_irq = false;
1783 break;
1784 case SOC_UNKNOWN:
1785 default:
1786 return 0;
1787 }
1788
1789 /* Remap the whole module range to be able to reset dispc outputs */
1790 devm_iounmap(ddata->dev, ddata->module_va);
1791 ddata->module_va = devm_ioremap(ddata->dev,
1792 ddata->module_pa,
1793 ddata->module_size);
1794 if (!ddata->module_va)
1795 return -EIO;
1796
1797 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */
1798 val = sysc_read(ddata, dispc_offset + 0x40);
1799 lcd_en = val & lcd_en_mask;
1800 digit_en = val & digit_en_mask;
1801 if (lcd_en)
1802 irq_mask |= BIT(0); /* FRAMEDONE */
1803 if (digit_en) {
1804 if (framedonetv_irq)
1805 irq_mask |= BIT(24); /* FRAMEDONETV */
1806 else
1807 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1808 }
1809 if (disable && (lcd_en || digit_en))
1810 sysc_write(ddata, dispc_offset + 0x40,
1811 val & ~(lcd_en_mask | digit_en_mask));
1812
1813 if (manager_count <= 2)
1814 return irq_mask;
1815
1816 /* DISPC_CONTROL2 */
1817 val = sysc_read(ddata, dispc_offset + 0x238);
1818 lcd2_en = val & lcd_en_mask;
1819 if (lcd2_en)
1820 irq_mask |= BIT(22); /* FRAMEDONE2 */
1821 if (disable && lcd2_en)
1822 sysc_write(ddata, dispc_offset + 0x238,
1823 val & ~lcd_en_mask);
1824
1825 if (manager_count <= 3)
1826 return irq_mask;
1827
1828 /* DISPC_CONTROL3 */
1829 val = sysc_read(ddata, dispc_offset + 0x848);
1830 lcd3_en = val & lcd_en_mask;
1831 if (lcd3_en)
1832 irq_mask |= BIT(30); /* FRAMEDONE3 */
1833 if (disable && lcd3_en)
1834 sysc_write(ddata, dispc_offset + 0x848,
1835 val & ~lcd_en_mask);
1836
1837 return irq_mask;
1838 }
1839
1840 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1841 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1842 {
1843 const int dispc_offset = 0x1000;
1844 int error;
1845 u32 irq_mask, val;
1846
1847 /* Get enabled outputs */
1848 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1849 if (!irq_mask)
1850 return;
1851
1852 /* Clear IRQSTATUS */
1853 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1854
1855 /* Disable outputs */
1856 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1857
1858 /* Poll IRQSTATUS */
1859 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1860 val, val != irq_mask, 100, 50);
1861 if (error)
1862 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1863 __func__, val, irq_mask);
1864
1865 if (sysc_soc->soc == SOC_3430) {
1866 /* Clear DSS_SDI_CONTROL */
1867 sysc_write(ddata, 0x44, 0);
1868
1869 /* Clear DSS_PLL_CONTROL */
1870 sysc_write(ddata, 0x48, 0);
1871 }
1872
1873 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1874 sysc_write(ddata, 0x40, 0);
1875 }
1876
1877 /* 1-wire needs module's internal clocks enabled for reset */
1878 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1879 {
1880 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1881 u16 val;
1882
1883 val = sysc_read(ddata, offset);
1884 val |= BIT(5);
1885 sysc_write(ddata, offset, val);
1886 }
1887
1888 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1889 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1890 {
1891 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1892
1893 sysc_write(ddata, offset, 1);
1894 }
1895
1896 /* I2C needs to be disabled for reset */
1897 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1898 {
1899 int offset;
1900 u16 val;
1901
1902 /* I2C_CON, omap2/3 is different from omap4 and later */
1903 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1904 offset = 0x24;
1905 else
1906 offset = 0xa4;
1907
1908 /* I2C_EN */
1909 val = sysc_read(ddata, offset);
1910 if (enable)
1911 val |= BIT(15);
1912 else
1913 val &= ~BIT(15);
1914 sysc_write(ddata, offset, val);
1915 }
1916
1917 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1918 {
1919 sysc_clk_quirk_i2c(ddata, false);
1920 }
1921
1922 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1923 {
1924 sysc_clk_quirk_i2c(ddata, true);
1925 }
1926
1927 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1928 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1929 {
1930 u32 val, kick0_val = 0, kick1_val = 0;
1931 unsigned long flags;
1932 int error;
1933
1934 if (!lock) {
1935 kick0_val = 0x83e70b13;
1936 kick1_val = 0x95a4f1e0;
1937 }
1938
1939 local_irq_save(flags);
1940 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1941 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1942 !(val & BIT(0)), 100, 50);
1943 if (error)
1944 dev_warn(ddata->dev, "rtc busy timeout\n");
1945 /* Now we have ~15 microseconds to read/write various registers */
1946 sysc_write(ddata, 0x6c, kick0_val);
1947 sysc_write(ddata, 0x70, kick1_val);
1948 local_irq_restore(flags);
1949 }
1950
1951 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1952 {
1953 sysc_quirk_rtc(ddata, false);
1954 }
1955
1956 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1957 {
1958 sysc_quirk_rtc(ddata, true);
1959 }
1960
1961 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */
1962 static void sysc_module_enable_quirk_otg(struct sysc *ddata)
1963 {
1964 int offset = 0x414; /* OTG_FORCESTDBY */
1965
1966 sysc_write(ddata, offset, 0);
1967 }
1968
1969 static void sysc_module_disable_quirk_otg(struct sysc *ddata)
1970 {
1971 int offset = 0x414; /* OTG_FORCESTDBY */
1972 u32 val = BIT(0); /* ENABLEFORCE */
1973
1974 sysc_write(ddata, offset, val);
1975 }
1976
1977 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1978 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1979 {
1980 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1981 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1982
1983 sysc_write(ddata, offset, val);
1984 }
1985
1986 /* Watchdog timer needs a disable sequence after reset */
1987 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1988 {
1989 int wps, spr, error;
1990 u32 val;
1991
1992 wps = 0x34;
1993 spr = 0x48;
1994
1995 sysc_write(ddata, spr, 0xaaaa);
1996 error = readl_poll_timeout(ddata->module_va + wps, val,
1997 !(val & 0x10), 100,
1998 MAX_MODULE_SOFTRESET_WAIT);
1999 if (error)
2000 dev_warn(ddata->dev, "wdt disable step1 failed\n");
2001
2002 sysc_write(ddata, spr, 0x5555);
2003 error = readl_poll_timeout(ddata->module_va + wps, val,
2004 !(val & 0x10), 100,
2005 MAX_MODULE_SOFTRESET_WAIT);
2006 if (error)
2007 dev_warn(ddata->dev, "wdt disable step2 failed\n");
2008 }
2009
2010 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
2011 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
2012 {
2013 u32 reg;
2014
2015 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2016 reg |= SYSC_PRUSS_STANDBY_INIT;
2017 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2018 }
2019
2020 static void sysc_init_module_quirks(struct sysc *ddata)
2021 {
2022 if (ddata->legacy_mode || !ddata->name)
2023 return;
2024
2025 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
2026 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
2027
2028 return;
2029 }
2030
2031 #ifdef CONFIG_OMAP_GPMC_DEBUG
2032 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2033 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
2034
2035 return;
2036 }
2037 #endif
2038
2039 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2040 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2041 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2042
2043 return;
2044 }
2045
2046 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2047 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2048
2049 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2050 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2051
2052 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2053 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2054 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2055
2056 return;
2057 }
2058
2059 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) {
2060 ddata->module_enable_quirk = sysc_module_enable_quirk_otg;
2061 ddata->module_disable_quirk = sysc_module_disable_quirk_otg;
2062 }
2063
2064 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2065 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2066
2067 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2068 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2069 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2070 }
2071
2072 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2073 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2074 }
2075
2076 static int sysc_clockdomain_init(struct sysc *ddata)
2077 {
2078 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2079 struct clk *fck = NULL, *ick = NULL;
2080 int error;
2081
2082 if (!pdata || !pdata->init_clockdomain)
2083 return 0;
2084
2085 switch (ddata->nr_clocks) {
2086 case 2:
2087 ick = ddata->clocks[SYSC_ICK];
2088 fallthrough;
2089 case 1:
2090 fck = ddata->clocks[SYSC_FCK];
2091 break;
2092 case 0:
2093 return 0;
2094 }
2095
2096 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2097 if (!error || error == -ENODEV)
2098 return 0;
2099
2100 return error;
2101 }
2102
2103 /*
2104 * Note that pdata->init_module() typically does a reset first. After
2105 * pdata->init_module() is done, PM runtime can be used for the interconnect
2106 * target module.
2107 */
2108 static int sysc_legacy_init(struct sysc *ddata)
2109 {
2110 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2111 int error;
2112
2113 if (!pdata || !pdata->init_module)
2114 return 0;
2115
2116 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2117 if (error == -EEXIST)
2118 error = 0;
2119
2120 return error;
2121 }
2122
2123 /*
2124 * Note that the caller must ensure the interconnect target module is enabled
2125 * before calling reset. Otherwise reset will not complete.
2126 */
2127 static int sysc_reset(struct sysc *ddata)
2128 {
2129 int sysc_offset, sysc_val, error;
2130 u32 sysc_mask;
2131
2132 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2133
2134 if (ddata->legacy_mode ||
2135 ddata->cap->regbits->srst_shift < 0 ||
2136 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2137 return 0;
2138
2139 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2140
2141 if (ddata->pre_reset_quirk)
2142 ddata->pre_reset_quirk(ddata);
2143
2144 if (sysc_offset >= 0) {
2145 sysc_val = sysc_read_sysconfig(ddata);
2146 sysc_val |= sysc_mask;
2147 sysc_write(ddata, sysc_offset, sysc_val);
2148 /* Flush posted write */
2149 sysc_val = sysc_read_sysconfig(ddata);
2150 }
2151
2152 if (ddata->cfg.srst_udelay)
2153 usleep_range(ddata->cfg.srst_udelay,
2154 ddata->cfg.srst_udelay * 2);
2155
2156 if (ddata->post_reset_quirk)
2157 ddata->post_reset_quirk(ddata);
2158
2159 error = sysc_wait_softreset(ddata);
2160 if (error)
2161 dev_warn(ddata->dev, "OCP softreset timed out\n");
2162
2163 if (ddata->reset_done_quirk)
2164 ddata->reset_done_quirk(ddata);
2165
2166 return error;
2167 }
2168
2169 /*
2170 * At this point the module is configured enough to read the revision but
2171 * module may not be completely configured yet to use PM runtime. Enable
2172 * all clocks directly during init to configure the quirks needed for PM
2173 * runtime based on the revision register.
2174 */
2175 static int sysc_init_module(struct sysc *ddata)
2176 {
2177 bool rstctrl_deasserted = false;
2178 int error = 0;
2179
2180 error = sysc_clockdomain_init(ddata);
2181 if (error)
2182 return error;
2183
2184 sysc_clkdm_deny_idle(ddata);
2185
2186 /*
2187 * Always enable clocks. The bootloader may or may not have enabled
2188 * the related clocks.
2189 */
2190 error = sysc_enable_opt_clocks(ddata);
2191 if (error)
2192 return error;
2193
2194 error = sysc_enable_main_clocks(ddata);
2195 if (error)
2196 goto err_opt_clocks;
2197
2198 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2199 error = reset_control_deassert(ddata->rsts);
2200 if (error)
2201 goto err_main_clocks;
2202 rstctrl_deasserted = true;
2203 }
2204
2205 ddata->revision = sysc_read_revision(ddata);
2206 sysc_init_revision_quirks(ddata);
2207 sysc_init_module_quirks(ddata);
2208
2209 if (ddata->legacy_mode) {
2210 error = sysc_legacy_init(ddata);
2211 if (error)
2212 goto err_main_clocks;
2213 }
2214
2215 if (!ddata->legacy_mode) {
2216 error = sysc_enable_module(ddata->dev);
2217 if (error)
2218 goto err_main_clocks;
2219 }
2220
2221 error = sysc_reset(ddata);
2222 if (error)
2223 dev_err(ddata->dev, "Reset failed with %d\n", error);
2224
2225 if (error && !ddata->legacy_mode)
2226 sysc_disable_module(ddata->dev);
2227
2228 err_main_clocks:
2229 if (error)
2230 sysc_disable_main_clocks(ddata);
2231 err_opt_clocks:
2232 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2233 if (error) {
2234 sysc_disable_opt_clocks(ddata);
2235 sysc_clkdm_allow_idle(ddata);
2236 }
2237
2238 if (error && rstctrl_deasserted &&
2239 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2240 reset_control_assert(ddata->rsts);
2241
2242 return error;
2243 }
2244
2245 static int sysc_init_sysc_mask(struct sysc *ddata)
2246 {
2247 struct device_node *np = ddata->dev->of_node;
2248 int error;
2249 u32 val;
2250
2251 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2252 if (error)
2253 return 0;
2254
2255 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2256
2257 return 0;
2258 }
2259
2260 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2261 const char *name)
2262 {
2263 struct device_node *np = ddata->dev->of_node;
2264 struct property *prop;
2265 const __be32 *p;
2266 u32 val;
2267
2268 of_property_for_each_u32(np, name, prop, p, val) {
2269 if (val >= SYSC_NR_IDLEMODES) {
2270 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2271 return -EINVAL;
2272 }
2273 *idlemodes |= (1 << val);
2274 }
2275
2276 return 0;
2277 }
2278
2279 static int sysc_init_idlemodes(struct sysc *ddata)
2280 {
2281 int error;
2282
2283 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2284 "ti,sysc-midle");
2285 if (error)
2286 return error;
2287
2288 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2289 "ti,sysc-sidle");
2290 if (error)
2291 return error;
2292
2293 return 0;
2294 }
2295
2296 /*
2297 * Only some devices on omap4 and later have SYSCONFIG reset done
2298 * bit. We can detect this if there is no SYSSTATUS at all, or the
2299 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2300 * have multiple bits for the child devices like OHCI and EHCI.
2301 * Depends on SYSC being parsed first.
2302 */
2303 static int sysc_init_syss_mask(struct sysc *ddata)
2304 {
2305 struct device_node *np = ddata->dev->of_node;
2306 int error;
2307 u32 val;
2308
2309 error = of_property_read_u32(np, "ti,syss-mask", &val);
2310 if (error) {
2311 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2312 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2313 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2314 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2315
2316 return 0;
2317 }
2318
2319 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2320 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2321
2322 ddata->cfg.syss_mask = val;
2323
2324 return 0;
2325 }
2326
2327 /*
2328 * Many child device drivers need to have fck and opt clocks available
2329 * to get the clock rate for device internal configuration etc.
2330 */
2331 static int sysc_child_add_named_clock(struct sysc *ddata,
2332 struct device *child,
2333 const char *name)
2334 {
2335 struct clk *clk;
2336 struct clk_lookup *l;
2337 int error = 0;
2338
2339 if (!name)
2340 return 0;
2341
2342 clk = clk_get(child, name);
2343 if (!IS_ERR(clk)) {
2344 error = -EEXIST;
2345 goto put_clk;
2346 }
2347
2348 clk = clk_get(ddata->dev, name);
2349 if (IS_ERR(clk))
2350 return -ENODEV;
2351
2352 l = clkdev_create(clk, name, dev_name(child));
2353 if (!l)
2354 error = -ENOMEM;
2355 put_clk:
2356 clk_put(clk);
2357
2358 return error;
2359 }
2360
2361 static int sysc_child_add_clocks(struct sysc *ddata,
2362 struct device *child)
2363 {
2364 int i, error;
2365
2366 for (i = 0; i < ddata->nr_clocks; i++) {
2367 error = sysc_child_add_named_clock(ddata,
2368 child,
2369 ddata->clock_roles[i]);
2370 if (error && error != -EEXIST) {
2371 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2372 ddata->clock_roles[i], error);
2373
2374 return error;
2375 }
2376 }
2377
2378 return 0;
2379 }
2380
2381 static struct device_type sysc_device_type = {
2382 };
2383
2384 static struct sysc *sysc_child_to_parent(struct device *dev)
2385 {
2386 struct device *parent = dev->parent;
2387
2388 if (!parent || parent->type != &sysc_device_type)
2389 return NULL;
2390
2391 return dev_get_drvdata(parent);
2392 }
2393
2394 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2395 {
2396 struct sysc *ddata;
2397 int error;
2398
2399 ddata = sysc_child_to_parent(dev);
2400
2401 error = pm_generic_runtime_suspend(dev);
2402 if (error)
2403 return error;
2404
2405 if (!ddata->enabled)
2406 return 0;
2407
2408 return sysc_runtime_suspend(ddata->dev);
2409 }
2410
2411 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2412 {
2413 struct sysc *ddata;
2414 int error;
2415
2416 ddata = sysc_child_to_parent(dev);
2417
2418 if (!ddata->enabled) {
2419 error = sysc_runtime_resume(ddata->dev);
2420 if (error < 0)
2421 dev_err(ddata->dev,
2422 "%s error: %i\n", __func__, error);
2423 }
2424
2425 return pm_generic_runtime_resume(dev);
2426 }
2427
2428 #ifdef CONFIG_PM_SLEEP
2429 static int sysc_child_suspend_noirq(struct device *dev)
2430 {
2431 struct sysc *ddata;
2432 int error;
2433
2434 ddata = sysc_child_to_parent(dev);
2435
2436 dev_dbg(ddata->dev, "%s %s\n", __func__,
2437 ddata->name ? ddata->name : "");
2438
2439 error = pm_generic_suspend_noirq(dev);
2440 if (error) {
2441 dev_err(dev, "%s error at %i: %i\n",
2442 __func__, __LINE__, error);
2443
2444 return error;
2445 }
2446
2447 if (!pm_runtime_status_suspended(dev)) {
2448 error = pm_generic_runtime_suspend(dev);
2449 if (error) {
2450 dev_dbg(dev, "%s busy at %i: %i\n",
2451 __func__, __LINE__, error);
2452
2453 return 0;
2454 }
2455
2456 error = sysc_runtime_suspend(ddata->dev);
2457 if (error) {
2458 dev_err(dev, "%s error at %i: %i\n",
2459 __func__, __LINE__, error);
2460
2461 return error;
2462 }
2463
2464 ddata->child_needs_resume = true;
2465 }
2466
2467 return 0;
2468 }
2469
2470 static int sysc_child_resume_noirq(struct device *dev)
2471 {
2472 struct sysc *ddata;
2473 int error;
2474
2475 ddata = sysc_child_to_parent(dev);
2476
2477 dev_dbg(ddata->dev, "%s %s\n", __func__,
2478 ddata->name ? ddata->name : "");
2479
2480 if (ddata->child_needs_resume) {
2481 ddata->child_needs_resume = false;
2482
2483 error = sysc_runtime_resume(ddata->dev);
2484 if (error)
2485 dev_err(ddata->dev,
2486 "%s runtime resume error: %i\n",
2487 __func__, error);
2488
2489 error = pm_generic_runtime_resume(dev);
2490 if (error)
2491 dev_err(ddata->dev,
2492 "%s generic runtime resume: %i\n",
2493 __func__, error);
2494 }
2495
2496 return pm_generic_resume_noirq(dev);
2497 }
2498 #endif
2499
2500 static struct dev_pm_domain sysc_child_pm_domain = {
2501 .ops = {
2502 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2503 sysc_child_runtime_resume,
2504 NULL)
2505 USE_PLATFORM_PM_SLEEP_OPS
2506 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2507 sysc_child_resume_noirq)
2508 }
2509 };
2510
2511 /* Caller needs to take list_lock if ever used outside of cpu_pm */
2512 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2513 {
2514 struct sysc_module *module;
2515 struct sysc *ddata;
2516
2517 list_for_each_entry(module, &sysc_soc->restored_modules, node) {
2518 ddata = module->ddata;
2519 sysc_reinit_module(ddata, ddata->enabled);
2520 }
2521 }
2522
2523 /**
2524 * sysc_context_notifier - optionally reset and restore module after idle
2525 * @nb: notifier block
2526 * @cmd: unused
2527 * @v: unused
2528 *
2529 * Some interconnect target modules need to be restored, or reset and restored
2530 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2531 * OTG and GPMC target modules even if the modules are unused.
2532 */
2533 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2534 void *v)
2535 {
2536 struct sysc_soc_info *soc;
2537
2538 soc = container_of(nb, struct sysc_soc_info, nb);
2539
2540 switch (cmd) {
2541 case CPU_CLUSTER_PM_ENTER:
2542 break;
2543 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2544 break;
2545 case CPU_CLUSTER_PM_EXIT:
2546 sysc_reinit_modules(soc);
2547 break;
2548 }
2549
2550 return NOTIFY_OK;
2551 }
2552
2553 /**
2554 * sysc_add_restored - optionally add reset and restore quirk hanlling
2555 * @ddata: device data
2556 */
2557 static void sysc_add_restored(struct sysc *ddata)
2558 {
2559 struct sysc_module *restored_module;
2560
2561 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2562 if (!restored_module)
2563 return;
2564
2565 restored_module->ddata = ddata;
2566
2567 mutex_lock(&sysc_soc->list_lock);
2568
2569 list_add(&restored_module->node, &sysc_soc->restored_modules);
2570
2571 if (sysc_soc->nb.notifier_call)
2572 goto out_unlock;
2573
2574 sysc_soc->nb.notifier_call = sysc_context_notifier;
2575 cpu_pm_register_notifier(&sysc_soc->nb);
2576
2577 out_unlock:
2578 mutex_unlock(&sysc_soc->list_lock);
2579 }
2580
2581 /**
2582 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2583 * @ddata: device driver data
2584 * @child: child device driver
2585 *
2586 * Allow idle for child devices as done with _od_runtime_suspend().
2587 * Otherwise many child devices will not idle because of the permanent
2588 * parent usecount set in pm_runtime_irq_safe().
2589 *
2590 * Note that the long term solution is to just modify the child device
2591 * drivers to not set pm_runtime_irq_safe() and then this can be just
2592 * dropped.
2593 */
2594 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2595 {
2596 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2597 dev_pm_domain_set(child, &sysc_child_pm_domain);
2598 }
2599
2600 static int sysc_notifier_call(struct notifier_block *nb,
2601 unsigned long event, void *device)
2602 {
2603 struct device *dev = device;
2604 struct sysc *ddata;
2605 int error;
2606
2607 ddata = sysc_child_to_parent(dev);
2608 if (!ddata)
2609 return NOTIFY_DONE;
2610
2611 switch (event) {
2612 case BUS_NOTIFY_ADD_DEVICE:
2613 error = sysc_child_add_clocks(ddata, dev);
2614 if (error)
2615 return error;
2616 sysc_legacy_idle_quirk(ddata, dev);
2617 break;
2618 default:
2619 break;
2620 }
2621
2622 return NOTIFY_DONE;
2623 }
2624
2625 static struct notifier_block sysc_nb = {
2626 .notifier_call = sysc_notifier_call,
2627 };
2628
2629 /* Device tree configured quirks */
2630 struct sysc_dts_quirk {
2631 const char *name;
2632 u32 mask;
2633 };
2634
2635 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2636 { .name = "ti,no-idle-on-init",
2637 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2638 { .name = "ti,no-reset-on-init",
2639 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2640 { .name = "ti,no-idle",
2641 .mask = SYSC_QUIRK_NO_IDLE, },
2642 };
2643
2644 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2645 bool is_child)
2646 {
2647 const struct property *prop;
2648 int i, len;
2649
2650 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2651 const char *name = sysc_dts_quirks[i].name;
2652
2653 prop = of_get_property(np, name, &len);
2654 if (!prop)
2655 continue;
2656
2657 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2658 if (is_child) {
2659 dev_warn(ddata->dev,
2660 "dts flag should be at module level for %s\n",
2661 name);
2662 }
2663 }
2664 }
2665
2666 static int sysc_init_dts_quirks(struct sysc *ddata)
2667 {
2668 struct device_node *np = ddata->dev->of_node;
2669 int error;
2670 u32 val;
2671
2672 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2673
2674 sysc_parse_dts_quirks(ddata, np, false);
2675 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2676 if (!error) {
2677 if (val > 255) {
2678 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2679 val);
2680 }
2681
2682 ddata->cfg.srst_udelay = (u8)val;
2683 }
2684
2685 return 0;
2686 }
2687
2688 static void sysc_unprepare(struct sysc *ddata)
2689 {
2690 int i;
2691
2692 if (!ddata->clocks)
2693 return;
2694
2695 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2696 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2697 clk_unprepare(ddata->clocks[i]);
2698 }
2699 }
2700
2701 /*
2702 * Common sysc register bits found on omap2, also known as type1
2703 */
2704 static const struct sysc_regbits sysc_regbits_omap2 = {
2705 .dmadisable_shift = -ENODEV,
2706 .midle_shift = 12,
2707 .sidle_shift = 3,
2708 .clkact_shift = 8,
2709 .emufree_shift = 5,
2710 .enwkup_shift = 2,
2711 .srst_shift = 1,
2712 .autoidle_shift = 0,
2713 };
2714
2715 static const struct sysc_capabilities sysc_omap2 = {
2716 .type = TI_SYSC_OMAP2,
2717 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2718 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2719 SYSC_OMAP2_AUTOIDLE,
2720 .regbits = &sysc_regbits_omap2,
2721 };
2722
2723 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2724 static const struct sysc_capabilities sysc_omap2_timer = {
2725 .type = TI_SYSC_OMAP2_TIMER,
2726 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2727 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2728 SYSC_OMAP2_AUTOIDLE,
2729 .regbits = &sysc_regbits_omap2,
2730 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2731 };
2732
2733 /*
2734 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2735 * with different sidle position
2736 */
2737 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2738 .dmadisable_shift = -ENODEV,
2739 .midle_shift = -ENODEV,
2740 .sidle_shift = 4,
2741 .clkact_shift = -ENODEV,
2742 .enwkup_shift = -ENODEV,
2743 .srst_shift = 1,
2744 .autoidle_shift = 0,
2745 .emufree_shift = -ENODEV,
2746 };
2747
2748 static const struct sysc_capabilities sysc_omap3_sham = {
2749 .type = TI_SYSC_OMAP3_SHAM,
2750 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2751 .regbits = &sysc_regbits_omap3_sham,
2752 };
2753
2754 /*
2755 * AES register bits found on omap3 and later, a variant of
2756 * sysc_regbits_omap2 with different sidle position
2757 */
2758 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2759 .dmadisable_shift = -ENODEV,
2760 .midle_shift = -ENODEV,
2761 .sidle_shift = 6,
2762 .clkact_shift = -ENODEV,
2763 .enwkup_shift = -ENODEV,
2764 .srst_shift = 1,
2765 .autoidle_shift = 0,
2766 .emufree_shift = -ENODEV,
2767 };
2768
2769 static const struct sysc_capabilities sysc_omap3_aes = {
2770 .type = TI_SYSC_OMAP3_AES,
2771 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2772 .regbits = &sysc_regbits_omap3_aes,
2773 };
2774
2775 /*
2776 * Common sysc register bits found on omap4, also known as type2
2777 */
2778 static const struct sysc_regbits sysc_regbits_omap4 = {
2779 .dmadisable_shift = 16,
2780 .midle_shift = 4,
2781 .sidle_shift = 2,
2782 .clkact_shift = -ENODEV,
2783 .enwkup_shift = -ENODEV,
2784 .emufree_shift = 1,
2785 .srst_shift = 0,
2786 .autoidle_shift = -ENODEV,
2787 };
2788
2789 static const struct sysc_capabilities sysc_omap4 = {
2790 .type = TI_SYSC_OMAP4,
2791 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2792 SYSC_OMAP4_SOFTRESET,
2793 .regbits = &sysc_regbits_omap4,
2794 };
2795
2796 static const struct sysc_capabilities sysc_omap4_timer = {
2797 .type = TI_SYSC_OMAP4_TIMER,
2798 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2799 SYSC_OMAP4_SOFTRESET,
2800 .regbits = &sysc_regbits_omap4,
2801 };
2802
2803 /*
2804 * Common sysc register bits found on omap4, also known as type3
2805 */
2806 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2807 .dmadisable_shift = -ENODEV,
2808 .midle_shift = 2,
2809 .sidle_shift = 0,
2810 .clkact_shift = -ENODEV,
2811 .enwkup_shift = -ENODEV,
2812 .srst_shift = -ENODEV,
2813 .emufree_shift = -ENODEV,
2814 .autoidle_shift = -ENODEV,
2815 };
2816
2817 static const struct sysc_capabilities sysc_omap4_simple = {
2818 .type = TI_SYSC_OMAP4_SIMPLE,
2819 .regbits = &sysc_regbits_omap4_simple,
2820 };
2821
2822 /*
2823 * SmartReflex sysc found on omap34xx
2824 */
2825 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2826 .dmadisable_shift = -ENODEV,
2827 .midle_shift = -ENODEV,
2828 .sidle_shift = -ENODEV,
2829 .clkact_shift = 20,
2830 .enwkup_shift = -ENODEV,
2831 .srst_shift = -ENODEV,
2832 .emufree_shift = -ENODEV,
2833 .autoidle_shift = -ENODEV,
2834 };
2835
2836 static const struct sysc_capabilities sysc_34xx_sr = {
2837 .type = TI_SYSC_OMAP34XX_SR,
2838 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2839 .regbits = &sysc_regbits_omap34xx_sr,
2840 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2841 SYSC_QUIRK_LEGACY_IDLE,
2842 };
2843
2844 /*
2845 * SmartReflex sysc found on omap36xx and later
2846 */
2847 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2848 .dmadisable_shift = -ENODEV,
2849 .midle_shift = -ENODEV,
2850 .sidle_shift = 24,
2851 .clkact_shift = -ENODEV,
2852 .enwkup_shift = 26,
2853 .srst_shift = -ENODEV,
2854 .emufree_shift = -ENODEV,
2855 .autoidle_shift = -ENODEV,
2856 };
2857
2858 static const struct sysc_capabilities sysc_36xx_sr = {
2859 .type = TI_SYSC_OMAP36XX_SR,
2860 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2861 .regbits = &sysc_regbits_omap36xx_sr,
2862 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2863 };
2864
2865 static const struct sysc_capabilities sysc_omap4_sr = {
2866 .type = TI_SYSC_OMAP4_SR,
2867 .regbits = &sysc_regbits_omap36xx_sr,
2868 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2869 };
2870
2871 /*
2872 * McASP register bits found on omap4 and later
2873 */
2874 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2875 .dmadisable_shift = -ENODEV,
2876 .midle_shift = -ENODEV,
2877 .sidle_shift = 0,
2878 .clkact_shift = -ENODEV,
2879 .enwkup_shift = -ENODEV,
2880 .srst_shift = -ENODEV,
2881 .emufree_shift = -ENODEV,
2882 .autoidle_shift = -ENODEV,
2883 };
2884
2885 static const struct sysc_capabilities sysc_omap4_mcasp = {
2886 .type = TI_SYSC_OMAP4_MCASP,
2887 .regbits = &sysc_regbits_omap4_mcasp,
2888 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2889 };
2890
2891 /*
2892 * McASP found on dra7 and later
2893 */
2894 static const struct sysc_capabilities sysc_dra7_mcasp = {
2895 .type = TI_SYSC_OMAP4_SIMPLE,
2896 .regbits = &sysc_regbits_omap4_simple,
2897 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2898 };
2899
2900 /*
2901 * FS USB host found on omap4 and later
2902 */
2903 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2904 .dmadisable_shift = -ENODEV,
2905 .midle_shift = -ENODEV,
2906 .sidle_shift = 24,
2907 .clkact_shift = -ENODEV,
2908 .enwkup_shift = 26,
2909 .srst_shift = -ENODEV,
2910 .emufree_shift = -ENODEV,
2911 .autoidle_shift = -ENODEV,
2912 };
2913
2914 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2915 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2916 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2917 .regbits = &sysc_regbits_omap4_usb_host_fs,
2918 };
2919
2920 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2921 .dmadisable_shift = -ENODEV,
2922 .midle_shift = -ENODEV,
2923 .sidle_shift = -ENODEV,
2924 .clkact_shift = -ENODEV,
2925 .enwkup_shift = 4,
2926 .srst_shift = 0,
2927 .emufree_shift = -ENODEV,
2928 .autoidle_shift = -ENODEV,
2929 };
2930
2931 static const struct sysc_capabilities sysc_dra7_mcan = {
2932 .type = TI_SYSC_DRA7_MCAN,
2933 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2934 .regbits = &sysc_regbits_dra7_mcan,
2935 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2936 };
2937
2938 /*
2939 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2940 */
2941 static const struct sysc_capabilities sysc_pruss = {
2942 .type = TI_SYSC_PRUSS,
2943 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2944 .regbits = &sysc_regbits_omap4_simple,
2945 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2946 };
2947
2948 static int sysc_init_pdata(struct sysc *ddata)
2949 {
2950 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2951 struct ti_sysc_module_data *mdata;
2952
2953 if (!pdata)
2954 return 0;
2955
2956 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2957 if (!mdata)
2958 return -ENOMEM;
2959
2960 if (ddata->legacy_mode) {
2961 mdata->name = ddata->legacy_mode;
2962 mdata->module_pa = ddata->module_pa;
2963 mdata->module_size = ddata->module_size;
2964 mdata->offsets = ddata->offsets;
2965 mdata->nr_offsets = SYSC_MAX_REGS;
2966 mdata->cap = ddata->cap;
2967 mdata->cfg = &ddata->cfg;
2968 }
2969
2970 ddata->mdata = mdata;
2971
2972 return 0;
2973 }
2974
2975 static int sysc_init_match(struct sysc *ddata)
2976 {
2977 const struct sysc_capabilities *cap;
2978
2979 cap = of_device_get_match_data(ddata->dev);
2980 if (!cap)
2981 return -EINVAL;
2982
2983 ddata->cap = cap;
2984 if (ddata->cap)
2985 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2986
2987 return 0;
2988 }
2989
2990 static void ti_sysc_idle(struct work_struct *work)
2991 {
2992 struct sysc *ddata;
2993
2994 ddata = container_of(work, struct sysc, idle_work.work);
2995
2996 /*
2997 * One time decrement of clock usage counts if left on from init.
2998 * Note that we disable opt clocks unconditionally in this case
2999 * as they are enabled unconditionally during init without
3000 * considering sysc_opt_clks_needed() at that point.
3001 */
3002 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3003 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
3004 sysc_disable_main_clocks(ddata);
3005 sysc_disable_opt_clocks(ddata);
3006 sysc_clkdm_allow_idle(ddata);
3007 }
3008
3009 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
3010 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
3011 return;
3012
3013 /*
3014 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
3015 * and SYSC_QUIRK_NO_RESET_ON_INIT
3016 */
3017 if (pm_runtime_active(ddata->dev))
3018 pm_runtime_put_sync(ddata->dev);
3019 }
3020
3021 /*
3022 * SoC model and features detection. Only needed for SoCs that need
3023 * special handling for quirks, no need to list others.
3024 */
3025 static const struct soc_device_attribute sysc_soc_match[] = {
3026 SOC_FLAG("OMAP242*", SOC_2420),
3027 SOC_FLAG("OMAP243*", SOC_2430),
3028 SOC_FLAG("OMAP3[45]*", SOC_3430),
3029 SOC_FLAG("OMAP3[67]*", SOC_3630),
3030 SOC_FLAG("OMAP443*", SOC_4430),
3031 SOC_FLAG("OMAP446*", SOC_4460),
3032 SOC_FLAG("OMAP447*", SOC_4470),
3033 SOC_FLAG("OMAP54*", SOC_5430),
3034 SOC_FLAG("AM433", SOC_AM3),
3035 SOC_FLAG("AM43*", SOC_AM4),
3036 SOC_FLAG("DRA7*", SOC_DRA7),
3037
3038 { /* sentinel */ }
3039 };
3040
3041 /*
3042 * List of SoCs variants with disabled features. By default we assume all
3043 * devices in the device tree are available so no need to list those SoCs.
3044 */
3045 static const struct soc_device_attribute sysc_soc_feat_match[] = {
3046 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
3047 SOC_FLAG("AM3505", DIS_SGX),
3048 SOC_FLAG("OMAP3525", DIS_SGX),
3049 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
3050 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
3051
3052 /* OMAP3630/DM3730 variants with some accelerators disabled */
3053 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
3054 SOC_FLAG("DM3725", DIS_SGX),
3055 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
3056 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
3057 SOC_FLAG("OMAP3621", DIS_ISP),
3058
3059 { /* sentinel */ }
3060 };
3061
3062 static int sysc_add_disabled(unsigned long base)
3063 {
3064 struct sysc_address *disabled_module;
3065
3066 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
3067 if (!disabled_module)
3068 return -ENOMEM;
3069
3070 disabled_module->base = base;
3071
3072 mutex_lock(&sysc_soc->list_lock);
3073 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3074 mutex_unlock(&sysc_soc->list_lock);
3075
3076 return 0;
3077 }
3078
3079 /*
3080 * One time init to detect the booted SoC, disable unavailable features
3081 * and initialize list for optional cpu_pm notifier.
3082 *
3083 * Note that we initialize static data shared across all ti-sysc instances
3084 * so ddata is only used for SoC type. This can be called from module_init
3085 * once we no longer need to rely on platform data.
3086 */
3087 static int sysc_init_static_data(struct sysc *ddata)
3088 {
3089 const struct soc_device_attribute *match;
3090 struct ti_sysc_platform_data *pdata;
3091 unsigned long features = 0;
3092 struct device_node *np;
3093
3094 if (sysc_soc)
3095 return 0;
3096
3097 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3098 if (!sysc_soc)
3099 return -ENOMEM;
3100
3101 mutex_init(&sysc_soc->list_lock);
3102 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3103 INIT_LIST_HEAD(&sysc_soc->restored_modules);
3104 sysc_soc->general_purpose = true;
3105
3106 pdata = dev_get_platdata(ddata->dev);
3107 if (pdata && pdata->soc_type_gp)
3108 sysc_soc->general_purpose = pdata->soc_type_gp();
3109
3110 match = soc_device_match(sysc_soc_match);
3111 if (match && match->data)
3112 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3113
3114 /*
3115 * Check and warn about possible old incomplete dtb. We now want to see
3116 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3117 */
3118 switch (sysc_soc->soc) {
3119 case SOC_AM3:
3120 case SOC_AM4:
3121 case SOC_4430 ... SOC_4470:
3122 case SOC_5430:
3123 case SOC_DRA7:
3124 np = of_find_node_by_path("/ocp");
3125 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3126 "ti-sysc: Incomplete old dtb, please update\n");
3127 break;
3128 default:
3129 break;
3130 }
3131
3132 /* Ignore devices that are not available on HS and EMU SoCs */
3133 if (!sysc_soc->general_purpose) {
3134 switch (sysc_soc->soc) {
3135 case SOC_3430 ... SOC_3630:
3136 sysc_add_disabled(0x48304000); /* timer12 */
3137 break;
3138 case SOC_AM3:
3139 sysc_add_disabled(0x48310000); /* rng */
3140 break;
3141 default:
3142 break;
3143 }
3144 }
3145
3146 match = soc_device_match(sysc_soc_feat_match);
3147 if (!match)
3148 return 0;
3149
3150 if (match->data)
3151 features = (unsigned long)match->data;
3152
3153 /*
3154 * Add disabled devices to the list based on the module base.
3155 * Note that this must be done before we attempt to access the
3156 * device and have module revision checks working.
3157 */
3158 if (features & DIS_ISP)
3159 sysc_add_disabled(0x480bd400);
3160 if (features & DIS_IVA)
3161 sysc_add_disabled(0x5d000000);
3162 if (features & DIS_SGX)
3163 sysc_add_disabled(0x50000000);
3164
3165 return 0;
3166 }
3167
3168 static void sysc_cleanup_static_data(void)
3169 {
3170 struct sysc_module *restored_module;
3171 struct sysc_address *disabled_module;
3172 struct list_head *pos, *tmp;
3173
3174 if (!sysc_soc)
3175 return;
3176
3177 if (sysc_soc->nb.notifier_call)
3178 cpu_pm_unregister_notifier(&sysc_soc->nb);
3179
3180 mutex_lock(&sysc_soc->list_lock);
3181 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3182 restored_module = list_entry(pos, struct sysc_module, node);
3183 list_del(pos);
3184 kfree(restored_module);
3185 }
3186 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3187 disabled_module = list_entry(pos, struct sysc_address, node);
3188 list_del(pos);
3189 kfree(disabled_module);
3190 }
3191 mutex_unlock(&sysc_soc->list_lock);
3192 }
3193
3194 static int sysc_check_disabled_devices(struct sysc *ddata)
3195 {
3196 struct sysc_address *disabled_module;
3197 int error = 0;
3198
3199 mutex_lock(&sysc_soc->list_lock);
3200 list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) {
3201 if (ddata->module_pa == disabled_module->base) {
3202 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3203 error = -ENODEV;
3204 break;
3205 }
3206 }
3207 mutex_unlock(&sysc_soc->list_lock);
3208
3209 return error;
3210 }
3211
3212 /*
3213 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3214 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3215 * are needed, we could also look at the timer register configuration.
3216 */
3217 static int sysc_check_active_timer(struct sysc *ddata)
3218 {
3219 int error;
3220
3221 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3222 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3223 return 0;
3224
3225 /*
3226 * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3227 * Revision C and later are fixed with commit 23885389dbbb ("ARM:
3228 * dts: Fix timer regression for beagleboard revision c"). This all
3229 * can be dropped if we stop supporting old beagleboard revisions
3230 * A to B4 at some point.
3231 */
3232 if (sysc_soc->soc == SOC_3430)
3233 error = -ENXIO;
3234 else
3235 error = -EBUSY;
3236
3237 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3238 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3239 return error;
3240
3241 return 0;
3242 }
3243
3244 static const struct of_device_id sysc_match_table[] = {
3245 { .compatible = "simple-bus", },
3246 { /* sentinel */ },
3247 };
3248
3249 static int sysc_probe(struct platform_device *pdev)
3250 {
3251 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3252 struct sysc *ddata;
3253 int error;
3254
3255 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3256 if (!ddata)
3257 return -ENOMEM;
3258
3259 ddata->offsets[SYSC_REVISION] = -ENODEV;
3260 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3261 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3262 ddata->dev = &pdev->dev;
3263 platform_set_drvdata(pdev, ddata);
3264
3265 error = sysc_init_static_data(ddata);
3266 if (error)
3267 return error;
3268
3269 error = sysc_init_match(ddata);
3270 if (error)
3271 return error;
3272
3273 error = sysc_init_dts_quirks(ddata);
3274 if (error)
3275 return error;
3276
3277 error = sysc_map_and_check_registers(ddata);
3278 if (error)
3279 return error;
3280
3281 error = sysc_init_sysc_mask(ddata);
3282 if (error)
3283 return error;
3284
3285 error = sysc_init_idlemodes(ddata);
3286 if (error)
3287 return error;
3288
3289 error = sysc_init_syss_mask(ddata);
3290 if (error)
3291 return error;
3292
3293 error = sysc_init_pdata(ddata);
3294 if (error)
3295 return error;
3296
3297 sysc_init_early_quirks(ddata);
3298
3299 error = sysc_check_disabled_devices(ddata);
3300 if (error)
3301 return error;
3302
3303 error = sysc_check_active_timer(ddata);
3304 if (error == -ENXIO)
3305 ddata->reserved = true;
3306 else if (error)
3307 return error;
3308
3309 error = sysc_get_clocks(ddata);
3310 if (error)
3311 return error;
3312
3313 error = sysc_init_resets(ddata);
3314 if (error)
3315 goto unprepare;
3316
3317 error = sysc_init_module(ddata);
3318 if (error)
3319 goto unprepare;
3320
3321 pm_runtime_enable(ddata->dev);
3322 error = pm_runtime_resume_and_get(ddata->dev);
3323 if (error < 0) {
3324 pm_runtime_disable(ddata->dev);
3325 goto unprepare;
3326 }
3327
3328 /* Balance use counts as PM runtime should have enabled these all */
3329 if (!(ddata->cfg.quirks &
3330 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3331 sysc_disable_main_clocks(ddata);
3332 sysc_disable_opt_clocks(ddata);
3333 sysc_clkdm_allow_idle(ddata);
3334 }
3335
3336 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3337 reset_control_assert(ddata->rsts);
3338
3339 sysc_show_registers(ddata);
3340
3341 ddata->dev->type = &sysc_device_type;
3342
3343 if (!ddata->reserved) {
3344 error = of_platform_populate(ddata->dev->of_node,
3345 sysc_match_table,
3346 pdata ? pdata->auxdata : NULL,
3347 ddata->dev);
3348 if (error)
3349 goto err;
3350 }
3351
3352 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3353
3354 /* At least earlycon won't survive without deferred idle */
3355 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3356 SYSC_QUIRK_NO_IDLE_ON_INIT |
3357 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3358 schedule_delayed_work(&ddata->idle_work, 3000);
3359 } else {
3360 pm_runtime_put(&pdev->dev);
3361 }
3362
3363 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3364 sysc_add_restored(ddata);
3365
3366 return 0;
3367
3368 err:
3369 pm_runtime_put_sync(&pdev->dev);
3370 pm_runtime_disable(&pdev->dev);
3371 unprepare:
3372 sysc_unprepare(ddata);
3373
3374 return error;
3375 }
3376
3377 static int sysc_remove(struct platform_device *pdev)
3378 {
3379 struct sysc *ddata = platform_get_drvdata(pdev);
3380 int error;
3381
3382 /* Device can still be enabled, see deferred idle quirk in probe */
3383 if (cancel_delayed_work_sync(&ddata->idle_work))
3384 ti_sysc_idle(&ddata->idle_work.work);
3385
3386 error = pm_runtime_resume_and_get(ddata->dev);
3387 if (error < 0) {
3388 pm_runtime_disable(ddata->dev);
3389 goto unprepare;
3390 }
3391
3392 of_platform_depopulate(&pdev->dev);
3393
3394 pm_runtime_put_sync(&pdev->dev);
3395 pm_runtime_disable(&pdev->dev);
3396
3397 if (!reset_control_status(ddata->rsts))
3398 reset_control_assert(ddata->rsts);
3399
3400 unprepare:
3401 sysc_unprepare(ddata);
3402
3403 return 0;
3404 }
3405
3406 static const struct of_device_id sysc_match[] = {
3407 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3408 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3409 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3410 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3411 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3412 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3413 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3414 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3415 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3416 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3417 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3418 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3419 { .compatible = "ti,sysc-usb-host-fs",
3420 .data = &sysc_omap4_usb_host_fs, },
3421 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3422 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3423 { },
3424 };
3425 MODULE_DEVICE_TABLE(of, sysc_match);
3426
3427 static struct platform_driver sysc_driver = {
3428 .probe = sysc_probe,
3429 .remove = sysc_remove,
3430 .driver = {
3431 .name = "ti-sysc",
3432 .of_match_table = sysc_match,
3433 .pm = &sysc_pm_ops,
3434 },
3435 };
3436
3437 static int __init sysc_init(void)
3438 {
3439 bus_register_notifier(&platform_bus_type, &sysc_nb);
3440
3441 return platform_driver_register(&sysc_driver);
3442 }
3443 module_init(sysc_init);
3444
3445 static void __exit sysc_exit(void)
3446 {
3447 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3448 platform_driver_unregister(&sysc_driver);
3449 sysc_cleanup_static_data();
3450 }
3451 module_exit(sysc_exit);
3452
3453 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3454 MODULE_LICENSE("GPL v2");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git