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Patch by Michael Bendzick, 12 Jul 2004:
[people/ms/u-boot.git] / drivers / cfi_flash.c
1 /*
2 * (C) Copyright 2002-2004
3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 * Modified to work with AMD flashes
8 *
9 * Copyright (C) 2004
10 * Ed Okerson
11 * Modified to work with little-endian systems.
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 *
31 * History
32 * 01/20/2004 - combined variants of original driver.
33 * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
34 * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
35 * 01/27/2004 - Little endian support Ed Okerson
36 *
37 * Tested Architectures
38 * Port Width Chip Width # of banks Flash Chip Board
39 * 32 16 1 28F128J3 seranoa/eagle
40 * 64 16 1 28F128J3 seranoa/falcon
41 *
42 */
43
44 /* The DEBUG define must be before common to enable debugging */
45 /* #define DEBUG */
46
47 #include <common.h>
48 #include <asm/processor.h>
49 #include <asm/byteorder.h>
50 #include <linux/byteorder/swab.h>
51 #ifdef CFG_FLASH_CFI_DRIVER
52
53 /*
54 * This file implements a Common Flash Interface (CFI) driver for U-Boot.
55 * The width of the port and the width of the chips are determined at initialization.
56 * These widths are used to calculate the address for access CFI data structures.
57 * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
58 *
59 * References
60 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
61 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
62 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
63 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
64 *
65 * TODO
66 *
67 * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
68 * Table (ALT) to determine if protection is available
69 *
70 * Add support for other command sets Use the PRI and ALT to determine command set
71 * Verify erase and program timeouts.
72 */
73
74 #ifndef CFG_FLASH_BANKS_LIST
75 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
76 #endif
77
78 #define FLASH_CMD_CFI 0x98
79 #define FLASH_CMD_READ_ID 0x90
80 #define FLASH_CMD_RESET 0xff
81 #define FLASH_CMD_BLOCK_ERASE 0x20
82 #define FLASH_CMD_ERASE_CONFIRM 0xD0
83 #define FLASH_CMD_WRITE 0x40
84 #define FLASH_CMD_PROTECT 0x60
85 #define FLASH_CMD_PROTECT_SET 0x01
86 #define FLASH_CMD_PROTECT_CLEAR 0xD0
87 #define FLASH_CMD_CLEAR_STATUS 0x50
88 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
89 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
90
91 #define FLASH_STATUS_DONE 0x80
92 #define FLASH_STATUS_ESS 0x40
93 #define FLASH_STATUS_ECLBS 0x20
94 #define FLASH_STATUS_PSLBS 0x10
95 #define FLASH_STATUS_VPENS 0x08
96 #define FLASH_STATUS_PSS 0x04
97 #define FLASH_STATUS_DPS 0x02
98 #define FLASH_STATUS_R 0x01
99 #define FLASH_STATUS_PROTECT 0x01
100
101 #define AMD_CMD_RESET 0xF0
102 #define AMD_CMD_WRITE 0xA0
103 #define AMD_CMD_ERASE_START 0x80
104 #define AMD_CMD_ERASE_SECTOR 0x30
105 #define AMD_CMD_UNLOCK_START 0xAA
106 #define AMD_CMD_UNLOCK_ACK 0x55
107
108 #define AMD_STATUS_TOGGLE 0x40
109 #define AMD_STATUS_ERROR 0x20
110 #define AMD_ADDR_ERASE_START 0x555
111 #define AMD_ADDR_START 0x555
112 #define AMD_ADDR_ACK 0x2AA
113
114 #define FLASH_OFFSET_CFI 0x55
115 #define FLASH_OFFSET_CFI_RESP 0x10
116 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
117 #define FLASH_OFFSET_WTOUT 0x1F
118 #define FLASH_OFFSET_WBTOUT 0x20
119 #define FLASH_OFFSET_ETOUT 0x21
120 #define FLASH_OFFSET_CETOUT 0x22
121 #define FLASH_OFFSET_WMAX_TOUT 0x23
122 #define FLASH_OFFSET_WBMAX_TOUT 0x24
123 #define FLASH_OFFSET_EMAX_TOUT 0x25
124 #define FLASH_OFFSET_CEMAX_TOUT 0x26
125 #define FLASH_OFFSET_SIZE 0x27
126 #define FLASH_OFFSET_INTERFACE 0x28
127 #define FLASH_OFFSET_BUFFER_SIZE 0x2A
128 #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
129 #define FLASH_OFFSET_ERASE_REGIONS 0x2D
130 #define FLASH_OFFSET_PROTECT 0x02
131 #define FLASH_OFFSET_USER_PROTECTION 0x85
132 #define FLASH_OFFSET_INTEL_PROTECTION 0x81
133
134
135 #define FLASH_MAN_CFI 0x01000000
136
137 #define CFI_CMDSET_NONE 0
138 #define CFI_CMDSET_INTEL_EXTENDED 1
139 #define CFI_CMDSET_AMD_STANDARD 2
140 #define CFI_CMDSET_INTEL_STANDARD 3
141 #define CFI_CMDSET_AMD_EXTENDED 4
142 #define CFI_CMDSET_MITSU_STANDARD 256
143 #define CFI_CMDSET_MITSU_EXTENDED 257
144 #define CFI_CMDSET_SST 258
145
146
147 typedef union {
148 unsigned char c;
149 unsigned short w;
150 unsigned long l;
151 unsigned long long ll;
152 } cfiword_t;
153
154 typedef union {
155 volatile unsigned char *cp;
156 volatile unsigned short *wp;
157 volatile unsigned long *lp;
158 volatile unsigned long long *llp;
159 } cfiptr_t;
160
161 #define NUM_ERASE_REGIONS 4
162
163 static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
164
165 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
166
167 /*-----------------------------------------------------------------------
168 * Functions
169 */
170
171 typedef unsigned long flash_sect_t;
172
173 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
174 static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
175 static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
176 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
177 static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
178 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
179 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
180 static int flash_detect_cfi (flash_info_t * info);
181 static ulong flash_get_size (ulong base, int banknum);
182 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
183 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
184 ulong tout, char *prompt);
185 #ifdef CFG_FLASH_USE_BUFFER_WRITE
186 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
187 #endif
188
189 /*-----------------------------------------------------------------------
190 * create an address based on the offset and the port width
191 */
192 inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
193 {
194 return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
195 }
196
197 #ifdef DEBUG
198 /*-----------------------------------------------------------------------
199 * Debug support
200 */
201 void print_longlong (char *str, unsigned long long data)
202 {
203 int i;
204 char *cp;
205
206 cp = (unsigned char *) &data;
207 for (i = 0; i < 8; i++)
208 sprintf (&str[i * 2], "%2.2x", *cp++);
209 }
210 static void flash_printqry (flash_info_t * info, flash_sect_t sect)
211 {
212 cfiptr_t cptr;
213 int x, y;
214
215 for (x = 0; x < 0x40; x += 16 / info->portwidth) {
216 cptr.cp =
217 flash_make_addr (info, sect,
218 x + FLASH_OFFSET_CFI_RESP);
219 debug ("%p : ", cptr.cp);
220 for (y = 0; y < 16; y++) {
221 debug ("%2.2x ", cptr.cp[y]);
222 }
223 debug (" ");
224 for (y = 0; y < 16; y++) {
225 if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
226 debug ("%c", cptr.cp[y]);
227 } else {
228 debug (".");
229 }
230 }
231 debug ("\n");
232 }
233 }
234 #endif
235
236
237 /*-----------------------------------------------------------------------
238 * read a character at a port width address
239 */
240 inline uchar flash_read_uchar (flash_info_t * info, uint offset)
241 {
242 uchar *cp;
243
244 cp = flash_make_addr (info, 0, offset);
245 #if defined(__LITTLE_ENDIAN)
246 return (cp[0]);
247 #else
248 return (cp[info->portwidth - 1]);
249 #endif
250 }
251
252 /*-----------------------------------------------------------------------
253 * read a short word by swapping for ppc format.
254 */
255 ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
256 {
257 uchar *addr;
258 ushort retval;
259
260 #ifdef DEBUG
261 int x;
262 #endif
263 addr = flash_make_addr (info, sect, offset);
264
265 #ifdef DEBUG
266 debug ("ushort addr is at %p info->portwidth = %d\n", addr,
267 info->portwidth);
268 for (x = 0; x < 2 * info->portwidth; x++) {
269 debug ("addr[%x] = 0x%x\n", x, addr[x]);
270 }
271 #endif
272 #if defined(__LITTLE_ENDIAN)
273 retval = ((addr[(info->portwidth)] << 8) | addr[0]);
274 #else
275 retval = ((addr[(2 * info->portwidth) - 1] << 8) |
276 addr[info->portwidth - 1]);
277 #endif
278
279 debug ("retval = 0x%x\n", retval);
280 return retval;
281 }
282
283 /*-----------------------------------------------------------------------
284 * read a long word by picking the least significant byte of each maiximum
285 * port size word. Swap for ppc format.
286 */
287 ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
288 {
289 uchar *addr;
290 ulong retval;
291
292 #ifdef DEBUG
293 int x;
294 #endif
295 addr = flash_make_addr (info, sect, offset);
296
297 #ifdef DEBUG
298 debug ("long addr is at %p info->portwidth = %d\n", addr,
299 info->portwidth);
300 for (x = 0; x < 4 * info->portwidth; x++) {
301 debug ("addr[%x] = 0x%x\n", x, addr[x]);
302 }
303 #endif
304 #if defined(__LITTLE_ENDIAN)
305 retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
306 (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
307 #else
308 retval = (addr[(2 * info->portwidth) - 1] << 24) |
309 (addr[(info->portwidth) - 1] << 16) |
310 (addr[(4 * info->portwidth) - 1] << 8) |
311 addr[(3 * info->portwidth) - 1];
312 #endif
313 return retval;
314 }
315
316 /*-----------------------------------------------------------------------
317 */
318 unsigned long flash_init (void)
319 {
320 unsigned long size = 0;
321 int i;
322
323 /* Init: no FLASHes known */
324 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
325 flash_info[i].flash_id = FLASH_UNKNOWN;
326 size += flash_info[i].size = flash_get_size (bank_base[i], i);
327 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
328 printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
329 i, flash_info[i].size, flash_info[i].size << 20);
330 }
331 }
332
333 /* Monitor protection ON by default */
334 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
335 flash_protect (FLAG_PROTECT_SET,
336 CFG_MONITOR_BASE,
337 CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
338 &flash_info[0]);
339 #endif
340
341 return (size);
342 }
343
344 /*-----------------------------------------------------------------------
345 */
346 int flash_erase (flash_info_t * info, int s_first, int s_last)
347 {
348 int rcode = 0;
349 int prot;
350 flash_sect_t sect;
351
352 if (info->flash_id != FLASH_MAN_CFI) {
353 puts ("Can't erase unknown flash type - aborted\n");
354 return 1;
355 }
356 if ((s_first < 0) || (s_first > s_last)) {
357 puts ("- no sectors to erase\n");
358 return 1;
359 }
360
361 prot = 0;
362 for (sect = s_first; sect <= s_last; ++sect) {
363 if (info->protect[sect]) {
364 prot++;
365 }
366 }
367 if (prot) {
368 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
369 } else {
370 putc ('\n');
371 }
372
373
374 for (sect = s_first; sect <= s_last; sect++) {
375 if (info->protect[sect] == 0) { /* not protected */
376 switch (info->vendor) {
377 case CFI_CMDSET_INTEL_STANDARD:
378 case CFI_CMDSET_INTEL_EXTENDED:
379 flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
380 flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
381 flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
382 break;
383 case CFI_CMDSET_AMD_STANDARD:
384 case CFI_CMDSET_AMD_EXTENDED:
385 flash_unlock_seq (info, sect);
386 flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
387 AMD_CMD_ERASE_START);
388 flash_unlock_seq (info, sect);
389 flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
390 break;
391 default:
392 debug ("Unkown flash vendor %d\n",
393 info->vendor);
394 break;
395 }
396
397 if (flash_full_status_check
398 (info, sect, info->erase_blk_tout, "erase")) {
399 rcode = 1;
400 } else
401 putc ('.');
402 }
403 }
404 puts (" done\n");
405 return rcode;
406 }
407
408 /*-----------------------------------------------------------------------
409 */
410 void flash_print_info (flash_info_t * info)
411 {
412 int i;
413
414 if (info->flash_id != FLASH_MAN_CFI) {
415 puts ("missing or unknown FLASH type\n");
416 return;
417 }
418
419 printf ("CFI conformant FLASH (%d x %d)",
420 (info->portwidth << 3), (info->chipwidth << 3));
421 printf (" Size: %ld MB in %d Sectors\n",
422 info->size >> 20, info->sector_count);
423 printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
424 info->erase_blk_tout,
425 info->write_tout,
426 info->buffer_write_tout,
427 info->buffer_size);
428
429 puts (" Sector Start Addresses:");
430 for (i = 0; i < info->sector_count; ++i) {
431 #ifdef CFG_FLASH_EMPTY_INFO
432 int k;
433 int size;
434 int erased;
435 volatile unsigned long *flash;
436
437 /*
438 * Check if whole sector is erased
439 */
440 if (i != (info->sector_count - 1))
441 size = info->start[i + 1] - info->start[i];
442 else
443 size = info->start[0] + info->size - info->start[i];
444 erased = 1;
445 flash = (volatile unsigned long *) info->start[i];
446 size = size >> 2; /* divide by 4 for longword access */
447 for (k = 0; k < size; k++) {
448 if (*flash++ != 0xffffffff) {
449 erased = 0;
450 break;
451 }
452 }
453
454 if ((i % 5) == 0)
455 printf ("\n");
456 /* print empty and read-only info */
457 printf (" %08lX%s%s",
458 info->start[i],
459 erased ? " E" : " ",
460 info->protect[i] ? "RO " : " ");
461 #else
462 if ((i % 5) == 0)
463 printf ("\n ");
464 printf (" %08lX%s",
465 info->start[i], info->protect[i] ? " (RO)" : " ");
466 #endif
467 }
468 putc ('\n');
469 return;
470 }
471
472 /*-----------------------------------------------------------------------
473 * Copy memory to flash, returns:
474 * 0 - OK
475 * 1 - write timeout
476 * 2 - Flash not erased
477 */
478 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
479 {
480 ulong wp;
481 ulong cp;
482 int aln;
483 cfiword_t cword;
484 int i, rc;
485
486 #ifdef CFG_FLASH_USE_BUFFER_WRITE
487 int buffered_size;
488 #endif
489 /* get lower aligned address */
490 /* get lower aligned address */
491 wp = (addr & ~(info->portwidth - 1));
492
493 /* handle unaligned start */
494 if ((aln = addr - wp) != 0) {
495 cword.l = 0;
496 cp = wp;
497 for (i = 0; i < aln; ++i, ++cp)
498 flash_add_byte (info, &cword, (*(uchar *) cp));
499
500 for (; (i < info->portwidth) && (cnt > 0); i++) {
501 flash_add_byte (info, &cword, *src++);
502 cnt--;
503 cp++;
504 }
505 for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
506 flash_add_byte (info, &cword, (*(uchar *) cp));
507 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
508 return rc;
509 wp = cp;
510 }
511
512 /* handle the aligned part */
513 #ifdef CFG_FLASH_USE_BUFFER_WRITE
514 buffered_size = (info->portwidth / info->chipwidth);
515 buffered_size *= info->buffer_size;
516 while (cnt >= info->portwidth) {
517 i = buffered_size > cnt ? cnt : buffered_size;
518 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
519 return rc;
520 wp += i;
521 src += i;
522 cnt -= i;
523 }
524 #else
525 while (cnt >= info->portwidth) {
526 cword.l = 0;
527 for (i = 0; i < info->portwidth; i++) {
528 flash_add_byte (info, &cword, *src++);
529 }
530 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
531 return rc;
532 wp += info->portwidth;
533 cnt -= info->portwidth;
534 }
535 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
536 if (cnt == 0) {
537 return (0);
538 }
539
540 /*
541 * handle unaligned tail bytes
542 */
543 cword.l = 0;
544 for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
545 flash_add_byte (info, &cword, *src++);
546 --cnt;
547 }
548 for (; i < info->portwidth; ++i, ++cp) {
549 flash_add_byte (info, &cword, (*(uchar *) cp));
550 }
551
552 return flash_write_cfiword (info, wp, cword);
553 }
554
555 /*-----------------------------------------------------------------------
556 */
557 #ifdef CFG_FLASH_PROTECTION
558
559 int flash_real_protect (flash_info_t * info, long sector, int prot)
560 {
561 int retcode = 0;
562
563 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
564 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
565 if (prot)
566 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
567 else
568 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
569
570 if ((retcode =
571 flash_full_status_check (info, sector, info->erase_blk_tout,
572 prot ? "protect" : "unprotect")) == 0) {
573
574 info->protect[sector] = prot;
575 /* Intel's unprotect unprotects all locking */
576 if (prot == 0) {
577 flash_sect_t i;
578
579 for (i = 0; i < info->sector_count; i++) {
580 if (info->protect[i])
581 flash_real_protect (info, i, 1);
582 }
583 }
584 }
585 return retcode;
586 }
587
588 /*-----------------------------------------------------------------------
589 * flash_read_user_serial - read the OneTimeProgramming cells
590 */
591 void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
592 int len)
593 {
594 uchar *src;
595 uchar *dst;
596
597 dst = buffer;
598 src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
599 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
600 memcpy (dst, src + offset, len);
601 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
602 }
603
604 /*
605 * flash_read_factory_serial - read the device Id from the protection area
606 */
607 void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
608 int len)
609 {
610 uchar *src;
611
612 src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
613 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
614 memcpy (buffer, src + offset, len);
615 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
616 }
617
618 #endif /* CFG_FLASH_PROTECTION */
619
620 /*
621 * flash_is_busy - check to see if the flash is busy
622 * This routine checks the status of the chip and returns true if the chip is busy
623 */
624 static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
625 {
626 int retval;
627
628 switch (info->vendor) {
629 case CFI_CMDSET_INTEL_STANDARD:
630 case CFI_CMDSET_INTEL_EXTENDED:
631 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
632 break;
633 case CFI_CMDSET_AMD_STANDARD:
634 case CFI_CMDSET_AMD_EXTENDED:
635 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
636 break;
637 default:
638 retval = 0;
639 }
640 debug ("flash_is_busy: %d\n", retval);
641 return retval;
642 }
643
644 /*-----------------------------------------------------------------------
645 * wait for XSR.7 to be set. Time out with an error if it does not.
646 * This routine does not set the flash to read-array mode.
647 */
648 static int flash_status_check (flash_info_t * info, flash_sect_t sector,
649 ulong tout, char *prompt)
650 {
651 ulong start;
652
653 /* Wait for command completion */
654 start = get_timer (0);
655 while (flash_is_busy (info, sector)) {
656 if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
657 printf ("Flash %s timeout at address %lx data %lx\n",
658 prompt, info->start[sector],
659 flash_read_long (info, sector, 0));
660 flash_write_cmd (info, sector, 0, info->cmd_reset);
661 return ERR_TIMOUT;
662 }
663 }
664 return ERR_OK;
665 }
666
667 /*-----------------------------------------------------------------------
668 * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
669 * This routine sets the flash to read-array mode.
670 */
671 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
672 ulong tout, char *prompt)
673 {
674 int retcode;
675
676 retcode = flash_status_check (info, sector, tout, prompt);
677 switch (info->vendor) {
678 case CFI_CMDSET_INTEL_EXTENDED:
679 case CFI_CMDSET_INTEL_STANDARD:
680 if ((retcode != ERR_OK)
681 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
682 retcode = ERR_INVAL;
683 printf ("Flash %s error at address %lx\n", prompt,
684 info->start[sector]);
685 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
686 puts ("Command Sequence Error.\n");
687 } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
688 puts ("Block Erase Error.\n");
689 retcode = ERR_NOT_ERASED;
690 } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
691 puts ("Locking Error\n");
692 }
693 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
694 puts ("Block locked.\n");
695 retcode = ERR_PROTECTED;
696 }
697 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
698 puts ("Vpp Low Error.\n");
699 }
700 flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
701 break;
702 default:
703 break;
704 }
705 return retcode;
706 }
707
708 /*-----------------------------------------------------------------------
709 */
710 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
711 {
712 #if defined(__LITTLE_ENDIAN)
713 unsigned short w;
714 unsigned int l;
715 unsigned long long ll;
716 #endif
717
718 switch (info->portwidth) {
719 case FLASH_CFI_8BIT:
720 cword->c = c;
721 break;
722 case FLASH_CFI_16BIT:
723 #if defined(__LITTLE_ENDIAN)
724 w = c;
725 w <<= 8;
726 cword->w = (cword->w >> 8) | w;
727 #else
728 cword->w = (cword->w << 8) | c;
729 #endif
730 break;
731 case FLASH_CFI_32BIT:
732 #if defined(__LITTLE_ENDIAN)
733 l = c;
734 l <<= 24;
735 cword->l = (cword->l >> 8) | l;
736 #else
737 cword->l = (cword->l << 8) | c;
738 #endif
739 break;
740 case FLASH_CFI_64BIT:
741 #if defined(__LITTLE_ENDIAN)
742 ll = c;
743 ll <<= 56;
744 cword->ll = (cword->ll >> 8) | ll;
745 #else
746 cword->ll = (cword->ll << 8) | c;
747 #endif
748 break;
749 }
750 }
751
752
753 /*-----------------------------------------------------------------------
754 * make a proper sized command based on the port and chip widths
755 */
756 static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
757 {
758 int i;
759
760 #if defined(__LITTLE_ENDIAN)
761 ushort stmpw;
762 uint stmpi;
763 #endif
764 uchar *cp = (uchar *) cmdbuf;
765
766 for (i = 0; i < info->portwidth; i++)
767 *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
768 #if defined(__LITTLE_ENDIAN)
769 switch (info->portwidth) {
770 case FLASH_CFI_8BIT:
771 break;
772 case FLASH_CFI_16BIT:
773 stmpw = *(ushort *) cmdbuf;
774 *(ushort *) cmdbuf = __swab16 (stmpw);
775 break;
776 case FLASH_CFI_32BIT:
777 stmpi = *(uint *) cmdbuf;
778 *(uint *) cmdbuf = __swab32 (stmpi);
779 break;
780 default:
781 puts ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
782 break;
783 }
784 #endif
785 }
786
787 /*
788 * Write a proper sized command to the correct address
789 */
790 static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
791 {
792
793 volatile cfiptr_t addr;
794 cfiword_t cword;
795
796 addr.cp = flash_make_addr (info, sect, offset);
797 flash_make_cmd (info, cmd, &cword);
798 switch (info->portwidth) {
799 case FLASH_CFI_8BIT:
800 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
801 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
802 *addr.cp = cword.c;
803 break;
804 case FLASH_CFI_16BIT:
805 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
806 cmd, cword.w,
807 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
808 *addr.wp = cword.w;
809 break;
810 case FLASH_CFI_32BIT:
811 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
812 cmd, cword.l,
813 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
814 *addr.lp = cword.l;
815 break;
816 case FLASH_CFI_64BIT:
817 #ifdef DEBUG
818 {
819 char str[20];
820
821 print_longlong (str, cword.ll);
822
823 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
824 addr.llp, cmd, str,
825 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
826 }
827 #endif
828 *addr.llp = cword.ll;
829 break;
830 }
831 }
832
833 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
834 {
835 flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
836 flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
837 }
838
839 /*-----------------------------------------------------------------------
840 */
841 static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
842 {
843 cfiptr_t cptr;
844 cfiword_t cword;
845 int retval;
846
847 cptr.cp = flash_make_addr (info, sect, offset);
848 flash_make_cmd (info, cmd, &cword);
849
850 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
851 switch (info->portwidth) {
852 case FLASH_CFI_8BIT:
853 debug ("is= %x %x\n", cptr.cp[0], cword.c);
854 retval = (cptr.cp[0] == cword.c);
855 break;
856 case FLASH_CFI_16BIT:
857 debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
858 retval = (cptr.wp[0] == cword.w);
859 break;
860 case FLASH_CFI_32BIT:
861 debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
862 retval = (cptr.lp[0] == cword.l);
863 break;
864 case FLASH_CFI_64BIT:
865 #ifdef DEBUG
866 {
867 char str1[20];
868 char str2[20];
869
870 print_longlong (str1, cptr.llp[0]);
871 print_longlong (str2, cword.ll);
872 debug ("is= %s %s\n", str1, str2);
873 }
874 #endif
875 retval = (cptr.llp[0] == cword.ll);
876 break;
877 default:
878 retval = 0;
879 break;
880 }
881 return retval;
882 }
883
884 /*-----------------------------------------------------------------------
885 */
886 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
887 {
888 cfiptr_t cptr;
889 cfiword_t cword;
890 int retval;
891
892 cptr.cp = flash_make_addr (info, sect, offset);
893 flash_make_cmd (info, cmd, &cword);
894 switch (info->portwidth) {
895 case FLASH_CFI_8BIT:
896 retval = ((cptr.cp[0] & cword.c) == cword.c);
897 break;
898 case FLASH_CFI_16BIT:
899 retval = ((cptr.wp[0] & cword.w) == cword.w);
900 break;
901 case FLASH_CFI_32BIT:
902 retval = ((cptr.lp[0] & cword.l) == cword.l);
903 break;
904 case FLASH_CFI_64BIT:
905 retval = ((cptr.llp[0] & cword.ll) == cword.ll);
906 break;
907 default:
908 retval = 0;
909 break;
910 }
911 return retval;
912 }
913
914 /*-----------------------------------------------------------------------
915 */
916 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
917 {
918 cfiptr_t cptr;
919 cfiword_t cword;
920 int retval;
921
922 cptr.cp = flash_make_addr (info, sect, offset);
923 flash_make_cmd (info, cmd, &cword);
924 switch (info->portwidth) {
925 case FLASH_CFI_8BIT:
926 retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
927 break;
928 case FLASH_CFI_16BIT:
929 retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
930 break;
931 case FLASH_CFI_32BIT:
932 retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
933 break;
934 case FLASH_CFI_64BIT:
935 retval = ((cptr.llp[0] & cword.ll) !=
936 (cptr.llp[0] & cword.ll));
937 break;
938 default:
939 retval = 0;
940 break;
941 }
942 return retval;
943 }
944
945 /*-----------------------------------------------------------------------
946 * detect if flash is compatible with the Common Flash Interface (CFI)
947 * http://www.jedec.org/download/search/jesd68.pdf
948 *
949 */
950 static int flash_detect_cfi (flash_info_t * info)
951 {
952 debug ("flash detect cfi\n");
953
954 for (info->portwidth = FLASH_CFI_8BIT;
955 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
956 for (info->chipwidth = FLASH_CFI_BY8;
957 info->chipwidth <= info->portwidth;
958 info->chipwidth <<= 1) {
959 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
960 flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
961 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
962 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
963 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
964 info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
965 debug ("device interface is %d\n",
966 info->interface);
967 debug ("found port %d chip %d ",
968 info->portwidth, info->chipwidth);
969 debug ("port %d bits chip %d bits\n",
970 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
971 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
972 return 1;
973 }
974 }
975 }
976 debug ("not found\n");
977 return 0;
978 }
979
980 /*
981 * The following code cannot be run from FLASH!
982 *
983 */
984 static ulong flash_get_size (ulong base, int banknum)
985 {
986 flash_info_t *info = &flash_info[banknum];
987 int i, j;
988 flash_sect_t sect_cnt;
989 unsigned long sector;
990 unsigned long tmp;
991 int size_ratio;
992 uchar num_erase_regions;
993 int erase_region_size;
994 int erase_region_count;
995
996 info->start[0] = base;
997
998 if (flash_detect_cfi (info)) {
999 info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
1000 #ifdef DEBUG
1001 flash_printqry (info, 0);
1002 #endif
1003 switch (info->vendor) {
1004 case CFI_CMDSET_INTEL_STANDARD:
1005 case CFI_CMDSET_INTEL_EXTENDED:
1006 default:
1007 info->cmd_reset = FLASH_CMD_RESET;
1008 break;
1009 case CFI_CMDSET_AMD_STANDARD:
1010 case CFI_CMDSET_AMD_EXTENDED:
1011 info->cmd_reset = AMD_CMD_RESET;
1012 break;
1013 }
1014
1015 debug ("manufacturer is %d\n", info->vendor);
1016 size_ratio = info->portwidth / info->chipwidth;
1017 /* if the chip is x8/x16 reduce the ratio by half */
1018 if ((info->interface == FLASH_CFI_X8X16)
1019 && (info->chipwidth == FLASH_CFI_BY8)) {
1020 size_ratio >>= 1;
1021 }
1022 num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
1023 debug ("size_ratio %d port %d bits chip %d bits\n",
1024 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1025 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1026 debug ("found %d erase regions\n", num_erase_regions);
1027 sect_cnt = 0;
1028 sector = base;
1029 for (i = 0; i < num_erase_regions; i++) {
1030 if (i > NUM_ERASE_REGIONS) {
1031 printf ("%d erase regions found, only %d used\n",
1032 num_erase_regions, NUM_ERASE_REGIONS);
1033 break;
1034 }
1035 tmp = flash_read_long (info, 0,
1036 FLASH_OFFSET_ERASE_REGIONS +
1037 i * 4);
1038 erase_region_size =
1039 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
1040 tmp >>= 16;
1041 erase_region_count = (tmp & 0xffff) + 1;
1042 debug ("erase_region_count = %d erase_region_size = %d\n",
1043 erase_region_count, erase_region_size);
1044 for (j = 0; j < erase_region_count; j++) {
1045 info->start[sect_cnt] = sector;
1046 sector += (erase_region_size * size_ratio);
1047 info->protect[sect_cnt] =
1048 flash_isset (info, sect_cnt,
1049 FLASH_OFFSET_PROTECT,
1050 FLASH_STATUS_PROTECT);
1051 sect_cnt++;
1052 }
1053 }
1054
1055 info->sector_count = sect_cnt;
1056 /* multiply the size by the number of chips */
1057 info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
1058 info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
1059 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
1060 info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
1061 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
1062 info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
1063 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
1064 info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
1065 info->flash_id = FLASH_MAN_CFI;
1066 if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
1067 info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
1068 }
1069 }
1070
1071 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
1072 return (info->size);
1073 }
1074
1075
1076 /*-----------------------------------------------------------------------
1077 */
1078 static int flash_write_cfiword (flash_info_t * info, ulong dest,
1079 cfiword_t cword)
1080 {
1081
1082 cfiptr_t ctladdr;
1083 cfiptr_t cptr;
1084 int flag;
1085
1086 ctladdr.cp = flash_make_addr (info, 0, 0);
1087 cptr.cp = (uchar *) dest;
1088
1089
1090 /* Check if Flash is (sufficiently) erased */
1091 switch (info->portwidth) {
1092 case FLASH_CFI_8BIT:
1093 flag = ((cptr.cp[0] & cword.c) == cword.c);
1094 break;
1095 case FLASH_CFI_16BIT:
1096 flag = ((cptr.wp[0] & cword.w) == cword.w);
1097 break;
1098 case FLASH_CFI_32BIT:
1099 flag = ((cptr.lp[0] & cword.l) == cword.l);
1100 break;
1101 case FLASH_CFI_64BIT:
1102 flag = ((cptr.lp[0] & cword.ll) == cword.ll);
1103 break;
1104 default:
1105 return 2;
1106 }
1107 if (!flag)
1108 return 2;
1109
1110 /* Disable interrupts which might cause a timeout here */
1111 flag = disable_interrupts ();
1112
1113 switch (info->vendor) {
1114 case CFI_CMDSET_INTEL_EXTENDED:
1115 case CFI_CMDSET_INTEL_STANDARD:
1116 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
1117 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
1118 break;
1119 case CFI_CMDSET_AMD_EXTENDED:
1120 case CFI_CMDSET_AMD_STANDARD:
1121 flash_unlock_seq (info, 0);
1122 flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
1123 break;
1124 }
1125
1126 switch (info->portwidth) {
1127 case FLASH_CFI_8BIT:
1128 cptr.cp[0] = cword.c;
1129 break;
1130 case FLASH_CFI_16BIT:
1131 cptr.wp[0] = cword.w;
1132 break;
1133 case FLASH_CFI_32BIT:
1134 cptr.lp[0] = cword.l;
1135 break;
1136 case FLASH_CFI_64BIT:
1137 cptr.llp[0] = cword.ll;
1138 break;
1139 }
1140
1141 /* re-enable interrupts if necessary */
1142 if (flag)
1143 enable_interrupts ();
1144
1145 return flash_full_status_check (info, 0, info->write_tout, "write");
1146 }
1147
1148 #ifdef CFG_FLASH_USE_BUFFER_WRITE
1149
1150 /* loop through the sectors from the highest address
1151 * when the passed address is greater or equal to the sector address
1152 * we have a match
1153 */
1154 static flash_sect_t find_sector (flash_info_t * info, ulong addr)
1155 {
1156 flash_sect_t sector;
1157
1158 for (sector = info->sector_count - 1; sector >= 0; sector--) {
1159 if (addr >= info->start[sector])
1160 break;
1161 }
1162 return sector;
1163 }
1164
1165 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
1166 int len)
1167 {
1168 flash_sect_t sector;
1169 int cnt;
1170 int retcode;
1171 volatile cfiptr_t src;
1172 volatile cfiptr_t dst;
1173 /* buffered writes in the AMD chip set is not supported yet */
1174 if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
1175 (info->vendor == CFI_CMDSET_AMD_EXTENDED))
1176 return ERR_INVAL;
1177
1178 src.cp = cp;
1179 dst.cp = (uchar *) dest;
1180 sector = find_sector (info, dest);
1181 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1182 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
1183 if ((retcode =
1184 flash_status_check (info, sector, info->buffer_write_tout,
1185 "write to buffer")) == ERR_OK) {
1186 /* reduce the number of loops by the width of the port */
1187 switch (info->portwidth) {
1188 case FLASH_CFI_8BIT:
1189 cnt = len;
1190 break;
1191 case FLASH_CFI_16BIT:
1192 cnt = len >> 1;
1193 break;
1194 case FLASH_CFI_32BIT:
1195 cnt = len >> 2;
1196 break;
1197 case FLASH_CFI_64BIT:
1198 cnt = len >> 3;
1199 break;
1200 default:
1201 return ERR_INVAL;
1202 break;
1203 }
1204 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1205 while (cnt-- > 0) {
1206 switch (info->portwidth) {
1207 case FLASH_CFI_8BIT:
1208 *dst.cp++ = *src.cp++;
1209 break;
1210 case FLASH_CFI_16BIT:
1211 *dst.wp++ = *src.wp++;
1212 break;
1213 case FLASH_CFI_32BIT:
1214 *dst.lp++ = *src.lp++;
1215 break;
1216 case FLASH_CFI_64BIT:
1217 *dst.llp++ = *src.llp++;
1218 break;
1219 default:
1220 return ERR_INVAL;
1221 break;
1222 }
1223 }
1224 flash_write_cmd (info, sector, 0,
1225 FLASH_CMD_WRITE_BUFFER_CONFIRM);
1226 retcode =
1227 flash_full_status_check (info, sector,
1228 info->buffer_write_tout,
1229 "buffer write");
1230 }
1231 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1232 return retcode;
1233 }
1234 #endif /* CFG_USE_FLASH_BUFFER_WRITE */
1235 #endif /* CFG_FLASH_CFI */
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