drivers/clk/clk-divider.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
   8  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   9  *
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <malloc.h>
  15 #include <clk-uclass.h>
  16 #include <dm/device.h>
  17 #include <dm/uclass.h>
  18 #include <dm/lists.h>
  19 #include <dm/device-internal.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/log2.h>
  22 #include <div64.h>
  23 #include <clk.h>
  24 #include "clk.h"
  25
  26 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
  27
  28 static unsigned int _get_table_div(const struct clk_div_table *table,
  29                                    unsigned int val)
  30 {
  31         const struct clk_div_table *clkt;
  32
  33         for (clkt = table; clkt->div; clkt++)
  34                 if (clkt->val == val)
  35                         return clkt->div;
  36         return 0;
  37 }
  38
  39 static unsigned int _get_div(const struct clk_div_table *table,
  40                              unsigned int val, unsigned long flags, u8 width)
  41 {
  42         if (flags & CLK_DIVIDER_ONE_BASED)
  43                 return val;
  44         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  45                 return 1 << val;
  46         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  47                 return val ? val : clk_div_mask(width) + 1;
  48         if (table)
  49                 return _get_table_div(table, val);
  50         return val + 1;
  51 }
  52
  53 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  54                                   unsigned int val,
  55                                   const struct clk_div_table *table,
  56                                   unsigned long flags, unsigned long width)
  57 {
  58         unsigned int div;
  59
  60         div = _get_div(table, val, flags, width);
  61         if (!div) {
  62                 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  63                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  64                      clk_hw_get_name(hw));
  65                 return parent_rate;
  66         }
  67
  68         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  69 }
  70
  71 static ulong clk_divider_recalc_rate(struct clk *clk)
  72 {
  73         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
  74                         dev_get_clk_ptr(clk->dev) : clk);
  75         unsigned long parent_rate = clk_get_parent_rate(clk);
  76         unsigned int val;
  77
  78 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  79         val = divider->io_divider_val;
  80 #else
  81         val = readl(divider->reg);
  82 #endif
  83         val >>= divider->shift;
  84         val &= clk_div_mask(divider->width);
  85
  86         return divider_recalc_rate(clk, parent_rate, val, divider->table,
  87                                    divider->flags, divider->width);
  88 }
  89
  90 static bool _is_valid_table_div(const struct clk_div_table *table,
  91                                 unsigned int div)
  92 {
  93         const struct clk_div_table *clkt;
  94
  95         for (clkt = table; clkt->div; clkt++)
  96                 if (clkt->div == div)
  97                         return true;
  98         return false;
  99 }
 100
 101 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
 102                           unsigned long flags)
 103 {
 104         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 105                 return is_power_of_2(div);
 106         if (table)
 107                 return _is_valid_table_div(table, div);
 108         return true;
 109 }
 110
 111 static unsigned int _get_table_val(const struct clk_div_table *table,
 112                                    unsigned int div)
 113 {
 114         const struct clk_div_table *clkt;
 115
 116         for (clkt = table; clkt->div; clkt++)
 117                 if (clkt->div == div)
 118                         return clkt->val;
 119         return 0;
 120 }
 121
 122 static unsigned int _get_val(const struct clk_div_table *table,
 123                              unsigned int div, unsigned long flags, u8 width)
 124 {
 125         if (flags & CLK_DIVIDER_ONE_BASED)
 126                 return div;
 127         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 128                 return __ffs(div);
 129         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 130                 return (div == clk_div_mask(width) + 1) ? 0 : div;
 131         if (table)
 132                 return  _get_table_val(table, div);
 133         return div - 1;
 134 }
 135 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 136                     const struct clk_div_table *table, u8 width,
 137                     unsigned long flags)
 138 {
 139         unsigned int div, value;
 140
 141         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 142
 143         if (!_is_valid_div(table, div, flags))
 144                 return -EINVAL;
 145
 146         value = _get_val(table, div, flags, width);
 147
 148         return min_t(unsigned int, value, clk_div_mask(width));
 149 }
 150
 151 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
 152 {
 153         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
 154                         dev_get_clk_ptr(clk->dev) : clk);
 155         unsigned long parent_rate = clk_get_parent_rate(clk);
 156         int value;
 157         u32 val;
 158
 159         value = divider_get_val(rate, parent_rate, divider->table,
 160                                 divider->width, divider->flags);
 161         if (value < 0)
 162                 return value;
 163
 164         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
 165                 val = clk_div_mask(divider->width) << (divider->shift + 16);
 166         } else {
 167                 val = readl(divider->reg);
 168                 val &= ~(clk_div_mask(divider->width) << divider->shift);
 169         }
 170         val |= (u32)value << divider->shift;
 171         writel(val, divider->reg);
 172
 173         return clk_get_rate(clk);
 174 }
 175
 176 const struct clk_ops clk_divider_ops = {
 177         .get_rate = clk_divider_recalc_rate,
 178         .set_rate = clk_divider_set_rate,
 179 };
 180
 181 static struct clk *_register_divider(struct device *dev, const char *name,
 182                 const char *parent_name, unsigned long flags,
 183                 void __iomem *reg, u8 shift, u8 width,
 184                 u8 clk_divider_flags, const struct clk_div_table *table)
 185 {
 186         struct clk_divider *div;
 187         struct clk *clk;
 188         int ret;
 189
 190         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
 191                 if (width + shift > 16) {
 192                         pr_warn("divider value exceeds LOWORD field\n");
 193                         return ERR_PTR(-EINVAL);
 194                 }
 195         }
 196
 197         /* allocate the divider */
 198         div = kzalloc(sizeof(*div), GFP_KERNEL);
 199         if (!div)
 200                 return ERR_PTR(-ENOMEM);
 201
 202         /* struct clk_divider assignments */
 203         div->reg = reg;
 204         div->shift = shift;
 205         div->width = width;
 206         div->flags = clk_divider_flags;
 207         div->table = table;
 208 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
 209         div->io_divider_val = *(u32 *)reg;
 210 #endif
 211
 212         /* register the clock */
 213         clk = &div->clk;
 214
 215         ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
 216         if (ret) {
 217                 kfree(div);
 218                 return ERR_PTR(ret);
 219         }
 220
 221         return clk;
 222 }
 223
 224 struct clk *clk_register_divider(struct device *dev, const char *name,
 225                 const char *parent_name, unsigned long flags,
 226                 void __iomem *reg, u8 shift, u8 width,
 227                 u8 clk_divider_flags)
 228 {
 229         struct clk *clk;
 230
 231         clk =  _register_divider(dev, name, parent_name, flags, reg, shift,
 232                                  width, clk_divider_flags, NULL);
 233         if (IS_ERR(clk))
 234                 return ERR_CAST(clk);
 235         return clk;
 236 }
 237
 238 U_BOOT_DRIVER(ccf_clk_divider) = {
 239         .name   = UBOOT_DM_CLK_CCF_DIVIDER,
 240         .id     = UCLASS_CLK,
 241         .ops    = &clk_divider_ops,
 242         .flags = DM_FLAG_PRE_RELOC,
 243 };