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[thirdparty/kernel/stable.git] / drivers / clk / clk-versaclock3.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Renesas Versaclock 3
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/i2c.h>
10 #include <linux/limits.h>
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13
14 #define NUM_CONFIG_REGISTERS 37
15
16 #define VC3_GENERAL_CTR 0x0
17 #define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3)
18 #define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2)
19
20 #define VC3_PLL3_M_DIVIDER 0x3
21 #define VC3_PLL3_M_DIV1 BIT(7)
22 #define VC3_PLL3_M_DIV2 BIT(6)
23 #define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0))
24
25 #define VC3_PLL3_N_DIVIDER 0x4
26 #define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5
27
28 #define VC3_PLL3_CHARGE_PUMP_CTRL 0x6
29 #define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7)
30
31 #define VC3_PLL1_CTRL_OUTDIV5 0x7
32 #define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7)
33
34 #define VC3_PLL1_M_DIVIDER 0x8
35 #define VC3_PLL1_M_DIV1 BIT(7)
36 #define VC3_PLL1_M_DIV2 BIT(6)
37 #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))
38
39 #define VC3_PLL1_VCO_N_DIVIDER 0x9
40 #define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a
41
42 #define VC3_OUT_DIV1_DIV2_CTRL 0xf
43
44 #define VC3_PLL2_FB_INT_DIV_MSB 0x10
45 #define VC3_PLL2_FB_INT_DIV_LSB 0x11
46 #define VC3_PLL2_FB_FRC_DIV_MSB 0x12
47 #define VC3_PLL2_FB_FRC_DIV_LSB 0x13
48
49 #define VC3_PLL2_M_DIVIDER 0x1a
50 #define VC3_PLL2_MDIV_DOUBLER BIT(7)
51 #define VC3_PLL2_M_DIV1 BIT(6)
52 #define VC3_PLL2_M_DIV2 BIT(5)
53 #define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0))
54
55 #define VC3_OUT_DIV3_DIV4_CTRL 0x1b
56
57 #define VC3_PLL_OP_CTRL 0x1c
58 #define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6
59
60 #define VC3_OUTPUT_CTR 0x1d
61 #define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
62
63 #define VC3_SE2_CTRL_REG0 0x1f
64 #define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
65
66 #define VC3_SE3_DIFF1_CTRL_REG 0x21
67 #define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
68
69 #define VC3_DIFF1_CTRL_REG 0x22
70 #define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7)
71
72 #define VC3_DIFF2_CTRL_REG 0x23
73 #define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7)
74
75 #define VC3_SE1_DIV4_CTRL 0x24
76 #define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3)
77
78 #define VC3_PLL1_VCO_MIN 300000000UL
79 #define VC3_PLL1_VCO_MAX 600000000UL
80
81 #define VC3_PLL2_VCO_MIN 400000000UL
82 #define VC3_PLL2_VCO_MAX 1200000000UL
83
84 #define VC3_PLL3_VCO_MIN 300000000UL
85 #define VC3_PLL3_VCO_MAX 800000000UL
86
87 #define VC3_2_POW_16 (U16_MAX + 1)
88 #define VC3_DIV_MASK(width) ((1 << (width)) - 1)
89
90 enum vc3_pfd_mux {
91 VC3_PFD2_MUX,
92 VC3_PFD3_MUX,
93 };
94
95 enum vc3_pfd {
96 VC3_PFD1,
97 VC3_PFD2,
98 VC3_PFD3,
99 };
100
101 enum vc3_pll {
102 VC3_PLL1,
103 VC3_PLL2,
104 VC3_PLL3,
105 };
106
107 enum vc3_div_mux {
108 VC3_DIV1_MUX,
109 VC3_DIV3_MUX,
110 VC3_DIV4_MUX,
111 };
112
113 enum vc3_div {
114 VC3_DIV1,
115 VC3_DIV2,
116 VC3_DIV3,
117 VC3_DIV4,
118 VC3_DIV5,
119 };
120
121 enum vc3_clk_mux {
122 VC3_DIFF2_MUX,
123 VC3_DIFF1_MUX,
124 VC3_SE3_MUX,
125 VC3_SE2_MUX,
126 VC3_SE1_MUX,
127 };
128
129 enum vc3_clk {
130 VC3_DIFF2,
131 VC3_DIFF1,
132 VC3_SE3,
133 VC3_SE2,
134 VC3_SE1,
135 VC3_REF,
136 };
137
138 struct vc3_clk_data {
139 u8 offs;
140 u8 bitmsk;
141 };
142
143 struct vc3_pfd_data {
144 u8 num;
145 u8 offs;
146 u8 mdiv1_bitmsk;
147 u8 mdiv2_bitmsk;
148 };
149
150 struct vc3_pll_data {
151 u8 num;
152 u8 int_div_msb_offs;
153 u8 int_div_lsb_offs;
154 unsigned long vco_min;
155 unsigned long vco_max;
156 };
157
158 struct vc3_div_data {
159 u8 offs;
160 const struct clk_div_table *table;
161 u8 shift;
162 u8 width;
163 u8 flags;
164 };
165
166 struct vc3_hw_data {
167 struct clk_hw hw;
168 struct regmap *regmap;
169 const void *data;
170
171 u32 div_int;
172 u32 div_frc;
173 };
174
175 static const struct clk_div_table div1_divs[] = {
176 { .val = 0, .div = 1, }, { .val = 1, .div = 4, },
177 { .val = 2, .div = 5, }, { .val = 3, .div = 6, },
178 { .val = 4, .div = 2, }, { .val = 5, .div = 8, },
179 { .val = 6, .div = 10, }, { .val = 7, .div = 12, },
180 { .val = 8, .div = 4, }, { .val = 9, .div = 16, },
181 { .val = 10, .div = 20, }, { .val = 11, .div = 24, },
182 { .val = 12, .div = 8, }, { .val = 13, .div = 32, },
183 { .val = 14, .div = 40, }, { .val = 15, .div = 48, },
184 {}
185 };
186
187 static const struct clk_div_table div245_divs[] = {
188 { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
189 { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
190 { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
191 { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
192 { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
193 { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
194 { .val = 12, .div = 5, }, { .val = 13, .div = 15, },
195 { .val = 14, .div = 25, }, { .val = 15, .div = 50, },
196 {}
197 };
198
199 static const struct clk_div_table div3_divs[] = {
200 { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
201 { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
202 { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
203 { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
204 { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
205 { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
206 { .val = 12, .div = 8, }, { .val = 13, .div = 24, },
207 { .val = 14, .div = 40, }, { .val = 15, .div = 80, },
208 {}
209 };
210
211 static struct clk_hw *clk_out[6];
212
213 static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw)
214 {
215 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
216 const struct vc3_clk_data *pfd_mux = vc3->data;
217 u32 src;
218
219 regmap_read(vc3->regmap, pfd_mux->offs, &src);
220
221 return !!(src & pfd_mux->bitmsk);
222 }
223
224 static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index)
225 {
226 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
227 const struct vc3_clk_data *pfd_mux = vc3->data;
228
229 regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk,
230 index ? pfd_mux->bitmsk : 0);
231 return 0;
232 }
233
234 static const struct clk_ops vc3_pfd_mux_ops = {
235 .determine_rate = clk_hw_determine_rate_no_reparent,
236 .set_parent = vc3_pfd_mux_set_parent,
237 .get_parent = vc3_pfd_mux_get_parent,
238 };
239
240 static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
241 unsigned long parent_rate)
242 {
243 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
244 const struct vc3_pfd_data *pfd = vc3->data;
245 unsigned int prediv, premul;
246 unsigned long rate;
247 u8 mdiv;
248
249 regmap_read(vc3->regmap, pfd->offs, &prediv);
250 if (pfd->num == VC3_PFD1) {
251 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
252 if (prediv & pfd->mdiv1_bitmsk) {
253 /* check doubler is set or not */
254 regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul);
255 if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
256 parent_rate *= 2;
257 return parent_rate;
258 }
259 mdiv = VC3_PLL1_M_DIV(prediv);
260 } else if (pfd->num == VC3_PFD2) {
261 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
262 if (prediv & pfd->mdiv1_bitmsk) {
263 regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul);
264 /* check doubler is set or not */
265 if (premul & VC3_PLL2_MDIV_DOUBLER)
266 parent_rate *= 2;
267 return parent_rate;
268 }
269
270 mdiv = VC3_PLL2_M_DIV(prediv);
271 } else {
272 /* The bypass_prediv is set, PLL fed from Ref_in directly. */
273 if (prediv & pfd->mdiv1_bitmsk)
274 return parent_rate;
275
276 mdiv = VC3_PLL3_M_DIV(prediv);
277 }
278
279 if (prediv & pfd->mdiv2_bitmsk)
280 rate = parent_rate / 2;
281 else
282 rate = parent_rate / mdiv;
283
284 return rate;
285 }
286
287 static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
288 unsigned long *parent_rate)
289 {
290 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
291 const struct vc3_pfd_data *pfd = vc3->data;
292 unsigned long idiv;
293
294 /* PLL cannot operate with input clock above 50 MHz. */
295 if (rate > 50000000)
296 return -EINVAL;
297
298 /* CLKIN within range of PLL input, feed directly to PLL. */
299 if (*parent_rate <= 50000000)
300 return *parent_rate;
301
302 idiv = DIV_ROUND_UP(*parent_rate, rate);
303 if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) {
304 if (idiv > 63)
305 return -EINVAL;
306 } else {
307 if (idiv > 31)
308 return -EINVAL;
309 }
310
311 return *parent_rate / idiv;
312 }
313
314 static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
315 unsigned long parent_rate)
316 {
317 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
318 const struct vc3_pfd_data *pfd = vc3->data;
319 unsigned long idiv;
320 u8 div;
321
322 /* CLKIN within range of PLL input, feed directly to PLL. */
323 if (parent_rate <= 50000000) {
324 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
325 pfd->mdiv1_bitmsk);
326 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0);
327 return 0;
328 }
329
330 idiv = DIV_ROUND_UP(parent_rate, rate);
331 /* We have dedicated div-2 predivider. */
332 if (idiv == 2) {
333 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk,
334 pfd->mdiv2_bitmsk);
335 regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
336 } else {
337 if (pfd->num == VC3_PFD1)
338 div = VC3_PLL1_M_DIV(idiv);
339 else if (pfd->num == VC3_PFD2)
340 div = VC3_PLL2_M_DIV(idiv);
341 else
342 div = VC3_PLL3_M_DIV(idiv);
343
344 regmap_write(vc3->regmap, pfd->offs, div);
345 }
346
347 return 0;
348 }
349
350 static const struct clk_ops vc3_pfd_ops = {
351 .recalc_rate = vc3_pfd_recalc_rate,
352 .round_rate = vc3_pfd_round_rate,
353 .set_rate = vc3_pfd_set_rate,
354 };
355
356 static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw,
357 unsigned long parent_rate)
358 {
359 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
360 const struct vc3_pll_data *pll = vc3->data;
361 u32 div_int, div_frc, val;
362 unsigned long rate;
363
364 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
365 div_int = (val & GENMASK(2, 0)) << 8;
366 regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val);
367 div_int |= val;
368
369 if (pll->num == VC3_PLL2) {
370 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val);
371 div_frc = val << 8;
372 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val);
373 div_frc |= val;
374 rate = (parent_rate *
375 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
376 } else {
377 rate = parent_rate * div_int;
378 }
379
380 return rate;
381 }
382
383 static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
384 unsigned long *parent_rate)
385 {
386 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
387 const struct vc3_pll_data *pll = vc3->data;
388 u64 div_frc;
389
390 if (rate < pll->vco_min)
391 rate = pll->vco_min;
392 if (rate > pll->vco_max)
393 rate = pll->vco_max;
394
395 vc3->div_int = rate / *parent_rate;
396
397 if (pll->num == VC3_PLL2) {
398 if (vc3->div_int > 0x7ff)
399 rate = *parent_rate * 0x7ff;
400
401 /* Determine best fractional part, which is 16 bit wide */
402 div_frc = rate % *parent_rate;
403 div_frc *= BIT(16) - 1;
404 do_div(div_frc, *parent_rate);
405
406 vc3->div_frc = (u32)div_frc;
407 rate = (*parent_rate *
408 (vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
409 } else {
410 rate = *parent_rate * vc3->div_int;
411 }
412
413 return rate;
414 }
415
416 static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate,
417 unsigned long parent_rate)
418 {
419 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
420 const struct vc3_pll_data *pll = vc3->data;
421 u32 val;
422
423 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
424 val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7);
425 regmap_write(vc3->regmap, pll->int_div_msb_offs, val);
426 regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff);
427
428 if (pll->num == VC3_PLL2) {
429 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB,
430 vc3->div_frc >> 8);
431 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB,
432 vc3->div_frc & 0xff);
433 }
434
435 return 0;
436 }
437
438 static const struct clk_ops vc3_pll_ops = {
439 .recalc_rate = vc3_pll_recalc_rate,
440 .round_rate = vc3_pll_round_rate,
441 .set_rate = vc3_pll_set_rate,
442 };
443
444 static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw)
445 {
446 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
447 const struct vc3_clk_data *div_mux = vc3->data;
448 u32 src;
449
450 regmap_read(vc3->regmap, div_mux->offs, &src);
451
452 return !!(src & div_mux->bitmsk);
453 }
454
455 static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index)
456 {
457 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
458 const struct vc3_clk_data *div_mux = vc3->data;
459
460 regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk,
461 index ? div_mux->bitmsk : 0);
462
463 return 0;
464 }
465
466 static const struct clk_ops vc3_div_mux_ops = {
467 .determine_rate = clk_hw_determine_rate_no_reparent,
468 .set_parent = vc3_div_mux_set_parent,
469 .get_parent = vc3_div_mux_get_parent,
470 };
471
472 static unsigned int vc3_get_div(const struct clk_div_table *table,
473 unsigned int val, unsigned long flag)
474 {
475 const struct clk_div_table *clkt;
476
477 for (clkt = table; clkt->div; clkt++)
478 if (clkt->val == val)
479 return clkt->div;
480
481 return 0;
482 }
483
484 static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,
485 unsigned long parent_rate)
486 {
487 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
488 const struct vc3_div_data *div_data = vc3->data;
489 unsigned int val;
490
491 regmap_read(vc3->regmap, div_data->offs, &val);
492 val >>= div_data->shift;
493 val &= VC3_DIV_MASK(div_data->width);
494
495 return divider_recalc_rate(hw, parent_rate, val, div_data->table,
496 div_data->flags, div_data->width);
497 }
498
499 static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate,
500 unsigned long *parent_rate)
501 {
502 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
503 const struct vc3_div_data *div_data = vc3->data;
504 unsigned int bestdiv;
505
506 /* if read only, just return current value */
507 if (div_data->flags & CLK_DIVIDER_READ_ONLY) {
508 regmap_read(vc3->regmap, div_data->offs, &bestdiv);
509 bestdiv >>= div_data->shift;
510 bestdiv &= VC3_DIV_MASK(div_data->width);
511 bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags);
512 return DIV_ROUND_UP(*parent_rate, bestdiv);
513 }
514
515 return divider_round_rate(hw, rate, parent_rate, div_data->table,
516 div_data->width, div_data->flags);
517 }
518
519 static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,
520 unsigned long parent_rate)
521 {
522 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
523 const struct vc3_div_data *div_data = vc3->data;
524 unsigned int value;
525
526 value = divider_get_val(rate, parent_rate, div_data->table,
527 div_data->width, div_data->flags);
528 regmap_update_bits(vc3->regmap, div_data->offs,
529 VC3_DIV_MASK(div_data->width) << div_data->shift,
530 value << div_data->shift);
531 return 0;
532 }
533
534 static const struct clk_ops vc3_div_ops = {
535 .recalc_rate = vc3_div_recalc_rate,
536 .round_rate = vc3_div_round_rate,
537 .set_rate = vc3_div_set_rate,
538 };
539
540 static int vc3_clk_mux_determine_rate(struct clk_hw *hw,
541 struct clk_rate_request *req)
542 {
543 int ret;
544 int frc;
545
546 ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT);
547 if (ret) {
548 /* The below check is equivalent to (best_parent_rate/rate) */
549 if (req->best_parent_rate >= req->rate) {
550 frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate,
551 req->rate);
552 req->rate *= frc;
553 return clk_mux_determine_rate_flags(hw, req,
554 CLK_SET_RATE_PARENT);
555 }
556 ret = 0;
557 }
558
559 return ret;
560 }
561
562 static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw)
563 {
564 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
565 const struct vc3_clk_data *clk_mux = vc3->data;
566 u32 val;
567
568 regmap_read(vc3->regmap, clk_mux->offs, &val);
569
570 return !!(val & clk_mux->bitmsk);
571 }
572
573 static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)
574 {
575 struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
576 const struct vc3_clk_data *clk_mux = vc3->data;
577
578 regmap_update_bits(vc3->regmap, clk_mux->offs,
579 clk_mux->bitmsk, index ? clk_mux->bitmsk : 0);
580 return 0;
581 }
582
583 static const struct clk_ops vc3_clk_mux_ops = {
584 .determine_rate = vc3_clk_mux_determine_rate,
585 .set_parent = vc3_clk_mux_set_parent,
586 .get_parent = vc3_clk_mux_get_parent,
587 };
588
589 static bool vc3_regmap_is_writeable(struct device *dev, unsigned int reg)
590 {
591 return true;
592 }
593
594 static const struct regmap_config vc3_regmap_config = {
595 .reg_bits = 8,
596 .val_bits = 8,
597 .cache_type = REGCACHE_RBTREE,
598 .max_register = 0x24,
599 .writeable_reg = vc3_regmap_is_writeable,
600 };
601
602 static struct vc3_hw_data clk_div[5];
603
604 static const struct clk_parent_data pfd_mux_parent_data[] = {
605 { .index = 0, },
606 { .hw = &clk_div[VC3_DIV2].hw }
607 };
608
609 static struct vc3_hw_data clk_pfd_mux[] = {
610 [VC3_PFD2_MUX] = {
611 .data = &(struct vc3_clk_data) {
612 .offs = VC3_PLL_OP_CTRL,
613 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
614 },
615 .hw.init = &(struct clk_init_data){
616 .name = "pfd2_mux",
617 .ops = &vc3_pfd_mux_ops,
618 .parent_data = pfd_mux_parent_data,
619 .num_parents = 2,
620 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
621 }
622 },
623 [VC3_PFD3_MUX] = {
624 .data = &(struct vc3_clk_data) {
625 .offs = VC3_GENERAL_CTR,
626 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
627 },
628 .hw.init = &(struct clk_init_data){
629 .name = "pfd3_mux",
630 .ops = &vc3_pfd_mux_ops,
631 .parent_data = pfd_mux_parent_data,
632 .num_parents = 2,
633 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
634 }
635 }
636 };
637
638 static struct vc3_hw_data clk_pfd[] = {
639 [VC3_PFD1] = {
640 .data = &(struct vc3_pfd_data) {
641 .num = VC3_PFD1,
642 .offs = VC3_PLL1_M_DIVIDER,
643 .mdiv1_bitmsk = VC3_PLL1_M_DIV1,
644 .mdiv2_bitmsk = VC3_PLL1_M_DIV2
645 },
646 .hw.init = &(struct clk_init_data){
647 .name = "pfd1",
648 .ops = &vc3_pfd_ops,
649 .parent_data = &(const struct clk_parent_data) {
650 .index = 0
651 },
652 .num_parents = 1,
653 .flags = CLK_SET_RATE_PARENT
654 }
655 },
656 [VC3_PFD2] = {
657 .data = &(struct vc3_pfd_data) {
658 .num = VC3_PFD2,
659 .offs = VC3_PLL2_M_DIVIDER,
660 .mdiv1_bitmsk = VC3_PLL2_M_DIV1,
661 .mdiv2_bitmsk = VC3_PLL2_M_DIV2
662 },
663 .hw.init = &(struct clk_init_data){
664 .name = "pfd2",
665 .ops = &vc3_pfd_ops,
666 .parent_hws = (const struct clk_hw *[]) {
667 &clk_pfd_mux[VC3_PFD2_MUX].hw
668 },
669 .num_parents = 1,
670 .flags = CLK_SET_RATE_PARENT
671 }
672 },
673 [VC3_PFD3] = {
674 .data = &(struct vc3_pfd_data) {
675 .num = VC3_PFD3,
676 .offs = VC3_PLL3_M_DIVIDER,
677 .mdiv1_bitmsk = VC3_PLL3_M_DIV1,
678 .mdiv2_bitmsk = VC3_PLL3_M_DIV2
679 },
680 .hw.init = &(struct clk_init_data){
681 .name = "pfd3",
682 .ops = &vc3_pfd_ops,
683 .parent_hws = (const struct clk_hw *[]) {
684 &clk_pfd_mux[VC3_PFD3_MUX].hw
685 },
686 .num_parents = 1,
687 .flags = CLK_SET_RATE_PARENT
688 }
689 }
690 };
691
692 static struct vc3_hw_data clk_pll[] = {
693 [VC3_PLL1] = {
694 .data = &(struct vc3_pll_data) {
695 .num = VC3_PLL1,
696 .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
697 .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
698 .vco_min = VC3_PLL1_VCO_MIN,
699 .vco_max = VC3_PLL1_VCO_MAX
700 },
701 .hw.init = &(struct clk_init_data){
702 .name = "pll1",
703 .ops = &vc3_pll_ops,
704 .parent_hws = (const struct clk_hw *[]) {
705 &clk_pfd[VC3_PFD1].hw
706 },
707 .num_parents = 1,
708 .flags = CLK_SET_RATE_PARENT
709 }
710 },
711 [VC3_PLL2] = {
712 .data = &(struct vc3_pll_data) {
713 .num = VC3_PLL2,
714 .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
715 .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
716 .vco_min = VC3_PLL2_VCO_MIN,
717 .vco_max = VC3_PLL2_VCO_MAX
718 },
719 .hw.init = &(struct clk_init_data){
720 .name = "pll2",
721 .ops = &vc3_pll_ops,
722 .parent_hws = (const struct clk_hw *[]) {
723 &clk_pfd[VC3_PFD2].hw
724 },
725 .num_parents = 1,
726 .flags = CLK_SET_RATE_PARENT
727 }
728 },
729 [VC3_PLL3] = {
730 .data = &(struct vc3_pll_data) {
731 .num = VC3_PLL3,
732 .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
733 .int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
734 .vco_min = VC3_PLL3_VCO_MIN,
735 .vco_max = VC3_PLL3_VCO_MAX
736 },
737 .hw.init = &(struct clk_init_data){
738 .name = "pll3",
739 .ops = &vc3_pll_ops,
740 .parent_hws = (const struct clk_hw *[]) {
741 &clk_pfd[VC3_PFD3].hw
742 },
743 .num_parents = 1,
744 .flags = CLK_SET_RATE_PARENT
745 }
746 }
747 };
748
749 static const struct clk_parent_data div_mux_parent_data[][2] = {
750 [VC3_DIV1_MUX] = {
751 { .hw = &clk_pll[VC3_PLL1].hw },
752 { .index = 0 }
753 },
754 [VC3_DIV3_MUX] = {
755 { .hw = &clk_pll[VC3_PLL2].hw },
756 { .hw = &clk_pll[VC3_PLL3].hw }
757 },
758 [VC3_DIV4_MUX] = {
759 { .hw = &clk_pll[VC3_PLL2].hw },
760 { .index = 0 }
761 }
762 };
763
764 static struct vc3_hw_data clk_div_mux[] = {
765 [VC3_DIV1_MUX] = {
766 .data = &(struct vc3_clk_data) {
767 .offs = VC3_GENERAL_CTR,
768 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
769 },
770 .hw.init = &(struct clk_init_data){
771 .name = "div1_mux",
772 .ops = &vc3_div_mux_ops,
773 .parent_data = div_mux_parent_data[VC3_DIV1_MUX],
774 .num_parents = 2,
775 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
776 }
777 },
778 [VC3_DIV3_MUX] = {
779 .data = &(struct vc3_clk_data) {
780 .offs = VC3_PLL3_CHARGE_PUMP_CTRL,
781 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
782 },
783 .hw.init = &(struct clk_init_data){
784 .name = "div3_mux",
785 .ops = &vc3_div_mux_ops,
786 .parent_data = div_mux_parent_data[VC3_DIV3_MUX],
787 .num_parents = 2,
788 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
789 }
790 },
791 [VC3_DIV4_MUX] = {
792 .data = &(struct vc3_clk_data) {
793 .offs = VC3_OUTPUT_CTR,
794 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
795 },
796 .hw.init = &(struct clk_init_data){
797 .name = "div4_mux",
798 .ops = &vc3_div_mux_ops,
799 .parent_data = div_mux_parent_data[VC3_DIV4_MUX],
800 .num_parents = 2,
801 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
802 }
803 }
804 };
805
806 static struct vc3_hw_data clk_div[] = {
807 [VC3_DIV1] = {
808 .data = &(struct vc3_div_data) {
809 .offs = VC3_OUT_DIV1_DIV2_CTRL,
810 .table = div1_divs,
811 .shift = 4,
812 .width = 4,
813 .flags = CLK_DIVIDER_READ_ONLY
814 },
815 .hw.init = &(struct clk_init_data){
816 .name = "div1",
817 .ops = &vc3_div_ops,
818 .parent_hws = (const struct clk_hw *[]) {
819 &clk_div_mux[VC3_DIV1_MUX].hw
820 },
821 .num_parents = 1,
822 .flags = CLK_SET_RATE_PARENT
823 }
824 },
825 [VC3_DIV2] = {
826 .data = &(struct vc3_div_data) {
827 .offs = VC3_OUT_DIV1_DIV2_CTRL,
828 .table = div245_divs,
829 .shift = 0,
830 .width = 4,
831 .flags = CLK_DIVIDER_READ_ONLY
832 },
833 .hw.init = &(struct clk_init_data){
834 .name = "div2",
835 .ops = &vc3_div_ops,
836 .parent_hws = (const struct clk_hw *[]) {
837 &clk_pll[VC3_PLL1].hw
838 },
839 .num_parents = 1,
840 .flags = CLK_SET_RATE_PARENT
841 }
842 },
843 [VC3_DIV3] = {
844 .data = &(struct vc3_div_data) {
845 .offs = VC3_OUT_DIV3_DIV4_CTRL,
846 .table = div3_divs,
847 .shift = 4,
848 .width = 4,
849 .flags = CLK_DIVIDER_READ_ONLY
850 },
851 .hw.init = &(struct clk_init_data){
852 .name = "div3",
853 .ops = &vc3_div_ops,
854 .parent_hws = (const struct clk_hw *[]) {
855 &clk_div_mux[VC3_DIV3_MUX].hw
856 },
857 .num_parents = 1,
858 .flags = CLK_SET_RATE_PARENT
859 }
860 },
861 [VC3_DIV4] = {
862 .data = &(struct vc3_div_data) {
863 .offs = VC3_OUT_DIV3_DIV4_CTRL,
864 .table = div245_divs,
865 .shift = 0,
866 .width = 4,
867 .flags = CLK_DIVIDER_READ_ONLY
868 },
869 .hw.init = &(struct clk_init_data){
870 .name = "div4",
871 .ops = &vc3_div_ops,
872 .parent_hws = (const struct clk_hw *[]) {
873 &clk_div_mux[VC3_DIV4_MUX].hw
874 },
875 .num_parents = 1,
876 .flags = CLK_SET_RATE_PARENT
877 }
878 },
879 [VC3_DIV5] = {
880 .data = &(struct vc3_div_data) {
881 .offs = VC3_PLL1_CTRL_OUTDIV5,
882 .table = div245_divs,
883 .shift = 0,
884 .width = 4,
885 .flags = CLK_DIVIDER_READ_ONLY
886 },
887 .hw.init = &(struct clk_init_data){
888 .name = "div5",
889 .ops = &vc3_div_ops,
890 .parent_hws = (const struct clk_hw *[]) {
891 &clk_pll[VC3_PLL3].hw
892 },
893 .num_parents = 1,
894 .flags = CLK_SET_RATE_PARENT
895 }
896 }
897 };
898
899 static struct vc3_hw_data clk_mux[] = {
900 [VC3_DIFF2_MUX] = {
901 .data = &(struct vc3_clk_data) {
902 .offs = VC3_DIFF2_CTRL_REG,
903 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
904 },
905 .hw.init = &(struct clk_init_data){
906 .name = "diff2_mux",
907 .ops = &vc3_clk_mux_ops,
908 .parent_hws = (const struct clk_hw *[]) {
909 &clk_div[VC3_DIV1].hw,
910 &clk_div[VC3_DIV3].hw
911 },
912 .num_parents = 2,
913 .flags = CLK_SET_RATE_PARENT
914 }
915 },
916 [VC3_DIFF1_MUX] = {
917 .data = &(struct vc3_clk_data) {
918 .offs = VC3_DIFF1_CTRL_REG,
919 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
920 },
921 .hw.init = &(struct clk_init_data){
922 .name = "diff1_mux",
923 .ops = &vc3_clk_mux_ops,
924 .parent_hws = (const struct clk_hw *[]) {
925 &clk_div[VC3_DIV1].hw,
926 &clk_div[VC3_DIV3].hw
927 },
928 .num_parents = 2,
929 .flags = CLK_SET_RATE_PARENT
930 }
931 },
932 [VC3_SE3_MUX] = {
933 .data = &(struct vc3_clk_data) {
934 .offs = VC3_SE3_DIFF1_CTRL_REG,
935 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
936 },
937 .hw.init = &(struct clk_init_data){
938 .name = "se3_mux",
939 .ops = &vc3_clk_mux_ops,
940 .parent_hws = (const struct clk_hw *[]) {
941 &clk_div[VC3_DIV2].hw,
942 &clk_div[VC3_DIV4].hw
943 },
944 .num_parents = 2,
945 .flags = CLK_SET_RATE_PARENT
946 }
947 },
948 [VC3_SE2_MUX] = {
949 .data = &(struct vc3_clk_data) {
950 .offs = VC3_SE2_CTRL_REG0,
951 .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
952 },
953 .hw.init = &(struct clk_init_data){
954 .name = "se2_mux",
955 .ops = &vc3_clk_mux_ops,
956 .parent_hws = (const struct clk_hw *[]) {
957 &clk_div[VC3_DIV5].hw,
958 &clk_div[VC3_DIV4].hw
959 },
960 .num_parents = 2,
961 .flags = CLK_SET_RATE_PARENT
962 }
963 },
964 [VC3_SE1_MUX] = {
965 .data = &(struct vc3_clk_data) {
966 .offs = VC3_SE1_DIV4_CTRL,
967 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
968 },
969 .hw.init = &(struct clk_init_data){
970 .name = "se1_mux",
971 .ops = &vc3_clk_mux_ops,
972 .parent_hws = (const struct clk_hw *[]) {
973 &clk_div[VC3_DIV5].hw,
974 &clk_div[VC3_DIV4].hw
975 },
976 .num_parents = 2,
977 .flags = CLK_SET_RATE_PARENT
978 }
979 }
980 };
981
982 static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
983 void *data)
984 {
985 unsigned int idx = clkspec->args[0];
986 struct clk_hw **clkout_hw = data;
987
988 if (idx >= ARRAY_SIZE(clk_out)) {
989 pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np);
990 return ERR_PTR(-EINVAL);
991 }
992
993 return clkout_hw[idx];
994 }
995
996 static int vc3_probe(struct i2c_client *client)
997 {
998 struct device *dev = &client->dev;
999 u8 settings[NUM_CONFIG_REGISTERS];
1000 struct regmap *regmap;
1001 const char *name;
1002 int ret, i;
1003
1004 regmap = devm_regmap_init_i2c(client, &vc3_regmap_config);
1005 if (IS_ERR(regmap))
1006 return dev_err_probe(dev, PTR_ERR(regmap),
1007 "failed to allocate register map\n");
1008
1009 ret = of_property_read_u8_array(dev->of_node, "renesas,settings",
1010 settings, ARRAY_SIZE(settings));
1011 if (!ret) {
1012 /*
1013 * A raw settings array was specified in the DT. Write the
1014 * settings to the device immediately.
1015 */
1016 for (i = 0; i < NUM_CONFIG_REGISTERS; i++) {
1017 ret = regmap_write(regmap, i, settings[i]);
1018 if (ret) {
1019 dev_err(dev, "error writing to chip (%i)\n", ret);
1020 return ret;
1021 }
1022 }
1023 } else if (ret == -EOVERFLOW) {
1024 dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n",
1025 ARRAY_SIZE(settings));
1026 return ret;
1027 }
1028
1029 /* Register pfd muxes */
1030 for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) {
1031 clk_pfd_mux[i].regmap = regmap;
1032 ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw);
1033 if (ret)
1034 return dev_err_probe(dev, ret, "%s failed\n",
1035 clk_pfd_mux[i].hw.init->name);
1036 }
1037
1038 /* Register pfd's */
1039 for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) {
1040 clk_pfd[i].regmap = regmap;
1041 ret = devm_clk_hw_register(dev, &clk_pfd[i].hw);
1042 if (ret)
1043 return dev_err_probe(dev, ret, "%s failed\n",
1044 clk_pfd[i].hw.init->name);
1045 }
1046
1047 /* Register pll's */
1048 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
1049 clk_pll[i].regmap = regmap;
1050 ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
1051 if (ret)
1052 return dev_err_probe(dev, ret, "%s failed\n",
1053 clk_pll[i].hw.init->name);
1054 }
1055
1056 /* Register divider muxes */
1057 for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) {
1058 clk_div_mux[i].regmap = regmap;
1059 ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw);
1060 if (ret)
1061 return dev_err_probe(dev, ret, "%s failed\n",
1062 clk_div_mux[i].hw.init->name);
1063 }
1064
1065 /* Register dividers */
1066 for (i = 0; i < ARRAY_SIZE(clk_div); i++) {
1067 clk_div[i].regmap = regmap;
1068 ret = devm_clk_hw_register(dev, &clk_div[i].hw);
1069 if (ret)
1070 return dev_err_probe(dev, ret, "%s failed\n",
1071 clk_div[i].hw.init->name);
1072 }
1073
1074 /* Register clk muxes */
1075 for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
1076 clk_mux[i].regmap = regmap;
1077 ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
1078 if (ret)
1079 return dev_err_probe(dev, ret, "%s failed\n",
1080 clk_mux[i].hw.init->name);
1081 }
1082
1083 /* Register clk outputs */
1084 for (i = 0; i < ARRAY_SIZE(clk_out); i++) {
1085 switch (i) {
1086 case VC3_DIFF2:
1087 name = "diff2";
1088 break;
1089 case VC3_DIFF1:
1090 name = "diff1";
1091 break;
1092 case VC3_SE3:
1093 name = "se3";
1094 break;
1095 case VC3_SE2:
1096 name = "se2";
1097 break;
1098 case VC3_SE1:
1099 name = "se1";
1100 break;
1101 case VC3_REF:
1102 name = "ref";
1103 break;
1104 default:
1105 return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i);
1106 }
1107
1108 if (i == VC3_REF)
1109 clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev,
1110 name, 0, CLK_SET_RATE_PARENT, 1, 1);
1111 else
1112 clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev,
1113 name, &clk_mux[i].hw, CLK_SET_RATE_PARENT, 1, 1);
1114
1115 if (IS_ERR(clk_out[i]))
1116 return PTR_ERR(clk_out[i]);
1117 }
1118
1119 ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out);
1120 if (ret)
1121 return dev_err_probe(dev, ret, "unable to add clk provider\n");
1122
1123 return ret;
1124 }
1125
1126 static const struct of_device_id dev_ids[] = {
1127 { .compatible = "renesas,5p35023" },
1128 { /* Sentinel */ }
1129 };
1130 MODULE_DEVICE_TABLE(of, dev_ids);
1131
1132 static struct i2c_driver vc3_driver = {
1133 .driver = {
1134 .name = "vc3",
1135 .of_match_table = of_match_ptr(dev_ids),
1136 },
1137 .probe = vc3_probe,
1138 };
1139 module_i2c_driver(vc3_driver);
1140
1141 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1142 MODULE_DESCRIPTION("Renesas VersaClock 3 driver");
1143 MODULE_LICENSE("GPL");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git