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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/clk/clk_stm32f7.c
fcdc3c052bd80b29e3846b89197b65170c4ed916
3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
11 #include <asm/arch/rcc.h>
12 #include <asm/arch/stm32.h>
13 #include <asm/arch/stm32_periph.h>
15 #define RCC_CR_HSION BIT(0)
16 #define RCC_CR_HSEON BIT(16)
17 #define RCC_CR_HSERDY BIT(17)
18 #define RCC_CR_HSEBYP BIT(18)
19 #define RCC_CR_CSSON BIT(19)
20 #define RCC_CR_PLLON BIT(24)
21 #define RCC_CR_PLLRDY BIT(25)
23 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
24 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
25 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
26 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
27 #define RCC_PLLCFGR_PLLSRC BIT(22)
28 #define RCC_PLLCFGR_PLLM_SHIFT 0
29 #define RCC_PLLCFGR_PLLN_SHIFT 6
30 #define RCC_PLLCFGR_PLLP_SHIFT 16
31 #define RCC_PLLCFGR_PLLQ_SHIFT 24
33 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
34 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
35 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
36 #define RCC_CFGR_SW0 BIT(0)
37 #define RCC_CFGR_SW1 BIT(1)
38 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
39 #define RCC_CFGR_SW_HSI 0
40 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
41 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
42 #define RCC_CFGR_SWS0 BIT(2)
43 #define RCC_CFGR_SWS1 BIT(3)
44 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
45 #define RCC_CFGR_SWS_HSI 0
46 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
47 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
48 #define RCC_CFGR_HPRE_SHIFT 4
49 #define RCC_CFGR_PPRE1_SHIFT 10
50 #define RCC_CFGR_PPRE2_SHIFT 13
53 * Offsets of some PWR registers
55 #define PWR_CR1_ODEN BIT(16)
56 #define PWR_CR1_ODSWEN BIT(17)
57 #define PWR_CSR1_ODRDY BIT(16)
58 #define PWR_CSR1_ODSWRDY BIT(17)
74 #define AHB_PSC_16 0xB
75 #define AHB_PSC_64 0xC
76 #define AHB_PSC_128 0xD
77 #define AHB_PSC_256 0xE
78 #define AHB_PSC_512 0xF
84 #define APB_PSC_16 0x7
86 #if !defined(CONFIG_STM32_HSE_HZ)
87 #error "CONFIG_STM32_HSE_HZ not defined!"
89 #if (CONFIG_STM32_HSE_HZ == 25000000)
90 #if (CONFIG_SYS_CLK_FREQ == 200000000)
92 struct pll_psc sys_pll_psc
= {
98 .apb1_psc
= APB_PSC_4
,
103 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
107 int configure_clocks(void)
109 /* Reset RCC configuration */
110 setbits_le32(&STM32_RCC
->cr
, RCC_CR_HSION
);
111 writel(0, &STM32_RCC
->cfgr
); /* Reset CFGR */
112 clrbits_le32(&STM32_RCC
->cr
, (RCC_CR_HSEON
| RCC_CR_CSSON
114 writel(0x24003010, &STM32_RCC
->pllcfgr
); /* Reset value from RM */
115 clrbits_le32(&STM32_RCC
->cr
, RCC_CR_HSEBYP
);
116 writel(0, &STM32_RCC
->cir
); /* Disable all interrupts */
118 /* Configure for HSE+PLL operation */
119 setbits_le32(&STM32_RCC
->cr
, RCC_CR_HSEON
);
120 while (!(readl(&STM32_RCC
->cr
) & RCC_CR_HSERDY
))
123 setbits_le32(&STM32_RCC
->cfgr
, ((
124 sys_pll_psc
.ahb_psc
<< RCC_CFGR_HPRE_SHIFT
)
125 | (sys_pll_psc
.apb1_psc
<< RCC_CFGR_PPRE1_SHIFT
)
126 | (sys_pll_psc
.apb2_psc
<< RCC_CFGR_PPRE2_SHIFT
)));
128 /* Configure the main PLL */
129 uint32_t pllcfgr
= 0;
130 pllcfgr
= RCC_PLLCFGR_PLLSRC
; /* pll source HSE */
131 pllcfgr
|= sys_pll_psc
.pll_m
<< RCC_PLLCFGR_PLLM_SHIFT
;
132 pllcfgr
|= sys_pll_psc
.pll_n
<< RCC_PLLCFGR_PLLN_SHIFT
;
133 pllcfgr
|= ((sys_pll_psc
.pll_p
>> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT
;
134 pllcfgr
|= sys_pll_psc
.pll_q
<< RCC_PLLCFGR_PLLQ_SHIFT
;
135 writel(pllcfgr
, &STM32_RCC
->pllcfgr
);
137 /* Enable the main PLL */
138 setbits_le32(&STM32_RCC
->cr
, RCC_CR_PLLON
);
139 while (!(readl(&STM32_RCC
->cr
) & RCC_CR_PLLRDY
))
142 /* Enable high performance mode, System frequency up to 200 MHz */
143 setbits_le32(&STM32_RCC
->apb1enr
, RCC_APB1ENR_PWREN
);
144 setbits_le32(&STM32_PWR
->cr1
, PWR_CR1_ODEN
);
146 while (!(readl(&STM32_PWR
->csr1
) & PWR_CSR1_ODRDY
))
148 /* Enable the Over-drive switch */
149 setbits_le32(&STM32_PWR
->cr1
, PWR_CR1_ODSWEN
);
151 while (!(readl(&STM32_PWR
->csr1
) & PWR_CSR1_ODSWRDY
))
154 stm32_flash_latency_cfg(5);
155 clrbits_le32(&STM32_RCC
->cfgr
, (RCC_CFGR_SW0
| RCC_CFGR_SW1
));
156 setbits_le32(&STM32_RCC
->cfgr
, RCC_CFGR_SW_PLL
);
158 while ((readl(&STM32_RCC
->cfgr
) & RCC_CFGR_SWS_MASK
) !=
165 unsigned long clock_get(enum clock clck
)
169 /* Prescaler table lookups for clock computation */
170 u8 ahb_psc_table
[16] = {
171 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
173 u8 apb_psc_table
[8] = {
174 0, 0, 0, 0, 1, 2, 3, 4
177 if ((readl(&STM32_RCC
->cfgr
) & RCC_CFGR_SWS_MASK
) ==
179 u16 pllm
, plln
, pllp
;
180 pllm
= (readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLM_MASK
);
181 plln
= ((readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLN_MASK
)
182 >> RCC_PLLCFGR_PLLN_SHIFT
);
183 pllp
= ((((readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLP_MASK
)
184 >> RCC_PLLCFGR_PLLP_SHIFT
) + 1) << 1);
185 sysclk
= ((CONFIG_STM32_HSE_HZ
/ pllm
) * plln
) / pllp
;
193 shift
= ahb_psc_table
[(
194 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_AHB_PSC_MASK
)
195 >> RCC_CFGR_HPRE_SHIFT
)];
196 return sysclk
>>= shift
;
199 shift
= apb_psc_table
[(
200 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_APB1_PSC_MASK
)
201 >> RCC_CFGR_PPRE1_SHIFT
)];
202 return sysclk
>>= shift
;
205 shift
= apb_psc_table
[(
206 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_APB2_PSC_MASK
)
207 >> RCC_CFGR_PPRE2_SHIFT
)];
208 return sysclk
>>= shift
;
216 static int stm32_clk_enable(struct clk
*clk
)
218 u32 offset
= clk
->id
/ 32;
219 u32 bit_index
= clk
->id
% 32;
221 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
222 __func__
, clk
->id
, offset
, bit_index
);
223 setbits_le32(&STM32_RCC
->ahb1enr
+ offset
, BIT(bit_index
));
228 void clock_setup(int peripheral
)
230 switch (peripheral
) {
231 case SYSCFG_CLOCK_CFG
:
232 setbits_le32(&STM32_RCC
->apb2enr
, RCC_APB2ENR_SYSCFGEN
);
234 case TIMER2_CLOCK_CFG
:
235 setbits_le32(&STM32_RCC
->apb1enr
, RCC_APB1ENR_TIM2EN
);
237 case STMMAC_CLOCK_CFG
:
238 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_AHB1ENR_ETHMAC_EN
);
239 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_AHB1ENR_ETHMAC_RX_EN
);
240 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_AHB1ENR_ETHMAC_TX_EN
);
247 static int stm32_clk_probe(struct udevice
*dev
)
249 debug("%s: stm32_clk_probe\n", __func__
);
255 static int stm32_clk_of_xlate(struct clk
*clk
, struct ofnode_phandle_args
*args
)
257 debug("%s(clk=%p)\n", __func__
, clk
);
259 if (args
->args_count
!= 2) {
260 debug("Invaild args_count: %d\n", args
->args_count
);
264 if (args
->args_count
)
265 clk
->id
= args
->args
[1];
272 static struct clk_ops stm32_clk_ops
= {
273 .of_xlate
= stm32_clk_of_xlate
,
274 .enable
= stm32_clk_enable
,
277 static const struct udevice_id stm32_clk_ids
[] = {
278 { .compatible
= "st,stm32f42xx-rcc"},
282 U_BOOT_DRIVER(stm32f7_clk
) = {
283 .name
= "stm32f7_clk",
285 .of_match
= stm32_clk_ids
,
286 .ops
= &stm32_clk_ops
,
287 .probe
= stm32_clk_probe
,
288 .flags
= DM_FLAG_PRE_RELOC
,