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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/clk/clk_zynq.c
2 * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
3 * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
5 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
6 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <clk-uclass.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/sys_proto.h>
21 /* Register bitfield defines */
22 #define PLLCTRL_FBDIV_MASK 0x7f000
23 #define PLLCTRL_FBDIV_SHIFT 12
24 #define PLLCTRL_BPFORCE_MASK (1 << 4)
25 #define PLLCTRL_PWRDWN_MASK 2
26 #define PLLCTRL_PWRDWN_SHIFT 1
27 #define PLLCTRL_RESET_MASK 1
28 #define PLLCTRL_RESET_SHIFT 0
30 #define ZYNQ_CLK_MAXDIV 0x3f
31 #define CLK_CTRL_DIV1_SHIFT 20
32 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
33 #define CLK_CTRL_DIV0_SHIFT 8
34 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
35 #define CLK_CTRL_SRCSEL_SHIFT 4
36 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
38 #define CLK_CTRL_DIV2X_SHIFT 26
39 #define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
40 #define CLK_CTRL_DIV3X_SHIFT 20
41 #define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
43 DECLARE_GLOBAL_DATA_PTR
;
45 #ifndef CONFIG_SPL_BUILD
46 enum zynq_clk_rclk
{mio_clk
, emio_clk
};
49 struct zynq_clk_priv
{
51 #ifndef CONFIG_SPL_BUILD
52 struct clk gem_emio_clk
[2];
56 static void *zynq_clk_get_register(enum zynq_clk id
)
60 return &slcr_base
->arm_pll_ctrl
;
62 return &slcr_base
->ddr_pll_ctrl
;
64 return &slcr_base
->io_pll_ctrl
;
66 return &slcr_base
->lqspi_clk_ctrl
;
68 return &slcr_base
->smc_clk_ctrl
;
70 return &slcr_base
->pcap_clk_ctrl
;
71 case sdio0_clk
... sdio1_clk
:
72 return &slcr_base
->sdio_clk_ctrl
;
73 case uart0_clk
... uart1_clk
:
74 return &slcr_base
->uart_clk_ctrl
;
75 case spi0_clk
... spi1_clk
:
76 return &slcr_base
->spi_clk_ctrl
;
77 #ifndef CONFIG_SPL_BUILD
79 return &slcr_base
->dci_clk_ctrl
;
81 return &slcr_base
->gem0_clk_ctrl
;
83 return &slcr_base
->gem1_clk_ctrl
;
85 return &slcr_base
->fpga0_clk_ctrl
;
87 return &slcr_base
->fpga1_clk_ctrl
;
89 return &slcr_base
->fpga2_clk_ctrl
;
91 return &slcr_base
->fpga3_clk_ctrl
;
92 case can0_clk
... can1_clk
:
93 return &slcr_base
->can_clk_ctrl
;
94 case dbg_trc_clk
... dbg_apb_clk
:
98 return &slcr_base
->dbg_clk_ctrl
;
102 static enum zynq_clk
zynq_clk_get_cpu_pll(u32 clk_ctrl
)
104 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
117 static enum zynq_clk
zynq_clk_get_peripheral_pll(u32 clk_ctrl
)
119 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
132 static ulong
zynq_clk_get_pll_rate(struct zynq_clk_priv
*priv
, enum zynq_clk id
)
134 u32 clk_ctrl
, reset
, pwrdwn
, mul
, bypass
;
136 clk_ctrl
= readl(zynq_clk_get_register(id
));
138 reset
= (clk_ctrl
& PLLCTRL_RESET_MASK
) >> PLLCTRL_RESET_SHIFT
;
139 pwrdwn
= (clk_ctrl
& PLLCTRL_PWRDWN_MASK
) >> PLLCTRL_PWRDWN_SHIFT
;
143 bypass
= clk_ctrl
& PLLCTRL_BPFORCE_MASK
;
147 mul
= (clk_ctrl
& PLLCTRL_FBDIV_MASK
) >> PLLCTRL_FBDIV_SHIFT
;
149 return priv
->ps_clk_freq
* mul
;
152 #ifndef CONFIG_SPL_BUILD
153 static enum zynq_clk_rclk
zynq_clk_get_gem_rclk(enum zynq_clk id
)
155 u32 clk_ctrl
, srcsel
;
158 clk_ctrl
= readl(&slcr_base
->gem0_rclk_ctrl
);
160 clk_ctrl
= readl(&slcr_base
->gem1_rclk_ctrl
);
162 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
170 static ulong
zynq_clk_get_cpu_rate(struct zynq_clk_priv
*priv
, enum zynq_clk id
)
172 u32 clk_621
, clk_ctrl
, div
;
175 clk_ctrl
= readl(&slcr_base
->arm_clk_ctrl
);
177 div
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
184 clk_621
= readl(&slcr_base
->clk_621_true
) & 1;
196 pll
= zynq_clk_get_cpu_pll(clk_ctrl
);
198 return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv
, pll
), div
);
201 #ifndef CONFIG_SPL_BUILD
202 static ulong
zynq_clk_get_ddr2x_rate(struct zynq_clk_priv
*priv
)
206 clk_ctrl
= readl(&slcr_base
->ddr_clk_ctrl
);
208 div
= (clk_ctrl
& CLK_CTRL_DIV2X_MASK
) >> CLK_CTRL_DIV2X_SHIFT
;
210 return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv
, ddrpll_clk
), div
);
214 static ulong
zynq_clk_get_ddr3x_rate(struct zynq_clk_priv
*priv
)
218 clk_ctrl
= readl(&slcr_base
->ddr_clk_ctrl
);
220 div
= (clk_ctrl
& CLK_CTRL_DIV3X_MASK
) >> CLK_CTRL_DIV3X_SHIFT
;
222 return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv
, ddrpll_clk
), div
);
225 #ifndef CONFIG_SPL_BUILD
226 static ulong
zynq_clk_get_dci_rate(struct zynq_clk_priv
*priv
)
228 u32 clk_ctrl
, div0
, div1
;
230 clk_ctrl
= readl(&slcr_base
->dci_clk_ctrl
);
232 div0
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
233 div1
= (clk_ctrl
& CLK_CTRL_DIV1_MASK
) >> CLK_CTRL_DIV1_SHIFT
;
235 return DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(
236 zynq_clk_get_pll_rate(priv
, ddrpll_clk
), div0
), div1
);
240 static ulong
zynq_clk_get_peripheral_rate(struct zynq_clk_priv
*priv
,
241 enum zynq_clk id
, bool two_divs
)
247 clk_ctrl
= readl(zynq_clk_get_register(id
));
249 div0
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
253 #ifndef CONFIG_SPL_BUILD
255 div1
= (clk_ctrl
& CLK_CTRL_DIV1_MASK
) >> CLK_CTRL_DIV1_SHIFT
;
261 pll
= zynq_clk_get_peripheral_pll(clk_ctrl
);
266 zynq_clk_get_pll_rate(priv
, pll
), div0
),
270 #ifndef CONFIG_SPL_BUILD
271 static ulong
zynq_clk_get_gem_rate(struct zynq_clk_priv
*priv
, enum zynq_clk id
)
275 if (zynq_clk_get_gem_rclk(id
) == mio_clk
)
276 return zynq_clk_get_peripheral_rate(priv
, id
, true);
278 parent
= &priv
->gem_emio_clk
[id
- gem0_clk
];
280 return clk_get_rate(parent
);
282 debug("%s: gem%d emio rx clock source unknown\n", __func__
,
288 static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate
,
290 u32
*div0
, u32
*div1
)
292 long new_err
, best_err
= (long)(~0UL >> 1);
293 ulong new_rate
, best_rate
= 0;
296 for (d0
= 1; d0
<= ZYNQ_CLK_MAXDIV
; d0
++) {
297 for (d1
= 1; d1
<= ZYNQ_CLK_MAXDIV
>> 1; d1
++) {
298 new_rate
= DIV_ROUND_CLOSEST(
299 DIV_ROUND_CLOSEST(pll_rate
, d0
), d1
);
300 new_err
= abs(new_rate
- rate
);
302 if (new_err
< best_err
) {
306 best_rate
= new_rate
;
314 static ulong
zynq_clk_set_peripheral_rate(struct zynq_clk_priv
*priv
,
315 enum zynq_clk id
, ulong rate
,
319 u32 clk_ctrl
, div0
= 0, div1
= 0;
320 ulong pll_rate
, new_rate
;
323 reg
= zynq_clk_get_register(id
);
324 clk_ctrl
= readl(reg
);
326 pll
= zynq_clk_get_peripheral_pll(clk_ctrl
);
327 pll_rate
= zynq_clk_get_pll_rate(priv
, pll
);
328 clk_ctrl
&= ~CLK_CTRL_DIV0_MASK
;
330 clk_ctrl
&= ~CLK_CTRL_DIV1_MASK
;
331 new_rate
= zynq_clk_calc_peripheral_two_divs(rate
, pll_rate
,
333 clk_ctrl
|= div1
<< CLK_CTRL_DIV1_SHIFT
;
335 div0
= DIV_ROUND_CLOSEST(pll_rate
, rate
);
336 if (div0
> ZYNQ_CLK_MAXDIV
)
337 div0
= ZYNQ_CLK_MAXDIV
;
338 new_rate
= DIV_ROUND_CLOSEST(rate
, div0
);
340 clk_ctrl
|= div0
<< CLK_CTRL_DIV0_SHIFT
;
343 writel(clk_ctrl
, reg
);
349 static ulong
zynq_clk_set_gem_rate(struct zynq_clk_priv
*priv
, enum zynq_clk id
,
354 if (zynq_clk_get_gem_rclk(id
) == mio_clk
)
355 return zynq_clk_set_peripheral_rate(priv
, id
, rate
, true);
357 parent
= &priv
->gem_emio_clk
[id
- gem0_clk
];
359 return clk_set_rate(parent
, rate
);
361 debug("%s: gem%d emio rx clock source unknown\n", __func__
,
368 #ifndef CONFIG_SPL_BUILD
369 static ulong
zynq_clk_get_rate(struct clk
*clk
)
371 struct zynq_clk_priv
*priv
= dev_get_priv(clk
->dev
);
372 enum zynq_clk id
= clk
->id
;
373 bool two_divs
= false;
376 case armpll_clk
... iopll_clk
:
377 return zynq_clk_get_pll_rate(priv
, id
);
378 case cpu_6or4x_clk
... cpu_1x_clk
:
379 return zynq_clk_get_cpu_rate(priv
, id
);
381 return zynq_clk_get_ddr2x_rate(priv
);
383 return zynq_clk_get_ddr3x_rate(priv
);
385 return zynq_clk_get_dci_rate(priv
);
386 case gem0_clk
... gem1_clk
:
387 return zynq_clk_get_gem_rate(priv
, id
);
388 case fclk0_clk
... can1_clk
:
391 case dbg_trc_clk
... dbg_apb_clk
:
392 case lqspi_clk
... pcap_clk
:
393 case sdio0_clk
... spi1_clk
:
394 return zynq_clk_get_peripheral_rate(priv
, id
, two_divs
);
396 return zynq_clk_get_cpu_rate(priv
, cpu_2x_clk
);
397 case usb0_aper_clk
... smc_aper_clk
:
398 return zynq_clk_get_cpu_rate(priv
, cpu_1x_clk
);
404 static ulong
zynq_clk_set_rate(struct clk
*clk
, ulong rate
)
406 struct zynq_clk_priv
*priv
= dev_get_priv(clk
->dev
);
407 enum zynq_clk id
= clk
->id
;
408 bool two_divs
= false;
411 case gem0_clk
... gem1_clk
:
412 return zynq_clk_set_gem_rate(priv
, id
, rate
);
413 case fclk0_clk
... can1_clk
:
416 case lqspi_clk
... pcap_clk
:
417 case sdio0_clk
... spi1_clk
:
418 case dbg_trc_clk
... dbg_apb_clk
:
419 return zynq_clk_set_peripheral_rate(priv
, id
, rate
, two_divs
);
425 static ulong
zynq_clk_get_rate(struct clk
*clk
)
427 struct zynq_clk_priv
*priv
= dev_get_priv(clk
->dev
);
428 enum zynq_clk id
= clk
->id
;
431 case cpu_6or4x_clk
... cpu_1x_clk
:
432 return zynq_clk_get_cpu_rate(priv
, id
);
434 return zynq_clk_get_ddr3x_rate(priv
);
435 case lqspi_clk
... pcap_clk
:
436 case sdio0_clk
... spi1_clk
:
437 return zynq_clk_get_peripheral_rate(priv
, id
, 0);
444 static struct clk_ops zynq_clk_ops
= {
445 .get_rate
= zynq_clk_get_rate
,
446 #ifndef CONFIG_SPL_BUILD
447 .set_rate
= zynq_clk_set_rate
,
451 static int zynq_clk_probe(struct udevice
*dev
)
453 struct zynq_clk_priv
*priv
= dev_get_priv(dev
);
454 #ifndef CONFIG_SPL_BUILD
459 for (i
= 0; i
< 2; i
++) {
460 sprintf(name
, "gem%d_emio_clk", i
);
461 ret
= clk_get_by_name(dev
, name
, &priv
->gem_emio_clk
[i
]);
462 if (ret
< 0 && ret
!= -FDT_ERR_NOTFOUND
) {
463 dev_err(dev
, "failed to get %s clock\n", name
);
469 priv
->ps_clk_freq
= fdtdec_get_uint(gd
->fdt_blob
, dev
->of_offset
,
470 "ps-clk-frequency", 33333333UL);
475 static const struct udevice_id zynq_clk_ids
[] = {
476 { .compatible
= "xlnx,ps7-clkc"},
480 U_BOOT_DRIVER(zynq_clk
) = {
483 .of_match
= zynq_clk_ids
,
484 .flags
= DM_FLAG_PRE_RELOC
,
485 .ops
= &zynq_clk_ops
,
486 .priv_auto_alloc_size
= sizeof(struct zynq_clk_priv
),
487 .probe
= zynq_clk_probe
,