4 * Copyright (C) 2016 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
11 #include <clk-uclass.h>
12 #include <dm/device.h>
15 #define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050
16 #define ZYNQMP_IOPLL_CTRL 0xFF5E0020
17 #define ZYNQMP_RPLL_CTRL 0xFF5E0030
18 #define ZYNQMP_DPLL_CTRL 0xFD1A002C
19 #define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
20 #define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
21 #define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
22 #define ZYNQMP_SIP_SVC_MMIO_READ 0xC2000014
23 #define ZYNQMP_DIV_MAX_VAL 0x3F
24 #define ZYNQMP_DIV1_SHFT 8
25 #define ZYNQMP_DIV1_SHFT 8
26 #define ZYNQMP_DIV2_SHFT 16
27 #define ZYNQMP_DIV_MASK 0x3F
28 #define ZYNQMP_PLL_CTRL_FBDIV_MASK 0x7F
29 #define ZYNQMP_PLL_CTRL_FBDIV_SHFT 8
30 #define ZYNQMP_GEM_REF_CTRL_SRC_MASK 0x7
31 #define ZYNQMP_GEM0_CLK_ID 45
32 #define ZYNQMP_GEM1_CLK_ID 46
33 #define ZYNQMP_GEM2_CLK_ID 47
34 #define ZYNQMP_GEM3_CLK_ID 48
36 static unsigned long pss_ref_clk
;
38 static int zynqmp_calculate_divisors(unsigned long req_rate
,
39 unsigned long parent_rate
,
46 * calculate two divisors to get
47 * required rate and each divisor
48 * should be less than 63
50 req_div
= DIV_ROUND_UP(parent_rate
, req_rate
);
52 for (i
= 1; i
<= req_div
; i
++) {
53 if ((req_div
% i
) == 0) {
56 if ((*div1
< ZYNQMP_DIV_MAX_VAL
) &&
57 (*div2
< ZYNQMP_DIV_MAX_VAL
))
65 static int zynqmp_get_periph_id(unsigned long id
)
70 case ZYNQMP_GEM0_CLK_ID
:
73 case ZYNQMP_GEM1_CLK_ID
:
76 case ZYNQMP_GEM2_CLK_ID
:
79 case ZYNQMP_GEM3_CLK_ID
:
83 printf("%s, Invalid clock id:%ld\n", __func__
, id
);
90 static int zynqmp_set_clk(unsigned long id
, u32 div1
, u32 div2
)
96 id
= zynqmp_get_periph_id(id
);
100 reg
= (ulong
)((u32
*)ZYNQMP_GEM0_REF_CTRL
+ id
);
101 mask
= (ZYNQMP_DIV_MASK
<< ZYNQMP_DIV1_SHFT
) |
102 (ZYNQMP_DIV_MASK
<< ZYNQMP_DIV2_SHFT
);
103 value
= (div1
<< ZYNQMP_DIV1_SHFT
) | (div2
<< ZYNQMP_DIV2_SHFT
);
105 debug("%s: reg:0x%lx, mask:0x%x, value:0x%x\n", __func__
, reg
, mask
,
108 regs
.regs
[0] = ZYNQMP_SIP_SVC_MMIO_WRITE
;
109 regs
.regs
[1] = ((u64
)mask
<< 32) | reg
;
110 regs
.regs
[2] = value
;
118 static unsigned long zynqmp_clk_get_rate(struct clk
*clk
)
125 id
= zynqmp_get_periph_id(clk
->id
);
129 reg
= (ulong
)((u32
*)ZYNQMP_GEM0_REF_CTRL
+ id
);
131 regs
.regs
[0] = ZYNQMP_SIP_SVC_MMIO_READ
;
138 value
= upper_32_bits(regs
.regs
[0]);
140 value
&= ZYNQMP_GEM_REF_CTRL_SRC_MASK
;
144 regs
.regs
[1] = ZYNQMP_IOPLL_CTRL
;
147 regs
.regs
[1] = ZYNQMP_RPLL_CTRL
;
150 regs
.regs
[1] = ZYNQMP_DPLL_CTRL
;
156 regs
.regs
[0] = ZYNQMP_SIP_SVC_MMIO_READ
;
162 value
= upper_32_bits(regs
.regs
[0]) &
163 (ZYNQMP_PLL_CTRL_FBDIV_MASK
<<
164 ZYNQMP_PLL_CTRL_FBDIV_SHFT
);
165 value
>>= ZYNQMP_PLL_CTRL_FBDIV_SHFT
;
166 value
*= pss_ref_clk
;
171 static ulong
zynqmp_clk_set_rate(struct clk
*clk
, unsigned long clk_rate
)
176 unsigned long input_clk
;
178 input_clk
= zynqmp_clk_get_rate(clk
);
179 if (IS_ERR_VALUE(input_clk
)) {
180 dev_err(dev
, "failed to get input_clk\n");
184 debug("%s: i/p CLK %ld, clk_rate:0x%ld\n", __func__
, input_clk
,
187 ret
= zynqmp_calculate_divisors(clk_rate
, input_clk
, &div1
, &div2
);
189 dev_err(dev
, "failed to proper divisors\n");
193 debug("%s: Div1:%d, Div2:%d\n", __func__
, div1
, div2
);
195 ret
= zynqmp_set_clk(clk
->id
, div1
, div2
);
197 dev_err(dev
, "failed to set gem clk\n");
204 static int zynqmp_clk_probe(struct udevice
*dev
)
209 debug("%s\n", __func__
);
210 ret
= clk_get_by_name(dev
, "pss_ref_clk", &clk
);
212 dev_err(dev
, "failed to get pss_ref_clk\n");
216 pss_ref_clk
= clk_get_rate(&clk
);
217 if (IS_ERR_VALUE(pss_ref_clk
)) {
218 dev_err(dev
, "failed to get rate pss_ref_clk\n");
225 static struct clk_ops zynqmp_clk_ops
= {
226 .set_rate
= zynqmp_clk_set_rate
,
227 .get_rate
= zynqmp_clk_get_rate
,
230 static const struct udevice_id zynqmp_clk_ids
[] = {
231 { .compatible
= "xlnx,zynqmp-clkc" },
235 U_BOOT_DRIVER(zynqmp_clk
) = {
236 .name
= "zynqmp-clk",
238 .of_match
= zynqmp_clk_ids
,
239 .probe
= zynqmp_clk_probe
,
240 .ops
= &zynqmp_clk_ops
,