4 * Copyright (C) 2016 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
11 #include <clk-uclass.h>
13 #include <asm/arch/sys_proto.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 static const resource_size_t zynqmp_crf_apb_clkc_base
= 0xfd1a0020;
19 static const resource_size_t zynqmp_crl_apb_clkc_base
= 0xff5e0020;
21 /* Full power domain clocks */
22 #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
23 #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
24 #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
25 #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
26 #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
27 #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
28 #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
29 /* Peripheral clocks */
30 #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
31 #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
32 #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
33 #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
34 #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
35 #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
36 #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
37 #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
38 #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
39 #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
40 #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
41 #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
42 #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
43 #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
44 #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
45 #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
47 /* Low power domain clocks */
48 #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
49 #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
50 #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
51 #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
52 #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
53 /* Peripheral clocks */
54 #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
55 #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
56 #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
57 #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
58 #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
59 #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
60 #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
61 #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
62 #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
63 #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
64 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
65 #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
66 #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
67 #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
68 #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
69 #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
70 #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
71 #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
72 #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
73 #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
74 #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
75 #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
76 #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
77 #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
78 #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
79 #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
80 #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
81 #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
82 #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
83 #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
84 #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
85 #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
86 #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
87 #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
88 #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
89 #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
90 #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
91 #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
92 #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
94 #define ZYNQ_CLK_MAXDIV 0x3f
95 #define CLK_CTRL_DIV1_SHIFT 16
96 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
97 #define CLK_CTRL_DIV0_SHIFT 8
98 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
99 #define CLK_CTRL_SRCSEL_SHIFT 0
100 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
101 #define PLLCTRL_FBDIV_MASK 0x7f00
102 #define PLLCTRL_FBDIV_SHIFT 8
103 #define PLLCTRL_RESET_MASK 1
104 #define PLLCTRL_RESET_SHIFT 0
105 #define PLLCTRL_BYPASS_MASK 0x8
106 #define PLLCTRL_BYPASS_SHFT 3
107 #define PLLCTRL_POST_SRC_SHFT 24
108 #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
111 #define NUM_MIO_PINS 77
116 iopll_to_fpd
, rpll_to_fpd
, apll_to_lpd
, dpll_to_lpd
, vpll_to_lpd
,
118 dbg_fpd
, dbg_lpd
, dbg_trace
, dbg_tstmp
,
119 dp_video_ref
, dp_audio_ref
,
120 dp_stc_ref
, gdma_ref
, dpdma_ref
,
121 ddr_ref
, sata_ref
, pcie_ref
,
122 gpu_ref
, gpu_pp0_ref
, gpu_pp1_ref
,
123 topsw_main
, topsw_lsbus
,
125 lpd_switch
, lpd_lsbus
,
126 usb0_bus_ref
, usb1_bus_ref
, usb3_dual_ref
, usb0
, usb1
,
128 csu_spb
, csu_pll
, pcap
,
130 gem_tsu_ref
, gem_tsu
,
131 gem0_ref
, gem1_ref
, gem2_ref
, gem3_ref
,
132 gem0_rx
, gem1_rx
, gem2_rx
, gem3_rx
,
134 sdio0_ref
, sdio1_ref
,
135 uart0_ref
, uart1_ref
,
138 i2c0_ref
, i2c1_ref
, can0_ref
, can1_ref
, can0
, can1
,
148 static const char * const clk_names
[clk_max
] = {
149 "iopll", "rpll", "apll", "dpll",
150 "vpll", "iopll_to_fpd", "rpll_to_fpd",
151 "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
152 "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
153 "dbg_trace", "dbg_tstmp", "dp_video_ref",
154 "dp_audio_ref", "dp_stc_ref", "gdma_ref",
155 "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
156 "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
157 "topsw_main", "topsw_lsbus", "gtgref0_ref",
158 "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
159 "usb1_bus_ref", "usb3_dual_ref", "usb0",
160 "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
161 "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
162 "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
163 "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
164 "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
165 "uart0_ref", "uart1_ref", "spi0_ref",
166 "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
167 "can0_ref", "can1_ref", "can0", "can1",
168 "dll_ref", "adma_ref", "timestamp_ref",
169 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
172 struct zynqmp_clk_priv
{
173 unsigned long ps_clk_freq
;
174 unsigned long video_clk
;
175 unsigned long pss_alt_ref_clk
;
176 unsigned long gt_crx_ref_clk
;
177 unsigned long aux_ref_clk
;
180 static u32
zynqmp_clk_get_register(enum zynqmp_clk id
)
184 return CRL_APB_IOPLL_CTRL
;
186 return CRL_APB_RPLL_CTRL
;
188 return CRF_APB_APLL_CTRL
;
190 return CRF_APB_DPLL_CTRL
;
192 return CRF_APB_VPLL_CTRL
;
194 return CRF_APB_ACPU_CTRL
;
196 return CRF_APB_DDR_CTRL
;
198 return CRL_APB_QSPI_REF_CTRL
;
200 return CRL_APB_GEM0_REF_CTRL
;
202 return CRL_APB_GEM1_REF_CTRL
;
204 return CRL_APB_GEM2_REF_CTRL
;
206 return CRL_APB_GEM3_REF_CTRL
;
208 return CRL_APB_UART0_REF_CTRL
;
210 return CRL_APB_UART1_REF_CTRL
;
212 return CRL_APB_SDIO0_REF_CTRL
;
214 return CRL_APB_SDIO1_REF_CTRL
;
216 return CRL_APB_SPI0_REF_CTRL
;
218 return CRL_APB_SPI1_REF_CTRL
;
220 return CRL_APB_NAND_REF_CTRL
;
222 return CRL_APB_I2C0_REF_CTRL
;
224 return CRL_APB_I2C1_REF_CTRL
;
226 return CRL_APB_CAN0_REF_CTRL
;
228 return CRL_APB_CAN1_REF_CTRL
;
230 debug("Invalid clk id%d\n", id
);
235 static enum zynqmp_clk
zynqmp_clk_get_cpu_pll(u32 clk_ctrl
)
237 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >>
238 CLK_CTRL_SRCSEL_SHIFT
;
251 static enum zynqmp_clk
zynqmp_clk_get_ddr_pll(u32 clk_ctrl
)
253 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >>
254 CLK_CTRL_SRCSEL_SHIFT
;
265 static enum zynqmp_clk
zynqmp_clk_get_peripheral_pll(u32 clk_ctrl
)
267 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >>
268 CLK_CTRL_SRCSEL_SHIFT
;
281 static ulong
zynqmp_clk_get_pll_src(ulong clk_ctrl
,
282 struct zynqmp_clk_priv
*priv
,
288 src_sel
= (clk_ctrl
& PLLCTRL_POST_SRC_MASK
) >>
289 PLLCTRL_POST_SRC_SHFT
;
291 src_sel
= (clk_ctrl
& PLLCTRL_POST_SRC_MASK
) >>
292 PLLCTRL_POST_SRC_SHFT
;
296 return priv
->video_clk
;
298 return priv
->pss_alt_ref_clk
;
300 return priv
->aux_ref_clk
;
302 return priv
->gt_crx_ref_clk
;
305 return priv
->ps_clk_freq
;
309 static ulong
zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv
*priv
,
312 u32 clk_ctrl
, reset
, mul
;
316 ret
= zynqmp_mmio_read(zynqmp_clk_get_register(id
), &clk_ctrl
);
318 printf("%s mio read fail\n", __func__
);
322 if (clk_ctrl
& PLLCTRL_BYPASS_MASK
)
323 freq
= zynqmp_clk_get_pll_src(clk_ctrl
, priv
, 0);
325 freq
= zynqmp_clk_get_pll_src(clk_ctrl
, priv
, 1);
327 reset
= (clk_ctrl
& PLLCTRL_RESET_MASK
) >> PLLCTRL_RESET_SHIFT
;
328 if (reset
&& !(clk_ctrl
& PLLCTRL_BYPASS_MASK
))
331 mul
= (clk_ctrl
& PLLCTRL_FBDIV_MASK
) >> PLLCTRL_FBDIV_SHIFT
;
335 if (clk_ctrl
& (1 << 16))
341 static ulong
zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv
*priv
,
347 unsigned long pllrate
;
349 ret
= zynqmp_mmio_read(CRF_APB_ACPU_CTRL
, &clk_ctrl
);
351 printf("%s mio read fail\n", __func__
);
355 div
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
357 pll
= zynqmp_clk_get_cpu_pll(clk_ctrl
);
358 pllrate
= zynqmp_clk_get_pll_rate(priv
, pll
);
359 if (IS_ERR_VALUE(pllrate
))
362 return DIV_ROUND_CLOSEST(pllrate
, div
);
365 static ulong
zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv
*priv
)
372 ret
= zynqmp_mmio_read(CRF_APB_DDR_CTRL
, &clk_ctrl
);
374 printf("%s mio read fail\n", __func__
);
378 div
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
380 pll
= zynqmp_clk_get_ddr_pll(clk_ctrl
);
381 pllrate
= zynqmp_clk_get_pll_rate(priv
, pll
);
382 if (IS_ERR_VALUE(pllrate
))
385 return DIV_ROUND_CLOSEST(pllrate
, div
);
388 static ulong
zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv
*priv
,
389 enum zynqmp_clk id
, bool two_divs
)
397 ret
= zynqmp_mmio_read(zynqmp_clk_get_register(id
), &clk_ctrl
);
399 printf("%s mio read fail\n", __func__
);
403 div0
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
408 div1
= (clk_ctrl
& CLK_CTRL_DIV1_MASK
) >> CLK_CTRL_DIV1_SHIFT
;
413 pll
= zynqmp_clk_get_peripheral_pll(clk_ctrl
);
414 pllrate
= zynqmp_clk_get_pll_rate(priv
, pll
);
415 if (IS_ERR_VALUE(pllrate
))
420 DIV_ROUND_CLOSEST(pllrate
, div0
), div1
);
423 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate
,
425 u32
*div0
, u32
*div1
)
427 long new_err
, best_err
= (long)(~0UL >> 1);
428 ulong new_rate
, best_rate
= 0;
431 for (d0
= 1; d0
<= ZYNQ_CLK_MAXDIV
; d0
++) {
432 for (d1
= 1; d1
<= ZYNQ_CLK_MAXDIV
>> 1; d1
++) {
433 new_rate
= DIV_ROUND_CLOSEST(
434 DIV_ROUND_CLOSEST(pll_rate
, d0
), d1
);
435 new_err
= abs(new_rate
- rate
);
437 if (new_err
< best_err
) {
441 best_rate
= new_rate
;
449 static ulong
zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv
*priv
,
450 enum zynqmp_clk id
, ulong rate
,
454 u32 clk_ctrl
, div0
= 0, div1
= 0;
455 ulong pll_rate
, new_rate
;
460 reg
= zynqmp_clk_get_register(id
);
461 ret
= zynqmp_mmio_read(reg
, &clk_ctrl
);
463 printf("%s mio read fail\n", __func__
);
467 pll
= zynqmp_clk_get_peripheral_pll(clk_ctrl
);
468 pll_rate
= zynqmp_clk_get_pll_rate(priv
, pll
);
469 if (IS_ERR_VALUE(pll_rate
))
472 clk_ctrl
&= ~CLK_CTRL_DIV0_MASK
;
474 clk_ctrl
&= ~CLK_CTRL_DIV1_MASK
;
475 new_rate
= zynqmp_clk_calc_peripheral_two_divs(rate
, pll_rate
,
477 clk_ctrl
|= div1
<< CLK_CTRL_DIV1_SHIFT
;
479 div0
= DIV_ROUND_CLOSEST(pll_rate
, rate
);
480 if (div0
> ZYNQ_CLK_MAXDIV
)
481 div0
= ZYNQ_CLK_MAXDIV
;
482 new_rate
= DIV_ROUND_CLOSEST(rate
, div0
);
484 clk_ctrl
|= div0
<< CLK_CTRL_DIV0_SHIFT
;
486 mask
= (ZYNQ_CLK_MAXDIV
<< CLK_CTRL_DIV0_SHIFT
) |
487 (ZYNQ_CLK_MAXDIV
<< CLK_CTRL_DIV1_SHIFT
);
489 ret
= zynqmp_mmio_write(reg
, mask
, clk_ctrl
);
491 printf("%s mio write fail\n", __func__
);
498 static ulong
zynqmp_clk_get_rate(struct clk
*clk
)
500 struct zynqmp_clk_priv
*priv
= dev_get_priv(clk
->dev
);
501 enum zynqmp_clk id
= clk
->id
;
502 bool two_divs
= false;
506 return zynqmp_clk_get_pll_rate(priv
, id
);
508 return zynqmp_clk_get_cpu_rate(priv
, id
);
510 return zynqmp_clk_get_ddr_rate(priv
);
511 case gem0_ref
... gem3_ref
:
512 case qspi_ref
... can1_ref
:
514 return zynqmp_clk_get_peripheral_rate(priv
, id
, two_divs
);
520 static ulong
zynqmp_clk_set_rate(struct clk
*clk
, ulong rate
)
522 struct zynqmp_clk_priv
*priv
= dev_get_priv(clk
->dev
);
523 enum zynqmp_clk id
= clk
->id
;
524 bool two_divs
= true;
527 case gem0_ref
... gem3_ref
:
528 case qspi_ref
... can1_ref
:
529 return zynqmp_clk_set_peripheral_rate(priv
, id
,
536 int soc_clk_dump(void)
541 ret
= uclass_get_device_by_driver(UCLASS_CLK
,
542 DM_GET_DRIVER(zynqmp_clk
), &dev
);
546 printf("clk\t\tfrequency\n");
547 for (i
= 0; i
< clk_max
; i
++) {
548 const char *name
= clk_names
[i
];
554 ret
= clk_request(dev
, &clk
);
558 rate
= clk_get_rate(&clk
);
562 if ((rate
== (unsigned long)-ENOSYS
) ||
563 (rate
== (unsigned long)-ENXIO
) ||
564 (rate
== (unsigned long)-EIO
))
565 printf("%10s%20s\n", name
, "unknown");
567 printf("%10s%20lu\n", name
, rate
);
574 static int zynqmp_get_freq_by_name(char *name
, struct udevice
*dev
, ulong
*freq
)
579 ret
= clk_get_by_name(dev
, name
, &clk
);
581 dev_err(dev
, "failed to get %s\n", name
);
585 *freq
= clk_get_rate(&clk
);
586 if (IS_ERR_VALUE(*freq
)) {
587 dev_err(dev
, "failed to get rate %s\n", name
);
593 static int zynqmp_clk_probe(struct udevice
*dev
)
596 struct zynqmp_clk_priv
*priv
= dev_get_priv(dev
);
598 debug("%s\n", __func__
);
599 ret
= zynqmp_get_freq_by_name("pss_ref_clk", dev
, &priv
->ps_clk_freq
);
603 ret
= zynqmp_get_freq_by_name("video_clk", dev
, &priv
->video_clk
);
607 ret
= zynqmp_get_freq_by_name("pss_alt_ref_clk", dev
,
608 &priv
->pss_alt_ref_clk
);
612 ret
= zynqmp_get_freq_by_name("aux_ref_clk", dev
, &priv
->aux_ref_clk
);
616 ret
= zynqmp_get_freq_by_name("gt_crx_ref_clk", dev
,
617 &priv
->gt_crx_ref_clk
);
624 static struct clk_ops zynqmp_clk_ops
= {
625 .set_rate
= zynqmp_clk_set_rate
,
626 .get_rate
= zynqmp_clk_get_rate
,
629 static const struct udevice_id zynqmp_clk_ids
[] = {
630 { .compatible
= "xlnx,zynqmp-clkc" },
634 U_BOOT_DRIVER(zynqmp_clk
) = {
635 .name
= "zynqmp-clk",
637 .of_match
= zynqmp_clk_ids
,
638 .probe
= zynqmp_clk_probe
,
639 .ops
= &zynqmp_clk_ops
,
640 .priv_auto_alloc_size
= sizeof(struct zynqmp_clk_priv
),