1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
18 #include "clk-input.h"
21 #include "clk-regmap.h"
22 #include "vid-pll-div.h"
23 #include "meson-eeclk.h"
26 static DEFINE_SPINLOCK(meson_clk_lock
);
28 static struct clk_regmap g12a_fixed_pll_dco
= {
29 .data
= &(struct meson_clk_pll_data
){
31 .reg_off
= HHI_FIX_PLL_CNTL0
,
36 .reg_off
= HHI_FIX_PLL_CNTL0
,
41 .reg_off
= HHI_FIX_PLL_CNTL0
,
46 .reg_off
= HHI_FIX_PLL_CNTL1
,
51 .reg_off
= HHI_FIX_PLL_CNTL0
,
56 .reg_off
= HHI_FIX_PLL_CNTL0
,
61 .hw
.init
= &(struct clk_init_data
){
62 .name
= "fixed_pll_dco",
63 .ops
= &meson_clk_pll_ro_ops
,
64 .parent_names
= (const char *[]){ IN_PREFIX
"xtal" },
69 static struct clk_regmap g12a_fixed_pll
= {
70 .data
= &(struct clk_regmap_div_data
){
71 .offset
= HHI_FIX_PLL_CNTL0
,
74 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
76 .hw
.init
= &(struct clk_init_data
){
78 .ops
= &clk_regmap_divider_ro_ops
,
79 .parent_names
= (const char *[]){ "fixed_pll_dco" },
82 * This clock won't ever change at runtime so
83 * CLK_SET_RATE_PARENT is not required
89 * Internal sys pll emulation configuration parameters
91 static const struct reg_sequence g12a_sys_init_regs
[] = {
92 { .reg
= HHI_SYS_PLL_CNTL1
, .def
= 0x00000000 },
93 { .reg
= HHI_SYS_PLL_CNTL2
, .def
= 0x00000000 },
94 { .reg
= HHI_SYS_PLL_CNTL3
, .def
= 0x48681c00 },
95 { .reg
= HHI_SYS_PLL_CNTL4
, .def
= 0x88770290 },
96 { .reg
= HHI_SYS_PLL_CNTL5
, .def
= 0x39272000 },
97 { .reg
= HHI_SYS_PLL_CNTL6
, .def
= 0x56540000 },
100 static struct clk_regmap g12a_sys_pll_dco
= {
101 .data
= &(struct meson_clk_pll_data
){
103 .reg_off
= HHI_SYS_PLL_CNTL0
,
108 .reg_off
= HHI_SYS_PLL_CNTL0
,
113 .reg_off
= HHI_SYS_PLL_CNTL0
,
118 .reg_off
= HHI_SYS_PLL_CNTL0
,
123 .reg_off
= HHI_SYS_PLL_CNTL0
,
127 .init_regs
= g12a_sys_init_regs
,
128 .init_count
= ARRAY_SIZE(g12a_sys_init_regs
),
130 .hw
.init
= &(struct clk_init_data
){
131 .name
= "sys_pll_dco",
132 .ops
= &meson_clk_pll_ro_ops
,
133 .parent_names
= (const char *[]){ IN_PREFIX
"xtal" },
138 static struct clk_regmap g12a_sys_pll
= {
139 .data
= &(struct clk_regmap_div_data
){
140 .offset
= HHI_SYS_PLL_CNTL0
,
143 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
145 .hw
.init
= &(struct clk_init_data
){
147 .ops
= &clk_regmap_divider_ro_ops
,
148 .parent_names
= (const char *[]){ "sys_pll_dco" },
153 static const struct pll_mult_range g12a_gp0_pll_mult_range
= {
159 * Internal gp0 pll emulation configuration parameters
161 static const struct reg_sequence g12a_gp0_init_regs
[] = {
162 { .reg
= HHI_GP0_PLL_CNTL1
, .def
= 0x00000000 },
163 { .reg
= HHI_GP0_PLL_CNTL2
, .def
= 0x00000000 },
164 { .reg
= HHI_GP0_PLL_CNTL3
, .def
= 0x48681c00 },
165 { .reg
= HHI_GP0_PLL_CNTL4
, .def
= 0x33771290 },
166 { .reg
= HHI_GP0_PLL_CNTL5
, .def
= 0x39272000 },
167 { .reg
= HHI_GP0_PLL_CNTL6
, .def
= 0x56540000 },
170 static struct clk_regmap g12a_gp0_pll_dco
= {
171 .data
= &(struct meson_clk_pll_data
){
173 .reg_off
= HHI_GP0_PLL_CNTL0
,
178 .reg_off
= HHI_GP0_PLL_CNTL0
,
183 .reg_off
= HHI_GP0_PLL_CNTL0
,
188 .reg_off
= HHI_GP0_PLL_CNTL1
,
193 .reg_off
= HHI_GP0_PLL_CNTL0
,
198 .reg_off
= HHI_GP0_PLL_CNTL0
,
202 .range
= &g12a_gp0_pll_mult_range
,
203 .init_regs
= g12a_gp0_init_regs
,
204 .init_count
= ARRAY_SIZE(g12a_gp0_init_regs
),
206 .hw
.init
= &(struct clk_init_data
){
207 .name
= "gp0_pll_dco",
208 .ops
= &meson_clk_pll_ops
,
209 .parent_names
= (const char *[]){ IN_PREFIX
"xtal" },
214 static struct clk_regmap g12a_gp0_pll
= {
215 .data
= &(struct clk_regmap_div_data
){
216 .offset
= HHI_GP0_PLL_CNTL0
,
219 .flags
= (CLK_DIVIDER_POWER_OF_TWO
|
220 CLK_DIVIDER_ROUND_CLOSEST
),
222 .hw
.init
= &(struct clk_init_data
){
224 .ops
= &clk_regmap_divider_ops
,
225 .parent_names
= (const char *[]){ "gp0_pll_dco" },
227 .flags
= CLK_SET_RATE_PARENT
,
232 * Internal hifi pll emulation configuration parameters
234 static const struct reg_sequence g12a_hifi_init_regs
[] = {
235 { .reg
= HHI_HIFI_PLL_CNTL1
, .def
= 0x00000000 },
236 { .reg
= HHI_HIFI_PLL_CNTL2
, .def
= 0x00000000 },
237 { .reg
= HHI_HIFI_PLL_CNTL3
, .def
= 0x6a285c00 },
238 { .reg
= HHI_HIFI_PLL_CNTL4
, .def
= 0x65771290 },
239 { .reg
= HHI_HIFI_PLL_CNTL5
, .def
= 0x39272000 },
240 { .reg
= HHI_HIFI_PLL_CNTL6
, .def
= 0x56540000 },
243 static struct clk_regmap g12a_hifi_pll_dco
= {
244 .data
= &(struct meson_clk_pll_data
){
246 .reg_off
= HHI_HIFI_PLL_CNTL0
,
251 .reg_off
= HHI_HIFI_PLL_CNTL0
,
256 .reg_off
= HHI_HIFI_PLL_CNTL0
,
261 .reg_off
= HHI_HIFI_PLL_CNTL1
,
266 .reg_off
= HHI_HIFI_PLL_CNTL0
,
271 .reg_off
= HHI_HIFI_PLL_CNTL0
,
275 .range
= &g12a_gp0_pll_mult_range
,
276 .init_regs
= g12a_hifi_init_regs
,
277 .init_count
= ARRAY_SIZE(g12a_hifi_init_regs
),
278 .flags
= CLK_MESON_PLL_ROUND_CLOSEST
,
280 .hw
.init
= &(struct clk_init_data
){
281 .name
= "hifi_pll_dco",
282 .ops
= &meson_clk_pll_ops
,
283 .parent_names
= (const char *[]){ IN_PREFIX
"xtal" },
288 static struct clk_regmap g12a_hifi_pll
= {
289 .data
= &(struct clk_regmap_div_data
){
290 .offset
= HHI_HIFI_PLL_CNTL0
,
293 .flags
= (CLK_DIVIDER_POWER_OF_TWO
|
294 CLK_DIVIDER_ROUND_CLOSEST
),
296 .hw
.init
= &(struct clk_init_data
){
298 .ops
= &clk_regmap_divider_ops
,
299 .parent_names
= (const char *[]){ "hifi_pll_dco" },
301 .flags
= CLK_SET_RATE_PARENT
,
305 static struct clk_regmap g12a_hdmi_pll_dco
= {
306 .data
= &(struct meson_clk_pll_data
){
308 .reg_off
= HHI_HDMI_PLL_CNTL0
,
313 .reg_off
= HHI_HDMI_PLL_CNTL0
,
318 .reg_off
= HHI_HDMI_PLL_CNTL0
,
323 .reg_off
= HHI_HDMI_PLL_CNTL1
,
328 .reg_off
= HHI_HDMI_PLL_CNTL0
,
333 .reg_off
= HHI_HDMI_PLL_CNTL0
,
338 .hw
.init
= &(struct clk_init_data
){
339 .name
= "hdmi_pll_dco",
340 .ops
= &meson_clk_pll_ro_ops
,
341 .parent_names
= (const char *[]){ IN_PREFIX
"xtal" },
344 * Display directly handle hdmi pll registers ATM, we need
345 * NOCACHE to keep our view of the clock as accurate as possible
347 .flags
= CLK_GET_RATE_NOCACHE
,
351 static struct clk_regmap g12a_hdmi_pll_od
= {
352 .data
= &(struct clk_regmap_div_data
){
353 .offset
= HHI_HDMI_PLL_CNTL0
,
356 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
358 .hw
.init
= &(struct clk_init_data
){
359 .name
= "hdmi_pll_od",
360 .ops
= &clk_regmap_divider_ro_ops
,
361 .parent_names
= (const char *[]){ "hdmi_pll_dco" },
363 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
367 static struct clk_regmap g12a_hdmi_pll_od2
= {
368 .data
= &(struct clk_regmap_div_data
){
369 .offset
= HHI_HDMI_PLL_CNTL0
,
372 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
374 .hw
.init
= &(struct clk_init_data
){
375 .name
= "hdmi_pll_od2",
376 .ops
= &clk_regmap_divider_ro_ops
,
377 .parent_names
= (const char *[]){ "hdmi_pll_od" },
379 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
383 static struct clk_regmap g12a_hdmi_pll
= {
384 .data
= &(struct clk_regmap_div_data
){
385 .offset
= HHI_HDMI_PLL_CNTL0
,
388 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
390 .hw
.init
= &(struct clk_init_data
){
392 .ops
= &clk_regmap_divider_ro_ops
,
393 .parent_names
= (const char *[]){ "hdmi_pll_od2" },
395 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
399 static struct clk_fixed_factor g12a_fclk_div2_div
= {
402 .hw
.init
= &(struct clk_init_data
){
403 .name
= "fclk_div2_div",
404 .ops
= &clk_fixed_factor_ops
,
405 .parent_names
= (const char *[]){ "fixed_pll" },
410 static struct clk_regmap g12a_fclk_div2
= {
411 .data
= &(struct clk_regmap_gate_data
){
412 .offset
= HHI_FIX_PLL_CNTL1
,
415 .hw
.init
= &(struct clk_init_data
){
417 .ops
= &clk_regmap_gate_ops
,
418 .parent_names
= (const char *[]){ "fclk_div2_div" },
423 static struct clk_fixed_factor g12a_fclk_div3_div
= {
426 .hw
.init
= &(struct clk_init_data
){
427 .name
= "fclk_div3_div",
428 .ops
= &clk_fixed_factor_ops
,
429 .parent_names
= (const char *[]){ "fixed_pll" },
434 static struct clk_regmap g12a_fclk_div3
= {
435 .data
= &(struct clk_regmap_gate_data
){
436 .offset
= HHI_FIX_PLL_CNTL1
,
439 .hw
.init
= &(struct clk_init_data
){
441 .ops
= &clk_regmap_gate_ops
,
442 .parent_names
= (const char *[]){ "fclk_div3_div" },
447 static struct clk_fixed_factor g12a_fclk_div4_div
= {
450 .hw
.init
= &(struct clk_init_data
){
451 .name
= "fclk_div4_div",
452 .ops
= &clk_fixed_factor_ops
,
453 .parent_names
= (const char *[]){ "fixed_pll" },
458 static struct clk_regmap g12a_fclk_div4
= {
459 .data
= &(struct clk_regmap_gate_data
){
460 .offset
= HHI_FIX_PLL_CNTL1
,
463 .hw
.init
= &(struct clk_init_data
){
465 .ops
= &clk_regmap_gate_ops
,
466 .parent_names
= (const char *[]){ "fclk_div4_div" },
471 static struct clk_fixed_factor g12a_fclk_div5_div
= {
474 .hw
.init
= &(struct clk_init_data
){
475 .name
= "fclk_div5_div",
476 .ops
= &clk_fixed_factor_ops
,
477 .parent_names
= (const char *[]){ "fixed_pll" },
482 static struct clk_regmap g12a_fclk_div5
= {
483 .data
= &(struct clk_regmap_gate_data
){
484 .offset
= HHI_FIX_PLL_CNTL1
,
487 .hw
.init
= &(struct clk_init_data
){
489 .ops
= &clk_regmap_gate_ops
,
490 .parent_names
= (const char *[]){ "fclk_div5_div" },
495 static struct clk_fixed_factor g12a_fclk_div7_div
= {
498 .hw
.init
= &(struct clk_init_data
){
499 .name
= "fclk_div7_div",
500 .ops
= &clk_fixed_factor_ops
,
501 .parent_names
= (const char *[]){ "fixed_pll" },
506 static struct clk_regmap g12a_fclk_div7
= {
507 .data
= &(struct clk_regmap_gate_data
){
508 .offset
= HHI_FIX_PLL_CNTL1
,
511 .hw
.init
= &(struct clk_init_data
){
513 .ops
= &clk_regmap_gate_ops
,
514 .parent_names
= (const char *[]){ "fclk_div7_div" },
519 static struct clk_fixed_factor g12a_fclk_div2p5_div
= {
522 .hw
.init
= &(struct clk_init_data
){
523 .name
= "fclk_div2p5_div",
524 .ops
= &clk_fixed_factor_ops
,
525 .parent_names
= (const char *[]){ "fixed_pll_dco" },
530 static struct clk_regmap g12a_fclk_div2p5
= {
531 .data
= &(struct clk_regmap_gate_data
){
532 .offset
= HHI_FIX_PLL_CNTL1
,
535 .hw
.init
= &(struct clk_init_data
){
536 .name
= "fclk_div2p5",
537 .ops
= &clk_regmap_gate_ops
,
538 .parent_names
= (const char *[]){ "fclk_div2p5_div" },
543 static struct clk_fixed_factor g12a_mpll_50m_div
= {
546 .hw
.init
= &(struct clk_init_data
){
547 .name
= "mpll_50m_div",
548 .ops
= &clk_fixed_factor_ops
,
549 .parent_names
= (const char *[]){ "fixed_pll_dco" },
554 static struct clk_regmap g12a_mpll_50m
= {
555 .data
= &(struct clk_regmap_mux_data
){
556 .offset
= HHI_FIX_PLL_CNTL3
,
560 .hw
.init
= &(struct clk_init_data
){
562 .ops
= &clk_regmap_mux_ro_ops
,
563 .parent_names
= (const char *[]){ IN_PREFIX
"xtal",
569 static struct clk_fixed_factor g12a_mpll_prediv
= {
572 .hw
.init
= &(struct clk_init_data
){
573 .name
= "mpll_prediv",
574 .ops
= &clk_fixed_factor_ops
,
575 .parent_names
= (const char *[]){ "fixed_pll_dco" },
580 static struct clk_regmap g12a_mpll0_div
= {
581 .data
= &(struct meson_clk_mpll_data
){
583 .reg_off
= HHI_MPLL_CNTL1
,
588 .reg_off
= HHI_MPLL_CNTL1
,
593 .reg_off
= HHI_MPLL_CNTL1
,
598 .reg_off
= HHI_MPLL_CNTL1
,
602 .lock
= &meson_clk_lock
,
604 .hw
.init
= &(struct clk_init_data
){
606 .ops
= &meson_clk_mpll_ops
,
607 .parent_names
= (const char *[]){ "mpll_prediv" },
612 static struct clk_regmap g12a_mpll0
= {
613 .data
= &(struct clk_regmap_gate_data
){
614 .offset
= HHI_MPLL_CNTL1
,
617 .hw
.init
= &(struct clk_init_data
){
619 .ops
= &clk_regmap_gate_ops
,
620 .parent_names
= (const char *[]){ "mpll0_div" },
622 .flags
= CLK_SET_RATE_PARENT
,
626 static struct clk_regmap g12a_mpll1_div
= {
627 .data
= &(struct meson_clk_mpll_data
){
629 .reg_off
= HHI_MPLL_CNTL3
,
634 .reg_off
= HHI_MPLL_CNTL3
,
639 .reg_off
= HHI_MPLL_CNTL3
,
644 .reg_off
= HHI_MPLL_CNTL3
,
648 .lock
= &meson_clk_lock
,
650 .hw
.init
= &(struct clk_init_data
){
652 .ops
= &meson_clk_mpll_ops
,
653 .parent_names
= (const char *[]){ "mpll_prediv" },
658 static struct clk_regmap g12a_mpll1
= {
659 .data
= &(struct clk_regmap_gate_data
){
660 .offset
= HHI_MPLL_CNTL3
,
663 .hw
.init
= &(struct clk_init_data
){
665 .ops
= &clk_regmap_gate_ops
,
666 .parent_names
= (const char *[]){ "mpll1_div" },
668 .flags
= CLK_SET_RATE_PARENT
,
672 static struct clk_regmap g12a_mpll2_div
= {
673 .data
= &(struct meson_clk_mpll_data
){
675 .reg_off
= HHI_MPLL_CNTL5
,
680 .reg_off
= HHI_MPLL_CNTL5
,
685 .reg_off
= HHI_MPLL_CNTL5
,
690 .reg_off
= HHI_MPLL_CNTL5
,
694 .lock
= &meson_clk_lock
,
696 .hw
.init
= &(struct clk_init_data
){
698 .ops
= &meson_clk_mpll_ops
,
699 .parent_names
= (const char *[]){ "mpll_prediv" },
704 static struct clk_regmap g12a_mpll2
= {
705 .data
= &(struct clk_regmap_gate_data
){
706 .offset
= HHI_MPLL_CNTL5
,
709 .hw
.init
= &(struct clk_init_data
){
711 .ops
= &clk_regmap_gate_ops
,
712 .parent_names
= (const char *[]){ "mpll2_div" },
714 .flags
= CLK_SET_RATE_PARENT
,
718 static struct clk_regmap g12a_mpll3_div
= {
719 .data
= &(struct meson_clk_mpll_data
){
721 .reg_off
= HHI_MPLL_CNTL7
,
726 .reg_off
= HHI_MPLL_CNTL7
,
731 .reg_off
= HHI_MPLL_CNTL7
,
736 .reg_off
= HHI_MPLL_CNTL7
,
740 .lock
= &meson_clk_lock
,
742 .hw
.init
= &(struct clk_init_data
){
744 .ops
= &meson_clk_mpll_ops
,
745 .parent_names
= (const char *[]){ "mpll_prediv" },
750 static struct clk_regmap g12a_mpll3
= {
751 .data
= &(struct clk_regmap_gate_data
){
752 .offset
= HHI_MPLL_CNTL7
,
755 .hw
.init
= &(struct clk_init_data
){
757 .ops
= &clk_regmap_gate_ops
,
758 .parent_names
= (const char *[]){ "mpll3_div" },
760 .flags
= CLK_SET_RATE_PARENT
,
764 static u32 mux_table_clk81
[] = { 0, 2, 3, 4, 5, 6, 7 };
765 static const char * const clk81_parent_names
[] = {
766 IN_PREFIX
"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
767 "fclk_div3", "fclk_div5"
770 static struct clk_regmap g12a_mpeg_clk_sel
= {
771 .data
= &(struct clk_regmap_mux_data
){
772 .offset
= HHI_MPEG_CLK_CNTL
,
775 .table
= mux_table_clk81
,
777 .hw
.init
= &(struct clk_init_data
){
778 .name
= "mpeg_clk_sel",
779 .ops
= &clk_regmap_mux_ro_ops
,
780 .parent_names
= clk81_parent_names
,
781 .num_parents
= ARRAY_SIZE(clk81_parent_names
),
785 static struct clk_regmap g12a_mpeg_clk_div
= {
786 .data
= &(struct clk_regmap_div_data
){
787 .offset
= HHI_MPEG_CLK_CNTL
,
791 .hw
.init
= &(struct clk_init_data
){
792 .name
= "mpeg_clk_div",
793 .ops
= &clk_regmap_divider_ops
,
794 .parent_names
= (const char *[]){ "mpeg_clk_sel" },
796 .flags
= CLK_SET_RATE_PARENT
,
800 static struct clk_regmap g12a_clk81
= {
801 .data
= &(struct clk_regmap_gate_data
){
802 .offset
= HHI_MPEG_CLK_CNTL
,
805 .hw
.init
= &(struct clk_init_data
){
807 .ops
= &clk_regmap_gate_ops
,
808 .parent_names
= (const char *[]){ "mpeg_clk_div" },
810 .flags
= (CLK_SET_RATE_PARENT
| CLK_IS_CRITICAL
),
814 static const char * const g12a_sd_emmc_clk0_parent_names
[] = {
815 IN_PREFIX
"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
818 * Following these parent clocks, we should also have had mpll2, mpll3
819 * and gp0_pll but these clocks are too precious to be used here. All
820 * the necessary rates for MMC and NAND operation can be acheived using
821 * g12a_ee_core or fclk_div clocks
826 static struct clk_regmap g12a_sd_emmc_a_clk0_sel
= {
827 .data
= &(struct clk_regmap_mux_data
){
828 .offset
= HHI_SD_EMMC_CLK_CNTL
,
832 .hw
.init
= &(struct clk_init_data
) {
833 .name
= "sd_emmc_a_clk0_sel",
834 .ops
= &clk_regmap_mux_ops
,
835 .parent_names
= g12a_sd_emmc_clk0_parent_names
,
836 .num_parents
= ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names
),
837 .flags
= CLK_SET_RATE_PARENT
,
841 static struct clk_regmap g12a_sd_emmc_a_clk0_div
= {
842 .data
= &(struct clk_regmap_div_data
){
843 .offset
= HHI_SD_EMMC_CLK_CNTL
,
847 .hw
.init
= &(struct clk_init_data
) {
848 .name
= "sd_emmc_a_clk0_div",
849 .ops
= &clk_regmap_divider_ops
,
850 .parent_names
= (const char *[]){ "sd_emmc_a_clk0_sel" },
852 .flags
= CLK_SET_RATE_PARENT
,
856 static struct clk_regmap g12a_sd_emmc_a_clk0
= {
857 .data
= &(struct clk_regmap_gate_data
){
858 .offset
= HHI_SD_EMMC_CLK_CNTL
,
861 .hw
.init
= &(struct clk_init_data
){
862 .name
= "sd_emmc_a_clk0",
863 .ops
= &clk_regmap_gate_ops
,
864 .parent_names
= (const char *[]){ "sd_emmc_a_clk0_div" },
866 .flags
= CLK_SET_RATE_PARENT
,
871 static struct clk_regmap g12a_sd_emmc_b_clk0_sel
= {
872 .data
= &(struct clk_regmap_mux_data
){
873 .offset
= HHI_SD_EMMC_CLK_CNTL
,
877 .hw
.init
= &(struct clk_init_data
) {
878 .name
= "sd_emmc_b_clk0_sel",
879 .ops
= &clk_regmap_mux_ops
,
880 .parent_names
= g12a_sd_emmc_clk0_parent_names
,
881 .num_parents
= ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names
),
882 .flags
= CLK_SET_RATE_PARENT
,
886 static struct clk_regmap g12a_sd_emmc_b_clk0_div
= {
887 .data
= &(struct clk_regmap_div_data
){
888 .offset
= HHI_SD_EMMC_CLK_CNTL
,
892 .hw
.init
= &(struct clk_init_data
) {
893 .name
= "sd_emmc_b_clk0_div",
894 .ops
= &clk_regmap_divider_ops
,
895 .parent_names
= (const char *[]){ "sd_emmc_b_clk0_sel" },
897 .flags
= CLK_SET_RATE_PARENT
,
901 static struct clk_regmap g12a_sd_emmc_b_clk0
= {
902 .data
= &(struct clk_regmap_gate_data
){
903 .offset
= HHI_SD_EMMC_CLK_CNTL
,
906 .hw
.init
= &(struct clk_init_data
){
907 .name
= "sd_emmc_b_clk0",
908 .ops
= &clk_regmap_gate_ops
,
909 .parent_names
= (const char *[]){ "sd_emmc_b_clk0_div" },
911 .flags
= CLK_SET_RATE_PARENT
,
915 /* EMMC/NAND clock */
916 static struct clk_regmap g12a_sd_emmc_c_clk0_sel
= {
917 .data
= &(struct clk_regmap_mux_data
){
918 .offset
= HHI_NAND_CLK_CNTL
,
922 .hw
.init
= &(struct clk_init_data
) {
923 .name
= "sd_emmc_c_clk0_sel",
924 .ops
= &clk_regmap_mux_ops
,
925 .parent_names
= g12a_sd_emmc_clk0_parent_names
,
926 .num_parents
= ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names
),
927 .flags
= CLK_SET_RATE_PARENT
,
931 static struct clk_regmap g12a_sd_emmc_c_clk0_div
= {
932 .data
= &(struct clk_regmap_div_data
){
933 .offset
= HHI_NAND_CLK_CNTL
,
937 .hw
.init
= &(struct clk_init_data
) {
938 .name
= "sd_emmc_c_clk0_div",
939 .ops
= &clk_regmap_divider_ops
,
940 .parent_names
= (const char *[]){ "sd_emmc_c_clk0_sel" },
942 .flags
= CLK_SET_RATE_PARENT
,
946 static struct clk_regmap g12a_sd_emmc_c_clk0
= {
947 .data
= &(struct clk_regmap_gate_data
){
948 .offset
= HHI_NAND_CLK_CNTL
,
951 .hw
.init
= &(struct clk_init_data
){
952 .name
= "sd_emmc_c_clk0",
953 .ops
= &clk_regmap_gate_ops
,
954 .parent_names
= (const char *[]){ "sd_emmc_c_clk0_div" },
956 .flags
= CLK_SET_RATE_PARENT
,
962 static const char * const g12a_vpu_parent_names
[] = {
963 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
964 "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
967 static struct clk_regmap g12a_vpu_0_sel
= {
968 .data
= &(struct clk_regmap_mux_data
){
969 .offset
= HHI_VPU_CLK_CNTL
,
973 .hw
.init
= &(struct clk_init_data
){
975 .ops
= &clk_regmap_mux_ops
,
976 .parent_names
= g12a_vpu_parent_names
,
977 .num_parents
= ARRAY_SIZE(g12a_vpu_parent_names
),
978 .flags
= CLK_SET_RATE_NO_REPARENT
,
982 static struct clk_regmap g12a_vpu_0_div
= {
983 .data
= &(struct clk_regmap_div_data
){
984 .offset
= HHI_VPU_CLK_CNTL
,
988 .hw
.init
= &(struct clk_init_data
){
990 .ops
= &clk_regmap_divider_ops
,
991 .parent_names
= (const char *[]){ "vpu_0_sel" },
993 .flags
= CLK_SET_RATE_PARENT
,
997 static struct clk_regmap g12a_vpu_0
= {
998 .data
= &(struct clk_regmap_gate_data
){
999 .offset
= HHI_VPU_CLK_CNTL
,
1002 .hw
.init
= &(struct clk_init_data
) {
1004 .ops
= &clk_regmap_gate_ops
,
1005 .parent_names
= (const char *[]){ "vpu_0_div" },
1007 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1011 static struct clk_regmap g12a_vpu_1_sel
= {
1012 .data
= &(struct clk_regmap_mux_data
){
1013 .offset
= HHI_VPU_CLK_CNTL
,
1017 .hw
.init
= &(struct clk_init_data
){
1018 .name
= "vpu_1_sel",
1019 .ops
= &clk_regmap_mux_ops
,
1020 .parent_names
= g12a_vpu_parent_names
,
1021 .num_parents
= ARRAY_SIZE(g12a_vpu_parent_names
),
1022 .flags
= CLK_SET_RATE_NO_REPARENT
,
1026 static struct clk_regmap g12a_vpu_1_div
= {
1027 .data
= &(struct clk_regmap_div_data
){
1028 .offset
= HHI_VPU_CLK_CNTL
,
1032 .hw
.init
= &(struct clk_init_data
){
1033 .name
= "vpu_1_div",
1034 .ops
= &clk_regmap_divider_ops
,
1035 .parent_names
= (const char *[]){ "vpu_1_sel" },
1037 .flags
= CLK_SET_RATE_PARENT
,
1041 static struct clk_regmap g12a_vpu_1
= {
1042 .data
= &(struct clk_regmap_gate_data
){
1043 .offset
= HHI_VPU_CLK_CNTL
,
1046 .hw
.init
= &(struct clk_init_data
) {
1048 .ops
= &clk_regmap_gate_ops
,
1049 .parent_names
= (const char *[]){ "vpu_1_div" },
1051 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1055 static struct clk_regmap g12a_vpu
= {
1056 .data
= &(struct clk_regmap_mux_data
){
1057 .offset
= HHI_VPU_CLK_CNTL
,
1061 .hw
.init
= &(struct clk_init_data
){
1063 .ops
= &clk_regmap_mux_ops
,
1065 * bit 31 selects from 2 possible parents:
1068 .parent_names
= (const char *[]){ "vpu_0", "vpu_1" },
1070 .flags
= CLK_SET_RATE_NO_REPARENT
,
1076 static const char * const g12a_vapb_parent_names
[] = {
1077 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
1078 "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
1081 static struct clk_regmap g12a_vapb_0_sel
= {
1082 .data
= &(struct clk_regmap_mux_data
){
1083 .offset
= HHI_VAPBCLK_CNTL
,
1087 .hw
.init
= &(struct clk_init_data
){
1088 .name
= "vapb_0_sel",
1089 .ops
= &clk_regmap_mux_ops
,
1090 .parent_names
= g12a_vapb_parent_names
,
1091 .num_parents
= ARRAY_SIZE(g12a_vapb_parent_names
),
1092 .flags
= CLK_SET_RATE_NO_REPARENT
,
1096 static struct clk_regmap g12a_vapb_0_div
= {
1097 .data
= &(struct clk_regmap_div_data
){
1098 .offset
= HHI_VAPBCLK_CNTL
,
1102 .hw
.init
= &(struct clk_init_data
){
1103 .name
= "vapb_0_div",
1104 .ops
= &clk_regmap_divider_ops
,
1105 .parent_names
= (const char *[]){ "vapb_0_sel" },
1107 .flags
= CLK_SET_RATE_PARENT
,
1111 static struct clk_regmap g12a_vapb_0
= {
1112 .data
= &(struct clk_regmap_gate_data
){
1113 .offset
= HHI_VAPBCLK_CNTL
,
1116 .hw
.init
= &(struct clk_init_data
) {
1118 .ops
= &clk_regmap_gate_ops
,
1119 .parent_names
= (const char *[]){ "vapb_0_div" },
1121 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1125 static struct clk_regmap g12a_vapb_1_sel
= {
1126 .data
= &(struct clk_regmap_mux_data
){
1127 .offset
= HHI_VAPBCLK_CNTL
,
1131 .hw
.init
= &(struct clk_init_data
){
1132 .name
= "vapb_1_sel",
1133 .ops
= &clk_regmap_mux_ops
,
1134 .parent_names
= g12a_vapb_parent_names
,
1135 .num_parents
= ARRAY_SIZE(g12a_vapb_parent_names
),
1136 .flags
= CLK_SET_RATE_NO_REPARENT
,
1140 static struct clk_regmap g12a_vapb_1_div
= {
1141 .data
= &(struct clk_regmap_div_data
){
1142 .offset
= HHI_VAPBCLK_CNTL
,
1146 .hw
.init
= &(struct clk_init_data
){
1147 .name
= "vapb_1_div",
1148 .ops
= &clk_regmap_divider_ops
,
1149 .parent_names
= (const char *[]){ "vapb_1_sel" },
1151 .flags
= CLK_SET_RATE_PARENT
,
1155 static struct clk_regmap g12a_vapb_1
= {
1156 .data
= &(struct clk_regmap_gate_data
){
1157 .offset
= HHI_VAPBCLK_CNTL
,
1160 .hw
.init
= &(struct clk_init_data
) {
1162 .ops
= &clk_regmap_gate_ops
,
1163 .parent_names
= (const char *[]){ "vapb_1_div" },
1165 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1169 static struct clk_regmap g12a_vapb_sel
= {
1170 .data
= &(struct clk_regmap_mux_data
){
1171 .offset
= HHI_VAPBCLK_CNTL
,
1175 .hw
.init
= &(struct clk_init_data
){
1177 .ops
= &clk_regmap_mux_ops
,
1179 * bit 31 selects from 2 possible parents:
1182 .parent_names
= (const char *[]){ "vapb_0", "vapb_1" },
1184 .flags
= CLK_SET_RATE_NO_REPARENT
,
1188 static struct clk_regmap g12a_vapb
= {
1189 .data
= &(struct clk_regmap_gate_data
){
1190 .offset
= HHI_VAPBCLK_CNTL
,
1193 .hw
.init
= &(struct clk_init_data
) {
1195 .ops
= &clk_regmap_gate_ops
,
1196 .parent_names
= (const char *[]){ "vapb_sel" },
1198 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1204 static struct clk_regmap g12a_vid_pll_div
= {
1205 .data
= &(struct meson_vid_pll_div_data
){
1207 .reg_off
= HHI_VID_PLL_CLK_DIV
,
1212 .reg_off
= HHI_VID_PLL_CLK_DIV
,
1217 .hw
.init
= &(struct clk_init_data
) {
1218 .name
= "vid_pll_div",
1219 .ops
= &meson_vid_pll_div_ro_ops
,
1220 .parent_names
= (const char *[]){ "hdmi_pll" },
1222 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
1226 static const char * const g12a_vid_pll_parent_names
[] = { "vid_pll_div",
1229 static struct clk_regmap g12a_vid_pll_sel
= {
1230 .data
= &(struct clk_regmap_mux_data
){
1231 .offset
= HHI_VID_PLL_CLK_DIV
,
1235 .hw
.init
= &(struct clk_init_data
){
1236 .name
= "vid_pll_sel",
1237 .ops
= &clk_regmap_mux_ops
,
1239 * bit 18 selects from 2 possible parents:
1240 * vid_pll_div or hdmi_pll
1242 .parent_names
= g12a_vid_pll_parent_names
,
1243 .num_parents
= ARRAY_SIZE(g12a_vid_pll_parent_names
),
1244 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1248 static struct clk_regmap g12a_vid_pll
= {
1249 .data
= &(struct clk_regmap_gate_data
){
1250 .offset
= HHI_VID_PLL_CLK_DIV
,
1253 .hw
.init
= &(struct clk_init_data
) {
1255 .ops
= &clk_regmap_gate_ops
,
1256 .parent_names
= (const char *[]){ "vid_pll_sel" },
1258 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1262 static const char * const g12a_vclk_parent_names
[] = {
1263 "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
1264 "fclk_div5", "fclk_div7"
1267 static struct clk_regmap g12a_vclk_sel
= {
1268 .data
= &(struct clk_regmap_mux_data
){
1269 .offset
= HHI_VID_CLK_CNTL
,
1273 .hw
.init
= &(struct clk_init_data
){
1275 .ops
= &clk_regmap_mux_ops
,
1276 .parent_names
= g12a_vclk_parent_names
,
1277 .num_parents
= ARRAY_SIZE(g12a_vclk_parent_names
),
1278 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1282 static struct clk_regmap g12a_vclk2_sel
= {
1283 .data
= &(struct clk_regmap_mux_data
){
1284 .offset
= HHI_VIID_CLK_CNTL
,
1288 .hw
.init
= &(struct clk_init_data
){
1289 .name
= "vclk2_sel",
1290 .ops
= &clk_regmap_mux_ops
,
1291 .parent_names
= g12a_vclk_parent_names
,
1292 .num_parents
= ARRAY_SIZE(g12a_vclk_parent_names
),
1293 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1297 static struct clk_regmap g12a_vclk_input
= {
1298 .data
= &(struct clk_regmap_gate_data
){
1299 .offset
= HHI_VID_CLK_DIV
,
1302 .hw
.init
= &(struct clk_init_data
) {
1303 .name
= "vclk_input",
1304 .ops
= &clk_regmap_gate_ops
,
1305 .parent_names
= (const char *[]){ "vclk_sel" },
1307 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1311 static struct clk_regmap g12a_vclk2_input
= {
1312 .data
= &(struct clk_regmap_gate_data
){
1313 .offset
= HHI_VIID_CLK_DIV
,
1316 .hw
.init
= &(struct clk_init_data
) {
1317 .name
= "vclk2_input",
1318 .ops
= &clk_regmap_gate_ops
,
1319 .parent_names
= (const char *[]){ "vclk2_sel" },
1321 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1325 static struct clk_regmap g12a_vclk_div
= {
1326 .data
= &(struct clk_regmap_div_data
){
1327 .offset
= HHI_VID_CLK_DIV
,
1331 .hw
.init
= &(struct clk_init_data
){
1333 .ops
= &clk_regmap_divider_ops
,
1334 .parent_names
= (const char *[]){ "vclk_input" },
1336 .flags
= CLK_GET_RATE_NOCACHE
,
1340 static struct clk_regmap g12a_vclk2_div
= {
1341 .data
= &(struct clk_regmap_div_data
){
1342 .offset
= HHI_VIID_CLK_DIV
,
1346 .hw
.init
= &(struct clk_init_data
){
1347 .name
= "vclk2_div",
1348 .ops
= &clk_regmap_divider_ops
,
1349 .parent_names
= (const char *[]){ "vclk2_input" },
1351 .flags
= CLK_GET_RATE_NOCACHE
,
1355 static struct clk_regmap g12a_vclk
= {
1356 .data
= &(struct clk_regmap_gate_data
){
1357 .offset
= HHI_VID_CLK_CNTL
,
1360 .hw
.init
= &(struct clk_init_data
) {
1362 .ops
= &clk_regmap_gate_ops
,
1363 .parent_names
= (const char *[]){ "vclk_div" },
1365 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1369 static struct clk_regmap g12a_vclk2
= {
1370 .data
= &(struct clk_regmap_gate_data
){
1371 .offset
= HHI_VIID_CLK_CNTL
,
1374 .hw
.init
= &(struct clk_init_data
) {
1376 .ops
= &clk_regmap_gate_ops
,
1377 .parent_names
= (const char *[]){ "vclk2_div" },
1379 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1383 static struct clk_regmap g12a_vclk_div1
= {
1384 .data
= &(struct clk_regmap_gate_data
){
1385 .offset
= HHI_VID_CLK_CNTL
,
1388 .hw
.init
= &(struct clk_init_data
) {
1389 .name
= "vclk_div1",
1390 .ops
= &clk_regmap_gate_ops
,
1391 .parent_names
= (const char *[]){ "vclk" },
1393 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1397 static struct clk_regmap g12a_vclk_div2_en
= {
1398 .data
= &(struct clk_regmap_gate_data
){
1399 .offset
= HHI_VID_CLK_CNTL
,
1402 .hw
.init
= &(struct clk_init_data
) {
1403 .name
= "vclk_div2_en",
1404 .ops
= &clk_regmap_gate_ops
,
1405 .parent_names
= (const char *[]){ "vclk" },
1407 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1411 static struct clk_regmap g12a_vclk_div4_en
= {
1412 .data
= &(struct clk_regmap_gate_data
){
1413 .offset
= HHI_VID_CLK_CNTL
,
1416 .hw
.init
= &(struct clk_init_data
) {
1417 .name
= "vclk_div4_en",
1418 .ops
= &clk_regmap_gate_ops
,
1419 .parent_names
= (const char *[]){ "vclk" },
1421 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1425 static struct clk_regmap g12a_vclk_div6_en
= {
1426 .data
= &(struct clk_regmap_gate_data
){
1427 .offset
= HHI_VID_CLK_CNTL
,
1430 .hw
.init
= &(struct clk_init_data
) {
1431 .name
= "vclk_div6_en",
1432 .ops
= &clk_regmap_gate_ops
,
1433 .parent_names
= (const char *[]){ "vclk" },
1435 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1439 static struct clk_regmap g12a_vclk_div12_en
= {
1440 .data
= &(struct clk_regmap_gate_data
){
1441 .offset
= HHI_VID_CLK_CNTL
,
1444 .hw
.init
= &(struct clk_init_data
) {
1445 .name
= "vclk_div12_en",
1446 .ops
= &clk_regmap_gate_ops
,
1447 .parent_names
= (const char *[]){ "vclk" },
1449 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1453 static struct clk_regmap g12a_vclk2_div1
= {
1454 .data
= &(struct clk_regmap_gate_data
){
1455 .offset
= HHI_VIID_CLK_CNTL
,
1458 .hw
.init
= &(struct clk_init_data
) {
1459 .name
= "vclk2_div1",
1460 .ops
= &clk_regmap_gate_ops
,
1461 .parent_names
= (const char *[]){ "vclk2" },
1463 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1467 static struct clk_regmap g12a_vclk2_div2_en
= {
1468 .data
= &(struct clk_regmap_gate_data
){
1469 .offset
= HHI_VIID_CLK_CNTL
,
1472 .hw
.init
= &(struct clk_init_data
) {
1473 .name
= "vclk2_div2_en",
1474 .ops
= &clk_regmap_gate_ops
,
1475 .parent_names
= (const char *[]){ "vclk2" },
1477 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1481 static struct clk_regmap g12a_vclk2_div4_en
= {
1482 .data
= &(struct clk_regmap_gate_data
){
1483 .offset
= HHI_VIID_CLK_CNTL
,
1486 .hw
.init
= &(struct clk_init_data
) {
1487 .name
= "vclk2_div4_en",
1488 .ops
= &clk_regmap_gate_ops
,
1489 .parent_names
= (const char *[]){ "vclk2" },
1491 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1495 static struct clk_regmap g12a_vclk2_div6_en
= {
1496 .data
= &(struct clk_regmap_gate_data
){
1497 .offset
= HHI_VIID_CLK_CNTL
,
1500 .hw
.init
= &(struct clk_init_data
) {
1501 .name
= "vclk2_div6_en",
1502 .ops
= &clk_regmap_gate_ops
,
1503 .parent_names
= (const char *[]){ "vclk2" },
1505 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1509 static struct clk_regmap g12a_vclk2_div12_en
= {
1510 .data
= &(struct clk_regmap_gate_data
){
1511 .offset
= HHI_VIID_CLK_CNTL
,
1514 .hw
.init
= &(struct clk_init_data
) {
1515 .name
= "vclk2_div12_en",
1516 .ops
= &clk_regmap_gate_ops
,
1517 .parent_names
= (const char *[]){ "vclk2" },
1519 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1523 static struct clk_fixed_factor g12a_vclk_div2
= {
1526 .hw
.init
= &(struct clk_init_data
){
1527 .name
= "vclk_div2",
1528 .ops
= &clk_fixed_factor_ops
,
1529 .parent_names
= (const char *[]){ "vclk_div2_en" },
1534 static struct clk_fixed_factor g12a_vclk_div4
= {
1537 .hw
.init
= &(struct clk_init_data
){
1538 .name
= "vclk_div4",
1539 .ops
= &clk_fixed_factor_ops
,
1540 .parent_names
= (const char *[]){ "vclk_div4_en" },
1545 static struct clk_fixed_factor g12a_vclk_div6
= {
1548 .hw
.init
= &(struct clk_init_data
){
1549 .name
= "vclk_div6",
1550 .ops
= &clk_fixed_factor_ops
,
1551 .parent_names
= (const char *[]){ "vclk_div6_en" },
1556 static struct clk_fixed_factor g12a_vclk_div12
= {
1559 .hw
.init
= &(struct clk_init_data
){
1560 .name
= "vclk_div12",
1561 .ops
= &clk_fixed_factor_ops
,
1562 .parent_names
= (const char *[]){ "vclk_div12_en" },
1567 static struct clk_fixed_factor g12a_vclk2_div2
= {
1570 .hw
.init
= &(struct clk_init_data
){
1571 .name
= "vclk2_div2",
1572 .ops
= &clk_fixed_factor_ops
,
1573 .parent_names
= (const char *[]){ "vclk2_div2_en" },
1578 static struct clk_fixed_factor g12a_vclk2_div4
= {
1581 .hw
.init
= &(struct clk_init_data
){
1582 .name
= "vclk2_div4",
1583 .ops
= &clk_fixed_factor_ops
,
1584 .parent_names
= (const char *[]){ "vclk2_div4_en" },
1589 static struct clk_fixed_factor g12a_vclk2_div6
= {
1592 .hw
.init
= &(struct clk_init_data
){
1593 .name
= "vclk2_div6",
1594 .ops
= &clk_fixed_factor_ops
,
1595 .parent_names
= (const char *[]){ "vclk2_div6_en" },
1600 static struct clk_fixed_factor g12a_vclk2_div12
= {
1603 .hw
.init
= &(struct clk_init_data
){
1604 .name
= "vclk2_div12",
1605 .ops
= &clk_fixed_factor_ops
,
1606 .parent_names
= (const char *[]){ "vclk2_div12_en" },
1611 static u32 mux_table_cts_sel
[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1612 static const char * const g12a_cts_parent_names
[] = {
1613 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
1614 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
1615 "vclk2_div6", "vclk2_div12"
1618 static struct clk_regmap g12a_cts_enci_sel
= {
1619 .data
= &(struct clk_regmap_mux_data
){
1620 .offset
= HHI_VID_CLK_DIV
,
1623 .table
= mux_table_cts_sel
,
1625 .hw
.init
= &(struct clk_init_data
){
1626 .name
= "cts_enci_sel",
1627 .ops
= &clk_regmap_mux_ops
,
1628 .parent_names
= g12a_cts_parent_names
,
1629 .num_parents
= ARRAY_SIZE(g12a_cts_parent_names
),
1630 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1634 static struct clk_regmap g12a_cts_encp_sel
= {
1635 .data
= &(struct clk_regmap_mux_data
){
1636 .offset
= HHI_VID_CLK_DIV
,
1639 .table
= mux_table_cts_sel
,
1641 .hw
.init
= &(struct clk_init_data
){
1642 .name
= "cts_encp_sel",
1643 .ops
= &clk_regmap_mux_ops
,
1644 .parent_names
= g12a_cts_parent_names
,
1645 .num_parents
= ARRAY_SIZE(g12a_cts_parent_names
),
1646 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1650 static struct clk_regmap g12a_cts_vdac_sel
= {
1651 .data
= &(struct clk_regmap_mux_data
){
1652 .offset
= HHI_VIID_CLK_DIV
,
1655 .table
= mux_table_cts_sel
,
1657 .hw
.init
= &(struct clk_init_data
){
1658 .name
= "cts_vdac_sel",
1659 .ops
= &clk_regmap_mux_ops
,
1660 .parent_names
= g12a_cts_parent_names
,
1661 .num_parents
= ARRAY_SIZE(g12a_cts_parent_names
),
1662 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1666 /* TOFIX: add support for cts_tcon */
1667 static u32 mux_table_hdmi_tx_sel
[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1668 static const char * const g12a_cts_hdmi_tx_parent_names
[] = {
1669 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
1670 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
1671 "vclk2_div6", "vclk2_div12"
1674 static struct clk_regmap g12a_hdmi_tx_sel
= {
1675 .data
= &(struct clk_regmap_mux_data
){
1676 .offset
= HHI_HDMI_CLK_CNTL
,
1679 .table
= mux_table_hdmi_tx_sel
,
1681 .hw
.init
= &(struct clk_init_data
){
1682 .name
= "hdmi_tx_sel",
1683 .ops
= &clk_regmap_mux_ops
,
1684 .parent_names
= g12a_cts_hdmi_tx_parent_names
,
1685 .num_parents
= ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names
),
1686 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1690 static struct clk_regmap g12a_cts_enci
= {
1691 .data
= &(struct clk_regmap_gate_data
){
1692 .offset
= HHI_VID_CLK_CNTL2
,
1695 .hw
.init
= &(struct clk_init_data
) {
1697 .ops
= &clk_regmap_gate_ops
,
1698 .parent_names
= (const char *[]){ "cts_enci_sel" },
1700 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1704 static struct clk_regmap g12a_cts_encp
= {
1705 .data
= &(struct clk_regmap_gate_data
){
1706 .offset
= HHI_VID_CLK_CNTL2
,
1709 .hw
.init
= &(struct clk_init_data
) {
1711 .ops
= &clk_regmap_gate_ops
,
1712 .parent_names
= (const char *[]){ "cts_encp_sel" },
1714 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1718 static struct clk_regmap g12a_cts_vdac
= {
1719 .data
= &(struct clk_regmap_gate_data
){
1720 .offset
= HHI_VID_CLK_CNTL2
,
1723 .hw
.init
= &(struct clk_init_data
) {
1725 .ops
= &clk_regmap_gate_ops
,
1726 .parent_names
= (const char *[]){ "cts_vdac_sel" },
1728 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1732 static struct clk_regmap g12a_hdmi_tx
= {
1733 .data
= &(struct clk_regmap_gate_data
){
1734 .offset
= HHI_VID_CLK_CNTL2
,
1737 .hw
.init
= &(struct clk_init_data
) {
1739 .ops
= &clk_regmap_gate_ops
,
1740 .parent_names
= (const char *[]){ "hdmi_tx_sel" },
1742 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1748 static const char * const g12a_hdmi_parent_names
[] = {
1749 IN_PREFIX
"xtal", "fclk_div4", "fclk_div3", "fclk_div5"
1752 static struct clk_regmap g12a_hdmi_sel
= {
1753 .data
= &(struct clk_regmap_mux_data
){
1754 .offset
= HHI_HDMI_CLK_CNTL
,
1757 .flags
= CLK_MUX_ROUND_CLOSEST
,
1759 .hw
.init
= &(struct clk_init_data
){
1761 .ops
= &clk_regmap_mux_ops
,
1762 .parent_names
= g12a_hdmi_parent_names
,
1763 .num_parents
= ARRAY_SIZE(g12a_hdmi_parent_names
),
1764 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1768 static struct clk_regmap g12a_hdmi_div
= {
1769 .data
= &(struct clk_regmap_div_data
){
1770 .offset
= HHI_HDMI_CLK_CNTL
,
1774 .hw
.init
= &(struct clk_init_data
){
1776 .ops
= &clk_regmap_divider_ops
,
1777 .parent_names
= (const char *[]){ "hdmi_sel" },
1779 .flags
= CLK_GET_RATE_NOCACHE
,
1783 static struct clk_regmap g12a_hdmi
= {
1784 .data
= &(struct clk_regmap_gate_data
){
1785 .offset
= HHI_HDMI_CLK_CNTL
,
1788 .hw
.init
= &(struct clk_init_data
) {
1790 .ops
= &clk_regmap_gate_ops
,
1791 .parent_names
= (const char *[]){ "hdmi_div" },
1793 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1798 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1799 * muxed by a glitch-free switch.
1802 static const char * const g12a_mali_0_1_parent_names
[] = {
1803 IN_PREFIX
"xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
1804 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
1807 static struct clk_regmap g12a_mali_0_sel
= {
1808 .data
= &(struct clk_regmap_mux_data
){
1809 .offset
= HHI_MALI_CLK_CNTL
,
1813 .hw
.init
= &(struct clk_init_data
){
1814 .name
= "mali_0_sel",
1815 .ops
= &clk_regmap_mux_ops
,
1816 .parent_names
= g12a_mali_0_1_parent_names
,
1818 .flags
= CLK_SET_RATE_NO_REPARENT
,
1822 static struct clk_regmap g12a_mali_0_div
= {
1823 .data
= &(struct clk_regmap_div_data
){
1824 .offset
= HHI_MALI_CLK_CNTL
,
1828 .hw
.init
= &(struct clk_init_data
){
1829 .name
= "mali_0_div",
1830 .ops
= &clk_regmap_divider_ops
,
1831 .parent_names
= (const char *[]){ "mali_0_sel" },
1833 .flags
= CLK_SET_RATE_NO_REPARENT
,
1837 static struct clk_regmap g12a_mali_0
= {
1838 .data
= &(struct clk_regmap_gate_data
){
1839 .offset
= HHI_MALI_CLK_CNTL
,
1842 .hw
.init
= &(struct clk_init_data
){
1844 .ops
= &clk_regmap_gate_ops
,
1845 .parent_names
= (const char *[]){ "mali_0_div" },
1847 .flags
= CLK_SET_RATE_PARENT
,
1851 static struct clk_regmap g12a_mali_1_sel
= {
1852 .data
= &(struct clk_regmap_mux_data
){
1853 .offset
= HHI_MALI_CLK_CNTL
,
1857 .hw
.init
= &(struct clk_init_data
){
1858 .name
= "mali_1_sel",
1859 .ops
= &clk_regmap_mux_ops
,
1860 .parent_names
= g12a_mali_0_1_parent_names
,
1862 .flags
= CLK_SET_RATE_NO_REPARENT
,
1866 static struct clk_regmap g12a_mali_1_div
= {
1867 .data
= &(struct clk_regmap_div_data
){
1868 .offset
= HHI_MALI_CLK_CNTL
,
1872 .hw
.init
= &(struct clk_init_data
){
1873 .name
= "mali_1_div",
1874 .ops
= &clk_regmap_divider_ops
,
1875 .parent_names
= (const char *[]){ "mali_1_sel" },
1877 .flags
= CLK_SET_RATE_NO_REPARENT
,
1881 static struct clk_regmap g12a_mali_1
= {
1882 .data
= &(struct clk_regmap_gate_data
){
1883 .offset
= HHI_MALI_CLK_CNTL
,
1886 .hw
.init
= &(struct clk_init_data
){
1888 .ops
= &clk_regmap_gate_ops
,
1889 .parent_names
= (const char *[]){ "mali_1_div" },
1891 .flags
= CLK_SET_RATE_PARENT
,
1895 static const char * const g12a_mali_parent_names
[] = {
1899 static struct clk_regmap g12a_mali
= {
1900 .data
= &(struct clk_regmap_mux_data
){
1901 .offset
= HHI_MALI_CLK_CNTL
,
1905 .hw
.init
= &(struct clk_init_data
){
1907 .ops
= &clk_regmap_mux_ops
,
1908 .parent_names
= g12a_mali_parent_names
,
1910 .flags
= CLK_SET_RATE_NO_REPARENT
,
1914 /* Everything Else (EE) domain gates */
1915 static MESON_GATE(g12a_ddr
, HHI_GCLK_MPEG0
, 0);
1916 static MESON_GATE(g12a_dos
, HHI_GCLK_MPEG0
, 1);
1917 static MESON_GATE(g12a_audio_locker
, HHI_GCLK_MPEG0
, 2);
1918 static MESON_GATE(g12a_mipi_dsi_host
, HHI_GCLK_MPEG0
, 3);
1919 static MESON_GATE(g12a_eth_phy
, HHI_GCLK_MPEG0
, 4);
1920 static MESON_GATE(g12a_isa
, HHI_GCLK_MPEG0
, 5);
1921 static MESON_GATE(g12a_pl301
, HHI_GCLK_MPEG0
, 6);
1922 static MESON_GATE(g12a_periphs
, HHI_GCLK_MPEG0
, 7);
1923 static MESON_GATE(g12a_spicc_0
, HHI_GCLK_MPEG0
, 8);
1924 static MESON_GATE(g12a_i2c
, HHI_GCLK_MPEG0
, 9);
1925 static MESON_GATE(g12a_sana
, HHI_GCLK_MPEG0
, 10);
1926 static MESON_GATE(g12a_sd
, HHI_GCLK_MPEG0
, 11);
1927 static MESON_GATE(g12a_rng0
, HHI_GCLK_MPEG0
, 12);
1928 static MESON_GATE(g12a_uart0
, HHI_GCLK_MPEG0
, 13);
1929 static MESON_GATE(g12a_spicc_1
, HHI_GCLK_MPEG0
, 14);
1930 static MESON_GATE(g12a_hiu_reg
, HHI_GCLK_MPEG0
, 19);
1931 static MESON_GATE(g12a_mipi_dsi_phy
, HHI_GCLK_MPEG0
, 20);
1932 static MESON_GATE(g12a_assist_misc
, HHI_GCLK_MPEG0
, 23);
1933 static MESON_GATE(g12a_emmc_a
, HHI_GCLK_MPEG0
, 4);
1934 static MESON_GATE(g12a_emmc_b
, HHI_GCLK_MPEG0
, 25);
1935 static MESON_GATE(g12a_emmc_c
, HHI_GCLK_MPEG0
, 26);
1936 static MESON_GATE(g12a_audio_codec
, HHI_GCLK_MPEG0
, 28);
1938 static MESON_GATE(g12a_audio
, HHI_GCLK_MPEG1
, 0);
1939 static MESON_GATE(g12a_eth_core
, HHI_GCLK_MPEG1
, 3);
1940 static MESON_GATE(g12a_demux
, HHI_GCLK_MPEG1
, 4);
1941 static MESON_GATE(g12a_audio_ififo
, HHI_GCLK_MPEG1
, 11);
1942 static MESON_GATE(g12a_adc
, HHI_GCLK_MPEG1
, 13);
1943 static MESON_GATE(g12a_uart1
, HHI_GCLK_MPEG1
, 16);
1944 static MESON_GATE(g12a_g2d
, HHI_GCLK_MPEG1
, 20);
1945 static MESON_GATE(g12a_reset
, HHI_GCLK_MPEG1
, 23);
1946 static MESON_GATE(g12a_pcie_comb
, HHI_GCLK_MPEG1
, 24);
1947 static MESON_GATE(g12a_parser
, HHI_GCLK_MPEG1
, 25);
1948 static MESON_GATE(g12a_usb_general
, HHI_GCLK_MPEG1
, 26);
1949 static MESON_GATE(g12a_pcie_phy
, HHI_GCLK_MPEG1
, 27);
1950 static MESON_GATE(g12a_ahb_arb0
, HHI_GCLK_MPEG1
, 29);
1952 static MESON_GATE(g12a_ahb_data_bus
, HHI_GCLK_MPEG2
, 1);
1953 static MESON_GATE(g12a_ahb_ctrl_bus
, HHI_GCLK_MPEG2
, 2);
1954 static MESON_GATE(g12a_htx_hdcp22
, HHI_GCLK_MPEG2
, 3);
1955 static MESON_GATE(g12a_htx_pclk
, HHI_GCLK_MPEG2
, 4);
1956 static MESON_GATE(g12a_bt656
, HHI_GCLK_MPEG2
, 6);
1957 static MESON_GATE(g12a_usb1_to_ddr
, HHI_GCLK_MPEG2
, 8);
1958 static MESON_GATE(g12a_mmc_pclk
, HHI_GCLK_MPEG2
, 11);
1959 static MESON_GATE(g12a_uart2
, HHI_GCLK_MPEG2
, 15);
1960 static MESON_GATE(g12a_vpu_intr
, HHI_GCLK_MPEG2
, 25);
1961 static MESON_GATE(g12a_gic
, HHI_GCLK_MPEG2
, 30);
1963 static MESON_GATE(g12a_vclk2_venci0
, HHI_GCLK_OTHER
, 1);
1964 static MESON_GATE(g12a_vclk2_venci1
, HHI_GCLK_OTHER
, 2);
1965 static MESON_GATE(g12a_vclk2_vencp0
, HHI_GCLK_OTHER
, 3);
1966 static MESON_GATE(g12a_vclk2_vencp1
, HHI_GCLK_OTHER
, 4);
1967 static MESON_GATE(g12a_vclk2_venct0
, HHI_GCLK_OTHER
, 5);
1968 static MESON_GATE(g12a_vclk2_venct1
, HHI_GCLK_OTHER
, 6);
1969 static MESON_GATE(g12a_vclk2_other
, HHI_GCLK_OTHER
, 7);
1970 static MESON_GATE(g12a_vclk2_enci
, HHI_GCLK_OTHER
, 8);
1971 static MESON_GATE(g12a_vclk2_encp
, HHI_GCLK_OTHER
, 9);
1972 static MESON_GATE(g12a_dac_clk
, HHI_GCLK_OTHER
, 10);
1973 static MESON_GATE(g12a_aoclk_gate
, HHI_GCLK_OTHER
, 14);
1974 static MESON_GATE(g12a_iec958_gate
, HHI_GCLK_OTHER
, 16);
1975 static MESON_GATE(g12a_enc480p
, HHI_GCLK_OTHER
, 20);
1976 static MESON_GATE(g12a_rng1
, HHI_GCLK_OTHER
, 21);
1977 static MESON_GATE(g12a_vclk2_enct
, HHI_GCLK_OTHER
, 22);
1978 static MESON_GATE(g12a_vclk2_encl
, HHI_GCLK_OTHER
, 23);
1979 static MESON_GATE(g12a_vclk2_venclmmc
, HHI_GCLK_OTHER
, 24);
1980 static MESON_GATE(g12a_vclk2_vencl
, HHI_GCLK_OTHER
, 25);
1981 static MESON_GATE(g12a_vclk2_other1
, HHI_GCLK_OTHER
, 26);
1983 static MESON_GATE_RO(g12a_dma
, HHI_GCLK_OTHER2
, 0);
1984 static MESON_GATE_RO(g12a_efuse
, HHI_GCLK_OTHER2
, 1);
1985 static MESON_GATE_RO(g12a_rom_boot
, HHI_GCLK_OTHER2
, 2);
1986 static MESON_GATE_RO(g12a_reset_sec
, HHI_GCLK_OTHER2
, 3);
1987 static MESON_GATE_RO(g12a_sec_ahb_apb3
, HHI_GCLK_OTHER2
, 4);
1989 /* Array of all clocks provided by this provider */
1990 static struct clk_hw_onecell_data g12a_hw_onecell_data
= {
1992 [CLKID_SYS_PLL
] = &g12a_sys_pll
.hw
,
1993 [CLKID_FIXED_PLL
] = &g12a_fixed_pll
.hw
,
1994 [CLKID_FCLK_DIV2
] = &g12a_fclk_div2
.hw
,
1995 [CLKID_FCLK_DIV3
] = &g12a_fclk_div3
.hw
,
1996 [CLKID_FCLK_DIV4
] = &g12a_fclk_div4
.hw
,
1997 [CLKID_FCLK_DIV5
] = &g12a_fclk_div5
.hw
,
1998 [CLKID_FCLK_DIV7
] = &g12a_fclk_div7
.hw
,
1999 [CLKID_FCLK_DIV2P5
] = &g12a_fclk_div2p5
.hw
,
2000 [CLKID_GP0_PLL
] = &g12a_gp0_pll
.hw
,
2001 [CLKID_MPEG_SEL
] = &g12a_mpeg_clk_sel
.hw
,
2002 [CLKID_MPEG_DIV
] = &g12a_mpeg_clk_div
.hw
,
2003 [CLKID_CLK81
] = &g12a_clk81
.hw
,
2004 [CLKID_MPLL0
] = &g12a_mpll0
.hw
,
2005 [CLKID_MPLL1
] = &g12a_mpll1
.hw
,
2006 [CLKID_MPLL2
] = &g12a_mpll2
.hw
,
2007 [CLKID_MPLL3
] = &g12a_mpll3
.hw
,
2008 [CLKID_DDR
] = &g12a_ddr
.hw
,
2009 [CLKID_DOS
] = &g12a_dos
.hw
,
2010 [CLKID_AUDIO_LOCKER
] = &g12a_audio_locker
.hw
,
2011 [CLKID_MIPI_DSI_HOST
] = &g12a_mipi_dsi_host
.hw
,
2012 [CLKID_ETH_PHY
] = &g12a_eth_phy
.hw
,
2013 [CLKID_ISA
] = &g12a_isa
.hw
,
2014 [CLKID_PL301
] = &g12a_pl301
.hw
,
2015 [CLKID_PERIPHS
] = &g12a_periphs
.hw
,
2016 [CLKID_SPICC0
] = &g12a_spicc_0
.hw
,
2017 [CLKID_I2C
] = &g12a_i2c
.hw
,
2018 [CLKID_SANA
] = &g12a_sana
.hw
,
2019 [CLKID_SD
] = &g12a_sd
.hw
,
2020 [CLKID_RNG0
] = &g12a_rng0
.hw
,
2021 [CLKID_UART0
] = &g12a_uart0
.hw
,
2022 [CLKID_SPICC1
] = &g12a_spicc_1
.hw
,
2023 [CLKID_HIU_IFACE
] = &g12a_hiu_reg
.hw
,
2024 [CLKID_MIPI_DSI_PHY
] = &g12a_mipi_dsi_phy
.hw
,
2025 [CLKID_ASSIST_MISC
] = &g12a_assist_misc
.hw
,
2026 [CLKID_SD_EMMC_A
] = &g12a_emmc_a
.hw
,
2027 [CLKID_SD_EMMC_B
] = &g12a_emmc_b
.hw
,
2028 [CLKID_SD_EMMC_C
] = &g12a_emmc_c
.hw
,
2029 [CLKID_AUDIO_CODEC
] = &g12a_audio_codec
.hw
,
2030 [CLKID_AUDIO
] = &g12a_audio
.hw
,
2031 [CLKID_ETH
] = &g12a_eth_core
.hw
,
2032 [CLKID_DEMUX
] = &g12a_demux
.hw
,
2033 [CLKID_AUDIO_IFIFO
] = &g12a_audio_ififo
.hw
,
2034 [CLKID_ADC
] = &g12a_adc
.hw
,
2035 [CLKID_UART1
] = &g12a_uart1
.hw
,
2036 [CLKID_G2D
] = &g12a_g2d
.hw
,
2037 [CLKID_RESET
] = &g12a_reset
.hw
,
2038 [CLKID_PCIE_COMB
] = &g12a_pcie_comb
.hw
,
2039 [CLKID_PARSER
] = &g12a_parser
.hw
,
2040 [CLKID_USB
] = &g12a_usb_general
.hw
,
2041 [CLKID_PCIE_PHY
] = &g12a_pcie_phy
.hw
,
2042 [CLKID_AHB_ARB0
] = &g12a_ahb_arb0
.hw
,
2043 [CLKID_AHB_DATA_BUS
] = &g12a_ahb_data_bus
.hw
,
2044 [CLKID_AHB_CTRL_BUS
] = &g12a_ahb_ctrl_bus
.hw
,
2045 [CLKID_HTX_HDCP22
] = &g12a_htx_hdcp22
.hw
,
2046 [CLKID_HTX_PCLK
] = &g12a_htx_pclk
.hw
,
2047 [CLKID_BT656
] = &g12a_bt656
.hw
,
2048 [CLKID_USB1_DDR_BRIDGE
] = &g12a_usb1_to_ddr
.hw
,
2049 [CLKID_MMC_PCLK
] = &g12a_mmc_pclk
.hw
,
2050 [CLKID_UART2
] = &g12a_uart2
.hw
,
2051 [CLKID_VPU_INTR
] = &g12a_vpu_intr
.hw
,
2052 [CLKID_GIC
] = &g12a_gic
.hw
,
2053 [CLKID_SD_EMMC_A_CLK0_SEL
] = &g12a_sd_emmc_a_clk0_sel
.hw
,
2054 [CLKID_SD_EMMC_A_CLK0_DIV
] = &g12a_sd_emmc_a_clk0_div
.hw
,
2055 [CLKID_SD_EMMC_A_CLK0
] = &g12a_sd_emmc_a_clk0
.hw
,
2056 [CLKID_SD_EMMC_B_CLK0_SEL
] = &g12a_sd_emmc_b_clk0_sel
.hw
,
2057 [CLKID_SD_EMMC_B_CLK0_DIV
] = &g12a_sd_emmc_b_clk0_div
.hw
,
2058 [CLKID_SD_EMMC_B_CLK0
] = &g12a_sd_emmc_b_clk0
.hw
,
2059 [CLKID_SD_EMMC_C_CLK0_SEL
] = &g12a_sd_emmc_c_clk0_sel
.hw
,
2060 [CLKID_SD_EMMC_C_CLK0_DIV
] = &g12a_sd_emmc_c_clk0_div
.hw
,
2061 [CLKID_SD_EMMC_C_CLK0
] = &g12a_sd_emmc_c_clk0
.hw
,
2062 [CLKID_MPLL0_DIV
] = &g12a_mpll0_div
.hw
,
2063 [CLKID_MPLL1_DIV
] = &g12a_mpll1_div
.hw
,
2064 [CLKID_MPLL2_DIV
] = &g12a_mpll2_div
.hw
,
2065 [CLKID_MPLL3_DIV
] = &g12a_mpll3_div
.hw
,
2066 [CLKID_FCLK_DIV2_DIV
] = &g12a_fclk_div2_div
.hw
,
2067 [CLKID_FCLK_DIV3_DIV
] = &g12a_fclk_div3_div
.hw
,
2068 [CLKID_FCLK_DIV4_DIV
] = &g12a_fclk_div4_div
.hw
,
2069 [CLKID_FCLK_DIV5_DIV
] = &g12a_fclk_div5_div
.hw
,
2070 [CLKID_FCLK_DIV7_DIV
] = &g12a_fclk_div7_div
.hw
,
2071 [CLKID_FCLK_DIV2P5_DIV
] = &g12a_fclk_div2p5_div
.hw
,
2072 [CLKID_HIFI_PLL
] = &g12a_hifi_pll
.hw
,
2073 [CLKID_VCLK2_VENCI0
] = &g12a_vclk2_venci0
.hw
,
2074 [CLKID_VCLK2_VENCI1
] = &g12a_vclk2_venci1
.hw
,
2075 [CLKID_VCLK2_VENCP0
] = &g12a_vclk2_vencp0
.hw
,
2076 [CLKID_VCLK2_VENCP1
] = &g12a_vclk2_vencp1
.hw
,
2077 [CLKID_VCLK2_VENCT0
] = &g12a_vclk2_venct0
.hw
,
2078 [CLKID_VCLK2_VENCT1
] = &g12a_vclk2_venct1
.hw
,
2079 [CLKID_VCLK2_OTHER
] = &g12a_vclk2_other
.hw
,
2080 [CLKID_VCLK2_ENCI
] = &g12a_vclk2_enci
.hw
,
2081 [CLKID_VCLK2_ENCP
] = &g12a_vclk2_encp
.hw
,
2082 [CLKID_DAC_CLK
] = &g12a_dac_clk
.hw
,
2083 [CLKID_AOCLK
] = &g12a_aoclk_gate
.hw
,
2084 [CLKID_IEC958
] = &g12a_iec958_gate
.hw
,
2085 [CLKID_ENC480P
] = &g12a_enc480p
.hw
,
2086 [CLKID_RNG1
] = &g12a_rng1
.hw
,
2087 [CLKID_VCLK2_ENCT
] = &g12a_vclk2_enct
.hw
,
2088 [CLKID_VCLK2_ENCL
] = &g12a_vclk2_encl
.hw
,
2089 [CLKID_VCLK2_VENCLMMC
] = &g12a_vclk2_venclmmc
.hw
,
2090 [CLKID_VCLK2_VENCL
] = &g12a_vclk2_vencl
.hw
,
2091 [CLKID_VCLK2_OTHER1
] = &g12a_vclk2_other1
.hw
,
2092 [CLKID_FIXED_PLL_DCO
] = &g12a_fixed_pll_dco
.hw
,
2093 [CLKID_SYS_PLL_DCO
] = &g12a_sys_pll_dco
.hw
,
2094 [CLKID_GP0_PLL_DCO
] = &g12a_gp0_pll_dco
.hw
,
2095 [CLKID_HIFI_PLL_DCO
] = &g12a_hifi_pll_dco
.hw
,
2096 [CLKID_DMA
] = &g12a_dma
.hw
,
2097 [CLKID_EFUSE
] = &g12a_efuse
.hw
,
2098 [CLKID_ROM_BOOT
] = &g12a_rom_boot
.hw
,
2099 [CLKID_RESET_SEC
] = &g12a_reset_sec
.hw
,
2100 [CLKID_SEC_AHB_APB3
] = &g12a_sec_ahb_apb3
.hw
,
2101 [CLKID_MPLL_PREDIV
] = &g12a_mpll_prediv
.hw
,
2102 [CLKID_VPU_0_SEL
] = &g12a_vpu_0_sel
.hw
,
2103 [CLKID_VPU_0_DIV
] = &g12a_vpu_0_div
.hw
,
2104 [CLKID_VPU_0
] = &g12a_vpu_0
.hw
,
2105 [CLKID_VPU_1_SEL
] = &g12a_vpu_1_sel
.hw
,
2106 [CLKID_VPU_1_DIV
] = &g12a_vpu_1_div
.hw
,
2107 [CLKID_VPU_1
] = &g12a_vpu_1
.hw
,
2108 [CLKID_VPU
] = &g12a_vpu
.hw
,
2109 [CLKID_VAPB_0_SEL
] = &g12a_vapb_0_sel
.hw
,
2110 [CLKID_VAPB_0_DIV
] = &g12a_vapb_0_div
.hw
,
2111 [CLKID_VAPB_0
] = &g12a_vapb_0
.hw
,
2112 [CLKID_VAPB_1_SEL
] = &g12a_vapb_1_sel
.hw
,
2113 [CLKID_VAPB_1_DIV
] = &g12a_vapb_1_div
.hw
,
2114 [CLKID_VAPB_1
] = &g12a_vapb_1
.hw
,
2115 [CLKID_VAPB_SEL
] = &g12a_vapb_sel
.hw
,
2116 [CLKID_VAPB
] = &g12a_vapb
.hw
,
2117 [CLKID_HDMI_PLL_DCO
] = &g12a_hdmi_pll_dco
.hw
,
2118 [CLKID_HDMI_PLL_OD
] = &g12a_hdmi_pll_od
.hw
,
2119 [CLKID_HDMI_PLL_OD2
] = &g12a_hdmi_pll_od2
.hw
,
2120 [CLKID_HDMI_PLL
] = &g12a_hdmi_pll
.hw
,
2121 [CLKID_VID_PLL
] = &g12a_vid_pll_div
.hw
,
2122 [CLKID_VID_PLL_SEL
] = &g12a_vid_pll_sel
.hw
,
2123 [CLKID_VID_PLL_DIV
] = &g12a_vid_pll
.hw
,
2124 [CLKID_VCLK_SEL
] = &g12a_vclk_sel
.hw
,
2125 [CLKID_VCLK2_SEL
] = &g12a_vclk2_sel
.hw
,
2126 [CLKID_VCLK_INPUT
] = &g12a_vclk_input
.hw
,
2127 [CLKID_VCLK2_INPUT
] = &g12a_vclk2_input
.hw
,
2128 [CLKID_VCLK_DIV
] = &g12a_vclk_div
.hw
,
2129 [CLKID_VCLK2_DIV
] = &g12a_vclk2_div
.hw
,
2130 [CLKID_VCLK
] = &g12a_vclk
.hw
,
2131 [CLKID_VCLK2
] = &g12a_vclk2
.hw
,
2132 [CLKID_VCLK_DIV1
] = &g12a_vclk_div1
.hw
,
2133 [CLKID_VCLK_DIV2_EN
] = &g12a_vclk_div2_en
.hw
,
2134 [CLKID_VCLK_DIV4_EN
] = &g12a_vclk_div4_en
.hw
,
2135 [CLKID_VCLK_DIV6_EN
] = &g12a_vclk_div6_en
.hw
,
2136 [CLKID_VCLK_DIV12_EN
] = &g12a_vclk_div12_en
.hw
,
2137 [CLKID_VCLK2_DIV1
] = &g12a_vclk2_div1
.hw
,
2138 [CLKID_VCLK2_DIV2_EN
] = &g12a_vclk2_div2_en
.hw
,
2139 [CLKID_VCLK2_DIV4_EN
] = &g12a_vclk2_div4_en
.hw
,
2140 [CLKID_VCLK2_DIV6_EN
] = &g12a_vclk2_div6_en
.hw
,
2141 [CLKID_VCLK2_DIV12_EN
] = &g12a_vclk2_div12_en
.hw
,
2142 [CLKID_VCLK_DIV2
] = &g12a_vclk_div2
.hw
,
2143 [CLKID_VCLK_DIV4
] = &g12a_vclk_div4
.hw
,
2144 [CLKID_VCLK_DIV6
] = &g12a_vclk_div6
.hw
,
2145 [CLKID_VCLK_DIV12
] = &g12a_vclk_div12
.hw
,
2146 [CLKID_VCLK2_DIV2
] = &g12a_vclk2_div2
.hw
,
2147 [CLKID_VCLK2_DIV4
] = &g12a_vclk2_div4
.hw
,
2148 [CLKID_VCLK2_DIV6
] = &g12a_vclk2_div6
.hw
,
2149 [CLKID_VCLK2_DIV12
] = &g12a_vclk2_div12
.hw
,
2150 [CLKID_CTS_ENCI_SEL
] = &g12a_cts_enci_sel
.hw
,
2151 [CLKID_CTS_ENCP_SEL
] = &g12a_cts_encp_sel
.hw
,
2152 [CLKID_CTS_VDAC_SEL
] = &g12a_cts_vdac_sel
.hw
,
2153 [CLKID_HDMI_TX_SEL
] = &g12a_hdmi_tx_sel
.hw
,
2154 [CLKID_CTS_ENCI
] = &g12a_cts_enci
.hw
,
2155 [CLKID_CTS_ENCP
] = &g12a_cts_encp
.hw
,
2156 [CLKID_CTS_VDAC
] = &g12a_cts_vdac
.hw
,
2157 [CLKID_HDMI_TX
] = &g12a_hdmi_tx
.hw
,
2158 [CLKID_HDMI_SEL
] = &g12a_hdmi_sel
.hw
,
2159 [CLKID_HDMI_DIV
] = &g12a_hdmi_div
.hw
,
2160 [CLKID_HDMI
] = &g12a_hdmi
.hw
,
2161 [CLKID_MALI_0_SEL
] = &g12a_mali_0_sel
.hw
,
2162 [CLKID_MALI_0_DIV
] = &g12a_mali_0_div
.hw
,
2163 [CLKID_MALI_0
] = &g12a_mali_0
.hw
,
2164 [CLKID_MALI_1_SEL
] = &g12a_mali_1_sel
.hw
,
2165 [CLKID_MALI_1_DIV
] = &g12a_mali_1_div
.hw
,
2166 [CLKID_MALI_1
] = &g12a_mali_1
.hw
,
2167 [CLKID_MALI
] = &g12a_mali
.hw
,
2168 [CLKID_MPLL_5OM_DIV
] = &g12a_mpll_50m_div
.hw
,
2169 [CLKID_MPLL_5OM
] = &g12a_mpll_50m
.hw
,
2175 /* Convenience table to populate regmap in .probe */
2176 static struct clk_regmap
*const g12a_clk_regmaps
[] = {
2181 &g12a_mipi_dsi_host
,
2222 &g12a_sd_emmc_a_clk0
,
2223 &g12a_sd_emmc_b_clk0
,
2224 &g12a_sd_emmc_c_clk0
,
2226 &g12a_sd_emmc_a_clk0_div
,
2227 &g12a_sd_emmc_b_clk0_div
,
2228 &g12a_sd_emmc_c_clk0_div
,
2230 &g12a_sd_emmc_a_clk0_sel
,
2231 &g12a_sd_emmc_b_clk0_sel
,
2232 &g12a_sd_emmc_c_clk0_sel
,
2261 &g12a_vclk2_venclmmc
,
2264 &g12a_fixed_pll_dco
,
2313 &g12a_vclk_div12_en
,
2315 &g12a_vclk2_div2_en
,
2316 &g12a_vclk2_div4_en
,
2317 &g12a_vclk2_div6_en
,
2318 &g12a_vclk2_div12_en
,
2340 static const struct meson_eeclkc_data g12a_clkc_data
= {
2341 .regmap_clks
= g12a_clk_regmaps
,
2342 .regmap_clk_num
= ARRAY_SIZE(g12a_clk_regmaps
),
2343 .hw_onecell_data
= &g12a_hw_onecell_data
2346 static const struct of_device_id clkc_match_table
[] = {
2347 { .compatible
= "amlogic,g12a-clkc", .data
= &g12a_clkc_data
},
2351 static struct platform_driver g12a_driver
= {
2352 .probe
= meson_eeclkc_probe
,
2354 .name
= "g12a-clkc",
2355 .of_match_table
= clkc_match_table
,
2359 builtin_platform_driver(g12a_driver
);