drivers/clk/mmp/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MACH_MMP_CLK_H
   3 #define __MACH_MMP_CLK_H
   4
   5 #include <linux/clk-provider.h>
   6 #include <linux/clkdev.h>
   7
   8 #define APBC_NO_BUS_CTRL        BIT(0)
   9 #define APBC_POWER_CTRL         BIT(1)
  10
  11
  12 /* Clock type "factor" */
  13 struct mmp_clk_factor_masks {
  14         unsigned int factor;
  15         unsigned int num_mask;
  16         unsigned int den_mask;
  17         unsigned int num_shift;
  18         unsigned int den_shift;
  19 };
  20
  21 struct mmp_clk_factor_tbl {
  22         unsigned int num;
  23         unsigned int den;
  24 };
  25
  26 struct mmp_clk_factor {
  27         struct clk_hw hw;
  28         void __iomem *base;
  29         struct mmp_clk_factor_masks *masks;
  30         struct mmp_clk_factor_tbl *ftbl;
  31         unsigned int ftbl_cnt;
  32         spinlock_t *lock;
  33 };
  34
  35 extern struct clk *mmp_clk_register_factor(const char *name,
  36                 const char *parent_name, unsigned long flags,
  37                 void __iomem *base, struct mmp_clk_factor_masks *masks,
  38                 struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
  39                 spinlock_t *lock);
  40
  41 /* Clock type "mix" */
  42 #define MMP_CLK_BITS_MASK(width, shift)                 \
  43                 (((1 << (width)) - 1) << (shift))
  44 #define MMP_CLK_BITS_GET_VAL(data, width, shift)        \
  45                 ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
  46 #define MMP_CLK_BITS_SET_VAL(val, width, shift)         \
  47                 (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
  48
  49 enum {
  50         MMP_CLK_MIX_TYPE_V1,
  51         MMP_CLK_MIX_TYPE_V2,
  52         MMP_CLK_MIX_TYPE_V3,
  53 };
  54
  55 /* The register layout */
  56 struct mmp_clk_mix_reg_info {
  57         void __iomem *reg_clk_ctrl;
  58         void __iomem *reg_clk_sel;
  59         u8 width_div;
  60         u8 shift_div;
  61         u8 width_mux;
  62         u8 shift_mux;
  63         u8 bit_fc;
  64 };
  65
  66 /* The suggested clock table from user. */
  67 struct mmp_clk_mix_clk_table {
  68         unsigned long rate;
  69         u8 parent_index;
  70         unsigned int divisor;
  71         unsigned int valid;
  72 };
  73
  74 struct mmp_clk_mix_config {
  75         struct mmp_clk_mix_reg_info reg_info;
  76         struct mmp_clk_mix_clk_table *table;
  77         unsigned int table_size;
  78         u32 *mux_table;
  79         struct clk_div_table *div_table;
  80         u8 div_flags;
  81         u8 mux_flags;
  82 };
  83
  84 struct mmp_clk_mix {
  85         struct clk_hw hw;
  86         struct mmp_clk_mix_reg_info reg_info;
  87         struct mmp_clk_mix_clk_table *table;
  88         u32 *mux_table;
  89         struct clk_div_table *div_table;
  90         unsigned int table_size;
  91         u8 div_flags;
  92         u8 mux_flags;
  93         unsigned int type;
  94         spinlock_t *lock;
  95 };
  96
  97 extern const struct clk_ops mmp_clk_mix_ops;
  98 extern struct clk *mmp_clk_register_mix(struct device *dev,
  99                                         const char *name,
 100                                         const char * const *parent_names,
 101                                         u8 num_parents,
 102                                         unsigned long flags,
 103                                         struct mmp_clk_mix_config *config,
 104                                         spinlock_t *lock);
 105
 106
 107 /* Clock type "gate". MMP private gate */
 108 #define MMP_CLK_GATE_NEED_DELAY         BIT(0)
 109
 110 struct mmp_clk_gate {
 111         struct clk_hw hw;
 112         void __iomem *reg;
 113         u32 mask;
 114         u32 val_enable;
 115         u32 val_disable;
 116         unsigned int flags;
 117         spinlock_t *lock;
 118 };
 119
 120 extern const struct clk_ops mmp_clk_gate_ops;
 121 extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
 122                         const char *parent_name, unsigned long flags,
 123                         void __iomem *reg, u32 mask, u32 val_enable,
 124                         u32 val_disable, unsigned int gate_flags,
 125                         spinlock_t *lock);
 126
 127 extern struct clk *mmp_clk_register_apbc(const char *name,
 128                 const char *parent_name, void __iomem *base,
 129                 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
 130 extern struct clk *mmp_clk_register_apmu(const char *name,
 131                 const char *parent_name, void __iomem *base, u32 enable_mask,
 132                 spinlock_t *lock);
 133
 134 struct mmp_clk_unit {
 135         unsigned int nr_clks;
 136         struct clk **clk_table;
 137         struct clk_onecell_data clk_data;
 138 };
 139
 140 struct mmp_param_fixed_rate_clk {
 141         unsigned int id;
 142         char *name;
 143         const char *parent_name;
 144         unsigned long flags;
 145         unsigned long fixed_rate;
 146 };
 147 void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
 148                                 struct mmp_param_fixed_rate_clk *clks,
 149                                 int size);
 150
 151 struct mmp_param_fixed_factor_clk {
 152         unsigned int id;
 153         char *name;
 154         const char *parent_name;
 155         unsigned long mult;
 156         unsigned long div;
 157         unsigned long flags;
 158 };
 159 void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
 160                                 struct mmp_param_fixed_factor_clk *clks,
 161                                 int size);
 162
 163 struct mmp_param_general_gate_clk {
 164         unsigned int id;
 165         const char *name;
 166         const char *parent_name;
 167         unsigned long flags;
 168         unsigned long offset;
 169         u8 bit_idx;
 170         u8 gate_flags;
 171         spinlock_t *lock;
 172 };
 173 void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
 174                                 struct mmp_param_general_gate_clk *clks,
 175                                 void __iomem *base, int size);
 176
 177 struct mmp_param_gate_clk {
 178         unsigned int id;
 179         char *name;
 180         const char *parent_name;
 181         unsigned long flags;
 182         unsigned long offset;
 183         u32 mask;
 184         u32 val_enable;
 185         u32 val_disable;
 186         unsigned int gate_flags;
 187         spinlock_t *lock;
 188 };
 189 void mmp_register_gate_clks(struct mmp_clk_unit *unit,
 190                         struct mmp_param_gate_clk *clks,
 191                         void __iomem *base, int size);
 192
 193 struct mmp_param_mux_clk {
 194         unsigned int id;
 195         char *name;
 196         const char * const *parent_name;
 197         u8 num_parents;
 198         unsigned long flags;
 199         unsigned long offset;
 200         u8 shift;
 201         u8 width;
 202         u8 mux_flags;
 203         spinlock_t *lock;
 204 };
 205 void mmp_register_mux_clks(struct mmp_clk_unit *unit,
 206                         struct mmp_param_mux_clk *clks,
 207                         void __iomem *base, int size);
 208
 209 struct mmp_param_div_clk {
 210         unsigned int id;
 211         char *name;
 212         const char *parent_name;
 213         unsigned long flags;
 214         unsigned long offset;
 215         u8 shift;
 216         u8 width;
 217         u8 div_flags;
 218         spinlock_t *lock;
 219 };
 220 void mmp_register_div_clks(struct mmp_clk_unit *unit,
 221                         struct mmp_param_div_clk *clks,
 222                         void __iomem *base, int size);
 223
 224 struct mmp_param_pll_clk {
 225         unsigned int id;
 226         char *name;
 227         unsigned long default_rate;
 228         unsigned long enable_offset;
 229         u32 enable;
 230         unsigned long offset;
 231         u8 shift;
 232         /* MMP3 specific: */
 233         unsigned long input_rate;
 234         unsigned long postdiv_offset;
 235         unsigned long postdiv_shift;
 236 };
 237 void mmp_register_pll_clks(struct mmp_clk_unit *unit,
 238                         struct mmp_param_pll_clk *clks,
 239                         void __iomem *base, int size);
 240
 241 #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)     \
 242 {                                                       \
 243         .width_div = (w_d),                             \
 244         .shift_div = (s_d),                             \
 245         .width_mux = (w_m),                             \
 246         .shift_mux = (s_m),                             \
 247         .bit_fc = (fc),                                 \
 248 }
 249
 250 void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
 251                 int nr_clks);
 252 void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
 253                 struct clk *clk);
 254 #endif