drivers/clk/pxa/clk-pxa25x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell PXA25x family clocks
   4  *
   5  * Copyright (C) 2014 Robert Jarzmik
   6  *
   7  * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
   8  *
   9  * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
  10  * should go away.
  11  */
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <mach/pxa2xx-regs.h>
  18 #include <linux/soc/pxa/smemc.h>
  19
  20 #include <dt-bindings/clock/pxa-clock.h>
  21 #include "clk-pxa.h"
  22
  23 #define KHz 1000
  24 #define MHz (1000 * 1000)
  25
  26 enum {
  27         PXA_CORE_RUN = 0,
  28         PXA_CORE_TURBO,
  29 };
  30
  31 #define PXA25x_CLKCFG(T)                        \
  32         (CLKCFG_FCS |                           \
  33          ((T) ? CLKCFG_TURBO : 0))
  34 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
  35
  36 /* Define the refresh period in mSec for the SDRAM and the number of rows */
  37 #define SDRAM_TREF      64      /* standard 64ms SDRAM */
  38
  39 /*
  40  * Various clock factors driven by the CCCR register.
  41  */
  42
  43 /* Crystal Frequency to Memory Frequency Multiplier (L) */
  44 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
  45
  46 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
  47 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
  48
  49 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
  50 /* Note: we store the value N * 2 here. */
  51 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  52
  53 static const char * const get_freq_khz[] = {
  54         "core", "run", "cpll", "memory"
  55 };
  56
  57 static u32 mdrefr_dri(unsigned int freq_khz)
  58 {
  59         u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
  60
  61         return interval / 32;
  62 }
  63
  64 /*
  65  * Get the clock frequency as reflected by CCCR and the turbo flag.
  66  * We assume these values have been applied via a fcs.
  67  * If info is not 0 we also display the current settings.
  68  */
  69 unsigned int pxa25x_get_clk_frequency_khz(int info)
  70 {
  71         struct clk *clk;
  72         unsigned long clks[5];
  73         int i;
  74
  75         for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
  76                 clk = clk_get(NULL, get_freq_khz[i]);
  77                 if (IS_ERR(clk)) {
  78                         clks[i] = 0;
  79                 } else {
  80                         clks[i] = clk_get_rate(clk);
  81                         clk_put(clk);
  82                 }
  83         }
  84
  85         if (info) {
  86                 pr_info("Run Mode clock: %ld.%02ldMHz\n",
  87                         clks[1] / 1000000, (clks[1] % 1000000) / 10000);
  88                 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
  89                         clks[2] / 1000000, (clks[2] % 1000000) / 10000);
  90                 pr_info("Memory clock: %ld.%02ldMHz\n",
  91                         clks[3] / 1000000, (clks[3] % 1000000) / 10000);
  92         }
  93
  94         return (unsigned int)clks[0] / KHz;
  95 }
  96
  97 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
  98                                                 unsigned long parent_rate)
  99 {
 100         unsigned long cccr = readl(CCCR);
 101         unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
 102
 103         return parent_rate / m;
 104 }
 105 PARENTS(clk_pxa25x_memory) = { "run" };
 106 RATE_RO_OPS(clk_pxa25x_memory, "memory");
 107
 108 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
 109 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
 110 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
 111
 112 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div,                 \
 113                     bit, is_lp, flags)                                  \
 114         PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div,    \
 115                  is_lp,  CKEN, CKEN_ ## bit, flags)
 116 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
 117         PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp,     \
 118                     div_hp, bit, NULL, 0)
 119 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
 120         PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp,    \
 121                     div_hp, bit, NULL, 0)
 122 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)   \
 123         PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp,       \
 124                     div_hp, bit, NULL, 0)
 125
 126 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)          \
 127         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
 128                        CKEN, CKEN_ ## bit, 0)
 129 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)       \
 130         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
 131                        CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
 132
 133 static struct desc_clk_cken pxa25x_clocks[] __initdata = {
 134         PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
 135         PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
 136         PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
 137         PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
 138         PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
 139         PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
 140         PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
 141         PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
 142         PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
 143         PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
 144         PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
 145         PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
 146         PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
 147         PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
 148         PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
 149
 150         PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
 151         PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
 152                              clk_pxa25x_memory_parents, 0),
 153 };
 154
 155 /*
 156  * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
 157  *   - freq_cpll = n * m * L * 3.6864 MHz
 158  *   - n = N2 / 2
 159  *   - m = 2^(M - 1), where 1 <= M <= 3
 160  *   - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
 161  */
 162 static struct pxa2xx_freq pxa25x_freqs[] = {
 163         /* CPU  MEMBUS  CCCR                  DIV2 CCLKCFG      */
 164         { 99532800, 99500, PXA25x_CCCR(2,  1, 1),  1, PXA25x_CLKCFG(1)},
 165         {199065600, 99500, PXA25x_CCCR(4,  1, 1),  0, PXA25x_CLKCFG(1)},
 166         {298598400, 99500, PXA25x_CCCR(3,  2, 1),  0, PXA25x_CLKCFG(1)},
 167         {398131200, 99500, PXA25x_CCCR(4,  2, 1),  0, PXA25x_CLKCFG(1)},
 168 };
 169
 170 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
 171 {
 172         unsigned long clkcfg;
 173         unsigned int t;
 174
 175         asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 176         t  = clkcfg & (1 << 0);
 177         if (t)
 178                 return PXA_CORE_TURBO;
 179         return PXA_CORE_RUN;
 180 }
 181
 182 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
 183 {
 184         if (index > PXA_CORE_TURBO)
 185                 return -EINVAL;
 186
 187         pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
 188
 189         return 0;
 190 }
 191
 192 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
 193                                           struct clk_rate_request *req)
 194 {
 195         return __clk_mux_determine_rate(hw, req);
 196 }
 197
 198 PARENTS(clk_pxa25x_core) = { "run", "cpll" };
 199 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
 200
 201 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
 202                                              unsigned long parent_rate)
 203 {
 204         unsigned long cccr = readl(CCCR);
 205         unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
 206
 207         return (parent_rate / n2) * 2;
 208 }
 209 PARENTS(clk_pxa25x_run) = { "cpll" };
 210 RATE_RO_OPS(clk_pxa25x_run, "run");
 211
 212 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
 213         unsigned long parent_rate)
 214 {
 215         unsigned long clkcfg, cccr = readl(CCCR);
 216         unsigned int l, m, n2, t;
 217
 218         asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 219         t = clkcfg & (1 << 0);
 220         l  =  L_clk_mult[(cccr >> 0) & 0x1f];
 221         m = M_clk_mult[(cccr >> 5) & 0x03];
 222         n2 = N2_clk_mult[(cccr >> 7) & 0x07];
 223
 224         return m * l * n2 * parent_rate / 2;
 225 }
 226
 227 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
 228                                           struct clk_rate_request *req)
 229 {
 230         return pxa2xx_determine_rate(req, pxa25x_freqs,
 231                                      ARRAY_SIZE(pxa25x_freqs));
 232 }
 233
 234 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
 235                                     unsigned long parent_rate)
 236 {
 237         int i;
 238
 239         pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
 240         for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
 241                 if (pxa25x_freqs[i].cpll == rate)
 242                         break;
 243
 244         if (i >= ARRAY_SIZE(pxa25x_freqs))
 245                 return -EINVAL;
 246
 247         pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, CCCR);
 248
 249         return 0;
 250 }
 251 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
 252 RATE_OPS(clk_pxa25x_cpll, "cpll");
 253
 254 static void __init pxa25x_register_core(void)
 255 {
 256         clkdev_pxa_register(CLK_NONE, "cpll", NULL,
 257                             clk_register_clk_pxa25x_cpll());
 258         clkdev_pxa_register(CLK_NONE, "run", NULL,
 259                             clk_register_clk_pxa25x_run());
 260         clkdev_pxa_register(CLK_CORE, "core", NULL,
 261                             clk_register_clk_pxa25x_core());
 262 }
 263
 264 static void __init pxa25x_register_plls(void)
 265 {
 266         clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
 267                                 CLK_GET_RATE_NOCACHE, 3686400);
 268         clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
 269                             clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
 270                                                     CLK_GET_RATE_NOCACHE,
 271                                                     32768));
 272         clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
 273         clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
 274                                   0, 26, 1);
 275         clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
 276                                   0, 40, 1);
 277 }
 278
 279 static void __init pxa25x_base_clocks_init(void)
 280 {
 281         pxa25x_register_plls();
 282         pxa25x_register_core();
 283         clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
 284                             clk_register_clk_pxa25x_memory());
 285 }
 286
 287 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
 288         { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
 289 struct dummy_clk {
 290         const char *con_id;
 291         const char *dev_id;
 292         const char *parent;
 293 };
 294 static struct dummy_clk dummy_clks[] __initdata = {
 295         DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
 296         DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
 297         DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
 298         DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
 299         DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
 300         DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
 301         DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
 302 };
 303
 304 static void __init pxa25x_dummy_clocks_init(void)
 305 {
 306         struct clk *clk;
 307         struct dummy_clk *d;
 308         const char *name;
 309         int i;
 310
 311         /*
 312          * All pinctrl logic has been wiped out of the clock driver, especially
 313          * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
 314          * control (ie. pxa2xx_mfp_config() invocation).
 315          */
 316         for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
 317                 d = &dummy_clks[i];
 318                 name = d->dev_id ? d->dev_id : d->con_id;
 319                 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
 320                 clk_register_clkdev(clk, d->con_id, d->dev_id);
 321         }
 322 }
 323
 324 int __init pxa25x_clocks_init(void)
 325 {
 326         pxa25x_base_clocks_init();
 327         pxa25x_dummy_clocks_init();
 328         return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
 329 }
 330
 331 static void __init pxa25x_dt_clocks_init(struct device_node *np)
 332 {
 333         pxa25x_clocks_init();
 334         clk_pxa_dt_common_init(np);
 335 }
 336 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
 337                pxa25x_dt_clocks_init);