drivers/clk/pxa/clk-pxa27x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell PXA27x family clocks
   4  *
   5  * Copyright (C) 2014 Robert Jarzmik
   6  *
   7  * Heavily inspired from former arch/arm/mach-pxa/clock.c.
   8  */
   9 #include <linux/clk-provider.h>
  10 #include <mach/pxa2xx-regs.h>
  11 #include <linux/io.h>
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/of.h>
  15 #include <linux/soc/pxa/smemc.h>
  16
  17 #include <dt-bindings/clock/pxa-clock.h>
  18 #include "clk-pxa.h"
  19
  20 #define KHz 1000
  21 #define MHz (1000 * 1000)
  22
  23 enum {
  24         PXA_CORE_13Mhz = 0,
  25         PXA_CORE_RUN,
  26         PXA_CORE_TURBO,
  27 };
  28
  29 enum {
  30         PXA_BUS_13Mhz = 0,
  31         PXA_BUS_RUN,
  32 };
  33
  34 enum {
  35         PXA_LCD_13Mhz = 0,
  36         PXA_LCD_RUN,
  37 };
  38
  39 enum {
  40         PXA_MEM_13Mhz = 0,
  41         PXA_MEM_SYSTEM_BUS,
  42         PXA_MEM_RUN,
  43 };
  44
  45 #define PXA27x_CLKCFG(B, HT, T)                 \
  46         (CLKCFG_FCS |                           \
  47          ((B)  ? CLKCFG_FASTBUS : 0) |          \
  48          ((HT) ? CLKCFG_HALFTURBO : 0) |        \
  49          ((T)  ? CLKCFG_TURBO : 0))
  50 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
  51
  52 /* Define the refresh period in mSec for the SDRAM and the number of rows */
  53 #define SDRAM_TREF      64      /* standard 64ms SDRAM */
  54
  55 static const char * const get_freq_khz[] = {
  56         "core", "run", "cpll", "memory",
  57         "system_bus"
  58 };
  59
  60 static u32 mdrefr_dri(unsigned int freq_khz)
  61 {
  62         u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
  63
  64         return (interval - 31) / 32;
  65 }
  66
  67 /*
  68  * Get the clock frequency as reflected by CCSR and the turbo flag.
  69  * We assume these values have been applied via a fcs.
  70  * If info is not 0 we also display the current settings.
  71  */
  72 unsigned int pxa27x_get_clk_frequency_khz(int info)
  73 {
  74         struct clk *clk;
  75         unsigned long clks[5];
  76         int i;
  77
  78         for (i = 0; i < 5; i++) {
  79                 clk = clk_get(NULL, get_freq_khz[i]);
  80                 if (IS_ERR(clk)) {
  81                         clks[i] = 0;
  82                 } else {
  83                         clks[i] = clk_get_rate(clk);
  84                         clk_put(clk);
  85                 }
  86         }
  87         if (info) {
  88                 pr_info("Run Mode clock: %ld.%02ldMHz\n",
  89                         clks[1] / 1000000, (clks[1] % 1000000) / 10000);
  90                 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
  91                         clks[2] / 1000000, (clks[2] % 1000000) / 10000);
  92                 pr_info("Memory clock: %ld.%02ldMHz\n",
  93                         clks[3] / 1000000, (clks[3] % 1000000) / 10000);
  94                 pr_info("System bus clock: %ld.%02ldMHz\n",
  95                         clks[4] / 1000000, (clks[4] % 1000000) / 10000);
  96         }
  97         return (unsigned int)clks[0] / KHz;
  98 }
  99
 100 bool pxa27x_is_ppll_disabled(void)
 101 {
 102         unsigned long ccsr = readl(CCSR);
 103
 104         return ccsr & (1 << CCCR_PPDIS_BIT);
 105 }
 106
 107 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp,           \
 108                     bit, is_lp, flags)                                  \
 109         PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp,   \
 110                  is_lp,  CKEN, CKEN_ ## bit, flags)
 111 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)   \
 112         PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp,       \
 113                     div_hp, bit, pxa27x_is_ppll_disabled, 0)
 114
 115 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
 116 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
 117 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
 118 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
 119 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
 120
 121 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay)          \
 122         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
 123                        CKEN, CKEN_ ## bit, 0)
 124 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay)       \
 125         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
 126                        CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
 127
 128 static struct desc_clk_cken pxa27x_clocks[] __initdata = {
 129         PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
 130         PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
 131         PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
 132         PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
 133         PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
 134         PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
 135         PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
 136         PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
 137         PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
 138         PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
 139         PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
 140         PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
 141         PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
 142         PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
 143         PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
 144         PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
 145         PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
 146         PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
 147         PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
 148         PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
 149         PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
 150
 151         PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
 152                           pxa27x_32Mhz_bus_parents, 0),
 153         PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
 154         PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
 155         PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
 156                           pxa27x_lcd_bus_parents, 0),
 157         PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
 158                              pxa27x_membus_parents, 0),
 159
 160 };
 161
 162 /*
 163  * PXA270 definitions
 164  *
 165  * For the PXA27x:
 166  * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
 167  *
 168  * A = 0 => memory controller clock from table 3-7,
 169  * A = 1 => memory controller clock = system bus clock
 170  * Run mode frequency   = 13 MHz * L
 171  * Turbo mode frequency = 13 MHz * L * N
 172  * System bus frequency = 13 MHz * L / (B + 1)
 173  *
 174  * In CCCR:
 175  * A = 1
 176  * L = 16         oscillator to run mode ratio
 177  * 2N = 6         2 * (turbo mode to run mode ratio)
 178  *
 179  * In CCLKCFG:
 180  * B = 1          Fast bus mode
 181  * HT = 0         Half-Turbo mode
 182  * T = 1          Turbo mode
 183  *
 184  * For now, just support some of the combinations in table 3-7 of
 185  * PXA27x Processor Family Developer's Manual to simplify frequency
 186  * change sequences.
 187  */
 188 static struct pxa2xx_freq pxa27x_freqs[] = {
 189         {104000000, 104000, PXA27x_CCCR(1,  8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
 190         {156000000, 104000, PXA27x_CCCR(1,  8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
 191         {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
 192         {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
 193         {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
 194         {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
 195         {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
 196 };
 197
 198 static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
 199         unsigned long parent_rate)
 200 {
 201         unsigned long clkcfg;
 202         unsigned int t, ht;
 203         unsigned int l, L, n2, N;
 204         unsigned long ccsr = readl(CCSR);
 205
 206         asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 207         t  = clkcfg & (1 << 0);
 208         ht = clkcfg & (1 << 2);
 209
 210         l  = ccsr & CCSR_L_MASK;
 211         n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
 212         L  = l * parent_rate;
 213         N  = (L * n2) / 2;
 214
 215         return N;
 216 }
 217
 218 static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
 219                                           struct clk_rate_request *req)
 220 {
 221         return pxa2xx_determine_rate(req, pxa27x_freqs,
 222                                      ARRAY_SIZE(pxa27x_freqs));
 223 }
 224
 225 static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
 226                                     unsigned long parent_rate)
 227 {
 228         int i;
 229
 230         pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
 231         for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
 232                 if (pxa27x_freqs[i].cpll == rate)
 233                         break;
 234
 235         if (i >= ARRAY_SIZE(pxa27x_freqs))
 236                 return -EINVAL;
 237
 238         pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, CCCR);
 239         return 0;
 240 }
 241
 242 PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
 243 RATE_OPS(clk_pxa27x_cpll, "cpll");
 244
 245 static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
 246                                                   unsigned long parent_rate)
 247 {
 248         unsigned int l, osc_forced;
 249         unsigned long ccsr = readl(CCSR);
 250         unsigned long cccr = readl(CCCR);
 251
 252         l  = ccsr & CCSR_L_MASK;
 253         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 254         if (osc_forced) {
 255                 if (cccr & (1 << CCCR_LCD_26_BIT))
 256                         return parent_rate * 2;
 257                 else
 258                         return parent_rate;
 259         }
 260
 261         if (l <= 7)
 262                 return parent_rate;
 263         if (l <= 16)
 264                 return parent_rate / 2;
 265         return parent_rate / 4;
 266 }
 267
 268 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
 269 {
 270         unsigned int osc_forced;
 271         unsigned long ccsr = readl(CCSR);
 272
 273         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 274         if (osc_forced)
 275                 return PXA_LCD_13Mhz;
 276         else
 277                 return PXA_LCD_RUN;
 278 }
 279
 280 PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
 281 MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
 282
 283 static void __init pxa27x_register_plls(void)
 284 {
 285         clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
 286                                 CLK_GET_RATE_NOCACHE,
 287                                 13 * MHz);
 288         clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
 289                             clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
 290                                                     CLK_GET_RATE_NOCACHE,
 291                                                     32768 * KHz));
 292         clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
 293         clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
 294 }
 295
 296 static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
 297 {
 298         unsigned long clkcfg;
 299         unsigned int t, ht, osc_forced;
 300         unsigned long ccsr = readl(CCSR);
 301
 302         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 303         if (osc_forced)
 304                 return PXA_CORE_13Mhz;
 305
 306         asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 307         t  = clkcfg & (1 << 0);
 308         ht = clkcfg & (1 << 2);
 309
 310         if (ht || t)
 311                 return PXA_CORE_TURBO;
 312         return PXA_CORE_RUN;
 313 }
 314
 315 static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
 316 {
 317         if (index > PXA_CORE_TURBO)
 318                 return -EINVAL;
 319
 320         pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
 321
 322         return 0;
 323 }
 324
 325 static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
 326                                           struct clk_rate_request *req)
 327 {
 328         return __clk_mux_determine_rate(hw, req);
 329 }
 330
 331 PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
 332 MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
 333
 334 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
 335                                              unsigned long parent_rate)
 336 {
 337         unsigned long ccsr = readl(CCSR);
 338         unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
 339
 340         return (parent_rate / n2) * 2;
 341 }
 342 PARENTS(clk_pxa27x_run) = { "cpll" };
 343 RATE_RO_OPS(clk_pxa27x_run, "run");
 344
 345 static void __init pxa27x_register_core(void)
 346 {
 347         clkdev_pxa_register(CLK_NONE, "cpll", NULL,
 348                             clk_register_clk_pxa27x_cpll());
 349         clkdev_pxa_register(CLK_NONE, "run", NULL,
 350                             clk_register_clk_pxa27x_run());
 351         clkdev_pxa_register(CLK_CORE, "core", NULL,
 352                             clk_register_clk_pxa27x_core());
 353 }
 354
 355 static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
 356                                                     unsigned long parent_rate)
 357 {
 358         unsigned long clkcfg;
 359         unsigned int b, osc_forced;
 360         unsigned long ccsr = readl(CCSR);
 361
 362         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 363         asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 364         b  = clkcfg & (1 << 3);
 365
 366         if (osc_forced)
 367                 return parent_rate;
 368         if (b)
 369                 return parent_rate;
 370         else
 371                 return parent_rate / 2;
 372 }
 373
 374 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
 375 {
 376         unsigned int osc_forced;
 377         unsigned long ccsr = readl(CCSR);
 378
 379         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 380         if (osc_forced)
 381                 return PXA_BUS_13Mhz;
 382         else
 383                 return PXA_BUS_RUN;
 384 }
 385
 386 PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
 387 MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
 388
 389 static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
 390                                                 unsigned long parent_rate)
 391 {
 392         unsigned int a, l, osc_forced;
 393         unsigned long cccr = readl(CCCR);
 394         unsigned long ccsr = readl(CCSR);
 395
 396         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 397         a = cccr & (1 << CCCR_A_BIT);
 398         l  = ccsr & CCSR_L_MASK;
 399
 400         if (osc_forced || a)
 401                 return parent_rate;
 402         if (l <= 10)
 403                 return parent_rate;
 404         if (l <= 20)
 405                 return parent_rate / 2;
 406         return parent_rate / 4;
 407 }
 408
 409 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
 410 {
 411         unsigned int osc_forced, a;
 412         unsigned long cccr = readl(CCCR);
 413         unsigned long ccsr = readl(CCSR);
 414
 415         osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
 416         a = cccr & (1 << CCCR_A_BIT);
 417         if (osc_forced)
 418                 return PXA_MEM_13Mhz;
 419         if (a)
 420                 return PXA_MEM_SYSTEM_BUS;
 421         else
 422                 return PXA_MEM_RUN;
 423 }
 424
 425 PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
 426 MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
 427
 428 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
 429         { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
 430 struct dummy_clk {
 431         const char *con_id;
 432         const char *dev_id;
 433         const char *parent;
 434 };
 435 static struct dummy_clk dummy_clks[] __initdata = {
 436         DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
 437         DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
 438         DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
 439         DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
 440 };
 441
 442 static void __init pxa27x_dummy_clocks_init(void)
 443 {
 444         struct clk *clk;
 445         struct dummy_clk *d;
 446         const char *name;
 447         int i;
 448
 449         for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
 450                 d = &dummy_clks[i];
 451                 name = d->dev_id ? d->dev_id : d->con_id;
 452                 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
 453                 clk_register_clkdev(clk, d->con_id, d->dev_id);
 454         }
 455 }
 456
 457 static void __init pxa27x_base_clocks_init(void)
 458 {
 459         pxa27x_register_plls();
 460         pxa27x_register_core();
 461         clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
 462                             clk_register_clk_pxa27x_system_bus());
 463         clkdev_pxa_register(CLK_NONE, "memory", NULL,
 464                             clk_register_clk_pxa27x_memory());
 465         clk_register_clk_pxa27x_lcd_base();
 466 }
 467
 468 int __init pxa27x_clocks_init(void)
 469 {
 470         pxa27x_base_clocks_init();
 471         pxa27x_dummy_clocks_init();
 472         return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
 473 }
 474
 475 static void __init pxa27x_dt_clocks_init(struct device_node *np)
 476 {
 477         pxa27x_clocks_init();
 478         clk_pxa_dt_common_init(np);
 479 }
 480 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);