drivers/clk/pxa/clk-pxa3xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell PXA3xxx family clocks
   4  *
   5  * Copyright (C) 2014 Robert Jarzmik
   6  *
   7  * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
   8  *
   9  * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
  10  * should go away.
  11  */
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/of.h>
  17 #include <linux/soc/pxa/cpu.h>
  18 #include <linux/soc/pxa/smemc.h>
  19 #include <linux/clk/pxa.h>
  20 #include <mach/pxa3xx-regs.h>
  21
  22 #include <dt-bindings/clock/pxa-clock.h>
  23 #include "clk-pxa.h"
  24
  25 #define KHz 1000
  26 #define MHz (1000 * 1000)
  27
  28 enum {
  29         PXA_CORE_60Mhz = 0,
  30         PXA_CORE_RUN,
  31         PXA_CORE_TURBO,
  32 };
  33
  34 enum {
  35         PXA_BUS_60Mhz = 0,
  36         PXA_BUS_HSS,
  37 };
  38
  39 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  40 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
  41
  42 /* crystal frequency to static memory controller multiplier (SMCFS) */
  43 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  44 static const char * const get_freq_khz[] = {
  45         "core", "ring_osc_60mhz", "run", "cpll", "system_bus"
  46 };
  47
  48 /*
  49  * Get the clock frequency as reflected by ACSR and the turbo flag.
  50  * We assume these values have been applied via a fcs.
  51  * If info is not 0 we also display the current settings.
  52  */
  53 unsigned int pxa3xx_get_clk_frequency_khz(int info)
  54 {
  55         struct clk *clk;
  56         unsigned long clks[5];
  57         int i;
  58
  59         for (i = 0; i < 5; i++) {
  60                 clk = clk_get(NULL, get_freq_khz[i]);
  61                 if (IS_ERR(clk)) {
  62                         clks[i] = 0;
  63                 } else {
  64                         clks[i] = clk_get_rate(clk);
  65                         clk_put(clk);
  66                 }
  67         }
  68         if (info) {
  69                 pr_info("RO Mode clock: %ld.%02ldMHz\n",
  70                         clks[1] / 1000000, (clks[0] % 1000000) / 10000);
  71                 pr_info("Run Mode clock: %ld.%02ldMHz\n",
  72                         clks[2] / 1000000, (clks[1] % 1000000) / 10000);
  73                 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
  74                         clks[3] / 1000000, (clks[2] % 1000000) / 10000);
  75                 pr_info("System bus clock: %ld.%02ldMHz\n",
  76                         clks[4] / 1000000, (clks[4] % 1000000) / 10000);
  77         }
  78         return (unsigned int)clks[0] / KHz;
  79 }
  80
  81 void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask)
  82 {
  83         u32 accr = ACCR;
  84
  85         accr &= ~disable;
  86         accr |= enable;
  87
  88         ACCR = accr;
  89         if (xclkcfg)
  90                 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
  91
  92         while ((ACSR & mask) != (accr & mask))
  93                 cpu_relax();
  94 }
  95
  96 static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
  97                                              unsigned long parent_rate)
  98 {
  99         unsigned long ac97_div, rate;
 100
 101         ac97_div = AC97_DIV;
 102
 103         /* This may loose precision for some rates but won't for the
 104          * standard 24.576MHz.
 105          */
 106         rate = parent_rate / 2;
 107         rate /= ((ac97_div >> 12) & 0x7fff);
 108         rate *= (ac97_div & 0xfff);
 109
 110         return rate;
 111 }
 112 PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
 113 RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
 114
 115 static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
 116                                               unsigned long parent_rate)
 117 {
 118         unsigned long acsr = ACSR;
 119
 120         return (parent_rate / 48)  * smcfs_mult[(acsr >> 23) & 0x7] /
 121                 pxa3xx_smemc_get_memclkdiv();
 122
 123 }
 124 PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
 125 RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
 126
 127 static bool pxa3xx_is_ring_osc_forced(void)
 128 {
 129         unsigned long acsr = ACSR;
 130
 131         return acsr & ACCR_D0CS;
 132 }
 133
 134 PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
 135 PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
 136 PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
 137 PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
 138 PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
 139 PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
 140
 141 #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
 142 #define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp,  \
 143                     div_hp, bit, is_lp, flags)                          \
 144         PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp,         \
 145                  mult_hp, div_hp, is_lp,  CKEN_AB(bit),                 \
 146                  (CKEN_ ## bit % 32), flags)
 147 #define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp,          \
 148                          mult_hp, div_hp, delay)                        \
 149         PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp,       \
 150                     div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
 151 #define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents)                 \
 152         PXA_CKEN_1RATE(dev_id, con_id, bit, parents,                    \
 153                        CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
 154
 155 static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
 156         PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
 157         PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
 158         PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
 159         PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
 160         PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
 161         PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
 162         PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
 163         PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
 164         PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
 165         PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
 166         PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
 167         PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
 168
 169         PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
 170                           pxa3xx_32Khz_bus_parents),
 171         PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
 172         PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
 173         PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
 174         PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
 175
 176         PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
 177                     pxa3xx_is_ring_osc_forced, 0),
 178         PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
 179                     pxa3xx_is_ring_osc_forced, 0),
 180         PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
 181                     pxa3xx_is_ring_osc_forced, 0),
 182         PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
 183                     1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
 184 };
 185
 186 static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
 187
 188         PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
 189         PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
 190         PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
 191 };
 192
 193 static struct desc_clk_cken pxa320_clocks[] __initdata = {
 194         PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
 195         PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
 196         PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
 197 };
 198
 199 static struct desc_clk_cken pxa93x_clocks[] __initdata = {
 200
 201         PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
 202         PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
 203         PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
 204 };
 205
 206 static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
 207                                             unsigned long parent_rate)
 208 {
 209         unsigned long acsr = ACSR;
 210         unsigned int hss = (acsr >> 14) & 0x3;
 211
 212         if (pxa3xx_is_ring_osc_forced())
 213                 return parent_rate;
 214         return parent_rate / 48 * hss_mult[hss];
 215 }
 216
 217 static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
 218 {
 219         if (pxa3xx_is_ring_osc_forced())
 220                 return PXA_BUS_60Mhz;
 221         else
 222                 return PXA_BUS_HSS;
 223 }
 224
 225 PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
 226 MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
 227
 228 static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
 229                                               unsigned long parent_rate)
 230 {
 231         return parent_rate;
 232 }
 233
 234 static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
 235 {
 236         unsigned long xclkcfg;
 237         unsigned int t;
 238
 239         if (pxa3xx_is_ring_osc_forced())
 240                 return PXA_CORE_60Mhz;
 241
 242         /* Read XCLKCFG register turbo bit */
 243         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
 244         t = xclkcfg & 0x1;
 245
 246         if (t)
 247                 return PXA_CORE_TURBO;
 248         return PXA_CORE_RUN;
 249 }
 250 PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
 251 MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
 252
 253 static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
 254                                              unsigned long parent_rate)
 255 {
 256         unsigned long acsr = ACSR;
 257         unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
 258         unsigned int t, xclkcfg;
 259
 260         /* Read XCLKCFG register turbo bit */
 261         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
 262         t = xclkcfg & 0x1;
 263
 264         return t ? (parent_rate / xn) * 2 : parent_rate;
 265 }
 266 PARENTS(clk_pxa3xx_run) = { "cpll" };
 267 RATE_RO_OPS(clk_pxa3xx_run, "run");
 268
 269 static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
 270         unsigned long parent_rate)
 271 {
 272         unsigned long acsr = ACSR;
 273         unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
 274         unsigned int xl = acsr & ACCR_XL_MASK;
 275         unsigned int t, xclkcfg;
 276
 277         /* Read XCLKCFG register turbo bit */
 278         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
 279         t = xclkcfg & 0x1;
 280
 281         pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
 282         return t ? parent_rate * xl * xn : parent_rate * xl;
 283 }
 284 PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
 285 RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
 286
 287 static void __init pxa3xx_register_core(void)
 288 {
 289         clk_register_clk_pxa3xx_cpll();
 290         clk_register_clk_pxa3xx_run();
 291
 292         clkdev_pxa_register(CLK_CORE, "core", NULL,
 293                             clk_register_clk_pxa3xx_core());
 294 }
 295
 296 static void __init pxa3xx_register_plls(void)
 297 {
 298         clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
 299                                 CLK_GET_RATE_NOCACHE,
 300                                 13 * MHz);
 301         clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
 302                             clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
 303                                                     CLK_GET_RATE_NOCACHE,
 304                                                     32768));
 305         clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
 306                                 CLK_GET_RATE_NOCACHE,
 307                                 120 * MHz);
 308         clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
 309         clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
 310         clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
 311                                   0, 1, 2);
 312 }
 313
 314 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
 315         { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
 316 struct dummy_clk {
 317         const char *con_id;
 318         const char *dev_id;
 319         const char *parent;
 320 };
 321 static struct dummy_clk dummy_clks[] __initdata = {
 322         DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
 323         DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
 324         DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
 325         DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
 326 };
 327
 328 static void __init pxa3xx_dummy_clocks_init(void)
 329 {
 330         struct clk *clk;
 331         struct dummy_clk *d;
 332         const char *name;
 333         int i;
 334
 335         for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
 336                 d = &dummy_clks[i];
 337                 name = d->dev_id ? d->dev_id : d->con_id;
 338                 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
 339                 clk_register_clkdev(clk, d->con_id, d->dev_id);
 340         }
 341 }
 342
 343 static void __init pxa3xx_base_clocks_init(void)
 344 {
 345         struct clk *clk;
 346
 347         pxa3xx_register_plls();
 348         pxa3xx_register_core();
 349         clk_register_clk_pxa3xx_system_bus();
 350         clk_register_clk_pxa3xx_ac97();
 351         clk_register_clk_pxa3xx_smemc();
 352         clk = clk_register_gate(NULL, "CLK_POUT",
 353                                 "osc_13mhz", 0, OSCC, 11, 0, NULL);
 354         clk_register_clkdev(clk, "CLK_POUT", NULL);
 355         clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
 356                             clk_register_fixed_factor(NULL, "os-timer0",
 357                                                       "osc_13mhz", 0, 1, 4));
 358 }
 359
 360 int __init pxa3xx_clocks_init(void)
 361 {
 362         int ret;
 363
 364         pxa3xx_base_clocks_init();
 365         pxa3xx_dummy_clocks_init();
 366         ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks));
 367         if (ret)
 368                 return ret;
 369         if (cpu_is_pxa320())
 370                 return clk_pxa_cken_init(pxa320_clocks,
 371                                          ARRAY_SIZE(pxa320_clocks));
 372         if (cpu_is_pxa300() || cpu_is_pxa310())
 373                 return clk_pxa_cken_init(pxa300_310_clocks,
 374                                          ARRAY_SIZE(pxa300_310_clocks));
 375         return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks));
 376 }
 377
 378 static void __init pxa3xx_dt_clocks_init(struct device_node *np)
 379 {
 380         pxa3xx_clocks_init();
 381         clk_pxa_dt_common_init(np);
 382 }
 383 CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);