2 * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <clk-uclass.h>
21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
24 #define CPG_RST_MODEMR 0x0060
26 #define CPG_PLL0CR 0x00d8
27 #define CPG_PLL2CR 0x002c
28 #define CPG_PLL4CR 0x01f4
30 #define CPG_RPC_PREDIV_MASK 0x3
31 #define CPG_RPC_PREDIV_OFFSET 3
32 #define CPG_RPC_POSTDIV_MASK 0x7
33 #define CPG_RPC_POSTDIV_OFFSET 0
36 * Module Standby and Software Reset register offets.
38 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
39 * R-Car Gen2, R-Car Gen3, and RZ/G1.
40 * These are NOT valid for R-Car Gen1 and RZ/A1!
44 * Module Stop Status Register offsets
47 static const u16 mstpsr
[] = {
48 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
49 0x9A0, 0x9A4, 0x9A8, 0x9AC,
52 #define MSTPSR(i) mstpsr[i]
56 * System Module Stop Control Register offsets
59 static const u16 smstpcr
[] = {
60 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
61 0x990, 0x994, 0x998, 0x99C,
64 #define SMSTPCR(i) smstpcr[i]
67 /* Realtime Module Stop Control Register offsets */
68 #define RMSTPCR(i) (smstpcr[i] - 0x20)
70 /* Modem Module Stop Control Register offsets (r8a73a4) */
71 #define MMSTPCR(i) (smstpcr[i] + 0x20)
73 /* Software Reset Clearing Register offsets */
74 #define SRSTCLR(i) (0x940 + (i) * 4)
76 struct gen3_clk_priv
{
79 struct clk clk_extalr
;
80 const struct rcar_gen3_cpg_pll_config
*cpg_pll_config
;
81 const struct cpg_core_clk
*core_clk
;
83 const struct mssr_mod_clk
*mod_clk
;
88 * Definitions of CPG Core Clocks
91 * - Clock outputs exported to DT
92 * - External input clocks
93 * - Internal CPG clocks
100 /* Depending on type */
101 unsigned int parent
; /* Core Clocks only */
109 CLK_TYPE_IN
, /* External Clock Input */
110 CLK_TYPE_FF
, /* Fixed Factor Clock */
112 /* Custom definitions start here */
116 #define DEF_TYPE(_name, _id, _type...) \
117 { .name = _name, .id = _id, .type = _type }
118 #define DEF_BASE(_name, _id, _type, _parent...) \
119 DEF_TYPE(_name, _id, _type, .parent = _parent)
121 #define DEF_INPUT(_name, _id) \
122 DEF_TYPE(_name, _id, CLK_TYPE_IN)
123 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
124 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
125 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
126 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
127 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
128 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
131 * Definitions of Module Clocks
133 struct mssr_mod_clk
{
136 unsigned int parent
; /* Add MOD_CLK_BASE for Module Clocks */
139 /* Convert from sparse base-100 to packed index space */
140 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
142 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
144 #define DEF_MOD(_name, _mod, _parent...) \
145 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
147 enum rcar_gen3_clk_types
{
148 CLK_TYPE_GEN3_MAIN
= CLK_TYPE_CUSTOM
,
159 struct rcar_gen3_cpg_pll_config
{
160 unsigned int extal_div
;
161 unsigned int pll1_mult
;
162 unsigned int pll3_mult
;
166 /* Core Clock Outputs exported to DT */
167 LAST_DT_CORE_CLK
= R8A7796_CLK_OSC
,
169 /* External Input Clocks */
173 /* Internal Core Clocks */
195 static const struct cpg_core_clk r8a7795_core_clks
[] = {
196 /* External Clock Inputs */
197 DEF_INPUT("extal", CLK_EXTAL
),
198 DEF_INPUT("extalr", CLK_EXTALR
),
200 /* Internal Core Clocks */
201 DEF_BASE(".main", CLK_MAIN
, CLK_TYPE_GEN3_MAIN
, CLK_EXTAL
),
202 DEF_BASE(".pll0", CLK_PLL0
, CLK_TYPE_GEN3_PLL0
, CLK_MAIN
),
203 DEF_BASE(".pll1", CLK_PLL1
, CLK_TYPE_GEN3_PLL1
, CLK_MAIN
),
204 DEF_BASE(".pll2", CLK_PLL2
, CLK_TYPE_GEN3_PLL2
, CLK_MAIN
),
205 DEF_BASE(".pll3", CLK_PLL3
, CLK_TYPE_GEN3_PLL3
, CLK_MAIN
),
206 DEF_BASE(".pll4", CLK_PLL4
, CLK_TYPE_GEN3_PLL4
, CLK_MAIN
),
208 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2
, CLK_PLL1
, 2, 1),
209 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4
, CLK_PLL1_DIV2
, 2, 1),
210 DEF_FIXED(".s0", CLK_S0
, CLK_PLL1_DIV2
, 2, 1),
211 DEF_FIXED(".s1", CLK_S1
, CLK_PLL1_DIV2
, 3, 1),
212 DEF_FIXED(".s2", CLK_S2
, CLK_PLL1_DIV2
, 4, 1),
213 DEF_FIXED(".s3", CLK_S3
, CLK_PLL1_DIV2
, 6, 1),
214 DEF_FIXED(".sdsrc", CLK_SDSRC
, CLK_PLL1_DIV2
, 2, 1),
215 DEF_FIXED(".rpcsrc", CLK_RPCSRC
, CLK_PLL1
, 2, 1),
217 /* Core Clock Outputs */
218 DEF_FIXED("ztr", R8A7795_CLK_ZTR
, CLK_PLL1_DIV2
, 6, 1),
219 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2
, CLK_PLL1_DIV2
, 12, 1),
220 DEF_FIXED("zt", R8A7795_CLK_ZT
, CLK_PLL1_DIV2
, 4, 1),
221 DEF_FIXED("zx", R8A7795_CLK_ZX
, CLK_PLL1_DIV2
, 2, 1),
222 DEF_FIXED("s0d1", R8A7795_CLK_S0D1
, CLK_S0
, 1, 1),
223 DEF_FIXED("s0d2", R8A7795_CLK_S0D2
, CLK_S0
, 2, 1),
224 DEF_FIXED("s0d3", R8A7795_CLK_S0D3
, CLK_S0
, 3, 1),
225 DEF_FIXED("s0d4", R8A7795_CLK_S0D4
, CLK_S0
, 4, 1),
226 DEF_FIXED("s0d6", R8A7795_CLK_S0D6
, CLK_S0
, 6, 1),
227 DEF_FIXED("s0d8", R8A7795_CLK_S0D8
, CLK_S0
, 8, 1),
228 DEF_FIXED("s0d12", R8A7795_CLK_S0D12
, CLK_S0
, 12, 1),
229 DEF_FIXED("s1d1", R8A7795_CLK_S1D1
, CLK_S1
, 1, 1),
230 DEF_FIXED("s1d2", R8A7795_CLK_S1D2
, CLK_S1
, 2, 1),
231 DEF_FIXED("s1d4", R8A7795_CLK_S1D4
, CLK_S1
, 4, 1),
232 DEF_FIXED("s2d1", R8A7795_CLK_S2D1
, CLK_S2
, 1, 1),
233 DEF_FIXED("s2d2", R8A7795_CLK_S2D2
, CLK_S2
, 2, 1),
234 DEF_FIXED("s2d4", R8A7795_CLK_S2D4
, CLK_S2
, 4, 1),
235 DEF_FIXED("s3d1", R8A7795_CLK_S3D1
, CLK_S3
, 1, 1),
236 DEF_FIXED("s3d2", R8A7795_CLK_S3D2
, CLK_S3
, 2, 1),
237 DEF_FIXED("s3d4", R8A7795_CLK_S3D4
, CLK_S3
, 4, 1),
239 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0
, CLK_SDSRC
, 0x074),
240 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1
, CLK_SDSRC
, 0x078),
241 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2
, CLK_SDSRC
, 0x268),
242 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3
, CLK_SDSRC
, 0x26c),
244 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC
, CLK_RPCSRC
, 0x238),
246 DEF_FIXED("cl", R8A7795_CLK_CL
, CLK_PLL1_DIV2
, 48, 1),
247 DEF_FIXED("cp", R8A7795_CLK_CP
, CLK_EXTAL
, 2, 1),
249 /* NOTE: HDMI, CSI, CAN etc. clock are missing */
251 DEF_BASE("r", R8A7795_CLK_R
, CLK_TYPE_GEN3_R
, CLK_RINT
),
254 static const struct mssr_mod_clk r8a7795_mod_clks
[] = {
255 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1
), /* ES1.x */
256 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1
),
257 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1
),
258 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4
),
259 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4
),
260 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4
),
261 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4
),
262 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4
),
263 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO
),
264 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO
),
265 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO
),
266 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO
),
267 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3
),
268 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3
),
269 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3
),
270 DEF_MOD("cmt3", 300, R8A7795_CLK_R
),
271 DEF_MOD("cmt2", 301, R8A7795_CLK_R
),
272 DEF_MOD("cmt1", 302, R8A7795_CLK_R
),
273 DEF_MOD("cmt0", 303, R8A7795_CLK_R
),
274 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4
),
275 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3
),
276 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2
),
277 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1
),
278 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0
),
279 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1
),
280 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1
),
281 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1
),
282 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1
), /* ES1.x */
283 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1
),
284 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1
),
285 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1
),
286 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1
),
287 DEF_MOD("rwdt", 402, R8A7795_CLK_R
),
288 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP
),
289 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1
),
290 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3
),
291 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3
),
292 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2
),
293 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2
),
294 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2
),
295 DEF_MOD("drif4", 511, R8A7795_CLK_S3D2
),
296 DEF_MOD("drif3", 512, R8A7795_CLK_S3D2
),
297 DEF_MOD("drif2", 513, R8A7795_CLK_S3D2
),
298 DEF_MOD("drif1", 514, R8A7795_CLK_S3D2
),
299 DEF_MOD("drif0", 515, R8A7795_CLK_S3D2
),
300 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1
),
301 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1
),
302 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1
),
303 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1
),
304 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1
),
305 DEF_MOD("thermal", 522, R8A7795_CLK_CP
),
306 DEF_MOD("pwm", 523, R8A7795_CLK_S0D12
),
307 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1
), /* ES1.x */
308 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2
),
309 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2
),
310 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2
),
311 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1
),
312 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1
),
313 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1
), /* ES1.x */
314 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1
),
315 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1
),
316 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1
), /* ES1.x */
317 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1
),
318 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1
),
319 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1
), /* ES1.x */
320 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1
), /* ES1.x */
321 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1
),
322 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1
), /* ES1.x */
323 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2
),
324 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2
),
325 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2
),
326 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1
),
327 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1
),
328 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1
), /* ES1.x */
329 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1
),
330 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1
),
331 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4
),
332 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4
),
333 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4
),
334 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4
),
335 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4
),
336 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4
),
337 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0
), /* ES1.x */
338 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0
),
339 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0
),
340 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0
),
341 DEF_MOD("du3", 721, R8A7795_CLK_S2D1
),
342 DEF_MOD("du2", 722, R8A7795_CLK_S2D1
),
343 DEF_MOD("du1", 723, R8A7795_CLK_S2D1
),
344 DEF_MOD("du0", 724, R8A7795_CLK_S2D1
),
345 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4
),
346 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI
),
347 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI
),
348 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2
),
349 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2
),
350 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2
),
351 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2
),
352 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2
),
353 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2
),
354 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2
),
355 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2
),
356 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6
),
357 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2
),
358 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2
),
359 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2
),
360 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2
),
361 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2
),
362 DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4
),
363 DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4
),
364 DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4
),
365 DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4
),
366 DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4
),
367 DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4
),
368 DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4
),
369 DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4
),
370 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2
),
371 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4
),
372 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4
),
373 DEF_MOD("rpc", 917, R8A7795_CLK_RPC
),
374 DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6
),
375 DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6
),
376 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP
),
377 DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6
),
378 DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6
),
379 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2
),
380 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2
),
381 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2
),
382 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4
),
383 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
384 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
385 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
386 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
387 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
388 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
389 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
390 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
391 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
392 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
393 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4
),
394 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
395 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
396 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
397 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
398 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
399 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
400 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
401 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
402 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
403 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
404 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
405 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
406 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
407 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
410 static const struct cpg_core_clk r8a7796_core_clks
[] = {
411 /* External Clock Inputs */
412 DEF_INPUT("extal", CLK_EXTAL
),
413 DEF_INPUT("extalr", CLK_EXTALR
),
415 /* Internal Core Clocks */
416 DEF_BASE(".main", CLK_MAIN
, CLK_TYPE_GEN3_MAIN
, CLK_EXTAL
),
417 DEF_BASE(".pll0", CLK_PLL0
, CLK_TYPE_GEN3_PLL0
, CLK_MAIN
),
418 DEF_BASE(".pll1", CLK_PLL1
, CLK_TYPE_GEN3_PLL1
, CLK_MAIN
),
419 DEF_BASE(".pll2", CLK_PLL2
, CLK_TYPE_GEN3_PLL2
, CLK_MAIN
),
420 DEF_BASE(".pll3", CLK_PLL3
, CLK_TYPE_GEN3_PLL3
, CLK_MAIN
),
421 DEF_BASE(".pll4", CLK_PLL4
, CLK_TYPE_GEN3_PLL4
, CLK_MAIN
),
423 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2
, CLK_PLL1
, 2, 1),
424 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4
, CLK_PLL1_DIV2
, 2, 1),
425 DEF_FIXED(".s0", CLK_S0
, CLK_PLL1_DIV2
, 2, 1),
426 DEF_FIXED(".s1", CLK_S1
, CLK_PLL1_DIV2
, 3, 1),
427 DEF_FIXED(".s2", CLK_S2
, CLK_PLL1_DIV2
, 4, 1),
428 DEF_FIXED(".s3", CLK_S3
, CLK_PLL1_DIV2
, 6, 1),
429 DEF_FIXED(".sdsrc", CLK_SDSRC
, CLK_PLL1_DIV2
, 2, 1),
430 DEF_FIXED(".rpcsrc", CLK_RPCSRC
, CLK_PLL1
, 2, 1),
432 /* Core Clock Outputs */
433 DEF_FIXED("ztr", R8A7796_CLK_ZTR
, CLK_PLL1_DIV2
, 6, 1),
434 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2
, CLK_PLL1_DIV2
, 12, 1),
435 DEF_FIXED("zt", R8A7796_CLK_ZT
, CLK_PLL1_DIV2
, 4, 1),
436 DEF_FIXED("zx", R8A7796_CLK_ZX
, CLK_PLL1_DIV2
, 2, 1),
437 DEF_FIXED("s0d1", R8A7796_CLK_S0D1
, CLK_S0
, 1, 1),
438 DEF_FIXED("s0d2", R8A7796_CLK_S0D2
, CLK_S0
, 2, 1),
439 DEF_FIXED("s0d3", R8A7796_CLK_S0D3
, CLK_S0
, 3, 1),
440 DEF_FIXED("s0d4", R8A7796_CLK_S0D4
, CLK_S0
, 4, 1),
441 DEF_FIXED("s0d6", R8A7796_CLK_S0D6
, CLK_S0
, 6, 1),
442 DEF_FIXED("s0d8", R8A7796_CLK_S0D8
, CLK_S0
, 8, 1),
443 DEF_FIXED("s0d12", R8A7796_CLK_S0D12
, CLK_S0
, 12, 1),
444 DEF_FIXED("s1d1", R8A7796_CLK_S1D1
, CLK_S1
, 1, 1),
445 DEF_FIXED("s1d2", R8A7796_CLK_S1D2
, CLK_S1
, 2, 1),
446 DEF_FIXED("s1d4", R8A7796_CLK_S1D4
, CLK_S1
, 4, 1),
447 DEF_FIXED("s2d1", R8A7796_CLK_S2D1
, CLK_S2
, 1, 1),
448 DEF_FIXED("s2d2", R8A7796_CLK_S2D2
, CLK_S2
, 2, 1),
449 DEF_FIXED("s2d4", R8A7796_CLK_S2D4
, CLK_S2
, 4, 1),
450 DEF_FIXED("s3d1", R8A7796_CLK_S3D1
, CLK_S3
, 1, 1),
451 DEF_FIXED("s3d2", R8A7796_CLK_S3D2
, CLK_S3
, 2, 1),
452 DEF_FIXED("s3d4", R8A7796_CLK_S3D4
, CLK_S3
, 4, 1),
454 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0
, CLK_SDSRC
, 0x074),
455 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1
, CLK_SDSRC
, 0x078),
456 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2
, CLK_SDSRC
, 0x268),
457 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3
, CLK_SDSRC
, 0x26c),
459 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC
, CLK_RPCSRC
, 0x238),
461 DEF_FIXED("cl", R8A7796_CLK_CL
, CLK_PLL1_DIV2
, 48, 1),
462 DEF_FIXED("cp", R8A7796_CLK_CP
, CLK_EXTAL
, 2, 1),
464 /* NOTE: HDMI, CSI, CAN etc. clock are missing */
466 DEF_BASE("r", R8A7796_CLK_R
, CLK_TYPE_GEN3_R
, CLK_RINT
),
469 static const struct mssr_mod_clk r8a7796_mod_clks
[] = {
470 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4
),
471 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4
),
472 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4
),
473 DEF_MOD("scif1", 206, R8A7796_CLK_S3D4
),
474 DEF_MOD("scif0", 207, R8A7796_CLK_S3D4
),
475 DEF_MOD("msiof3", 208, R8A7796_CLK_MSO
),
476 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO
),
477 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO
),
478 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO
),
479 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3
),
480 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3
),
481 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3
),
482 DEF_MOD("cmt3", 300, R8A7796_CLK_R
),
483 DEF_MOD("cmt2", 301, R8A7796_CLK_R
),
484 DEF_MOD("cmt1", 302, R8A7796_CLK_R
),
485 DEF_MOD("cmt0", 303, R8A7796_CLK_R
),
486 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4
),
487 DEF_MOD("sdif3", 311, R8A7796_CLK_SD3
),
488 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2
),
489 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1
),
490 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0
),
491 DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1
),
492 DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1
),
493 DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1
),
494 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1
),
495 DEF_MOD("rwdt", 402, R8A7796_CLK_R
),
496 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP
),
497 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1
),
498 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3
),
499 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3
),
500 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2
),
501 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2
),
502 DEF_MOD("drif5", 510, R8A7796_CLK_S3D2
),
503 DEF_MOD("drif4", 511, R8A7796_CLK_S3D2
),
504 DEF_MOD("drif3", 512, R8A7796_CLK_S3D2
),
505 DEF_MOD("drif2", 513, R8A7796_CLK_S3D2
),
506 DEF_MOD("drif1", 514, R8A7796_CLK_S3D2
),
507 DEF_MOD("drif0", 515, R8A7796_CLK_S3D2
),
508 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1
),
509 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1
),
510 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1
),
511 DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1
),
512 DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1
),
513 DEF_MOD("thermal", 522, R8A7796_CLK_CP
),
514 DEF_MOD("pwm", 523, R8A7796_CLK_S0D12
),
515 DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2
),
516 DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2
),
517 DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2
),
518 DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1
),
519 DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1
),
520 DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1
),
521 DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2
),
522 DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2
),
523 DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2
),
524 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2
),
525 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2
),
526 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1
),
527 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1
),
528 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4
),
529 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4
),
530 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4
),
531 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0
),
532 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0
),
533 DEF_MOD("du2", 722, R8A7796_CLK_S2D1
),
534 DEF_MOD("du1", 723, R8A7796_CLK_S2D1
),
535 DEF_MOD("du0", 724, R8A7796_CLK_S2D1
),
536 DEF_MOD("lvds", 727, R8A7796_CLK_S2D1
),
537 DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI
),
538 DEF_MOD("vin7", 804, R8A7796_CLK_S0D2
),
539 DEF_MOD("vin6", 805, R8A7796_CLK_S0D2
),
540 DEF_MOD("vin5", 806, R8A7796_CLK_S0D2
),
541 DEF_MOD("vin4", 807, R8A7796_CLK_S0D2
),
542 DEF_MOD("vin3", 808, R8A7796_CLK_S0D2
),
543 DEF_MOD("vin2", 809, R8A7796_CLK_S0D2
),
544 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2
),
545 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2
),
546 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6
),
547 DEF_MOD("imr1", 822, R8A7796_CLK_S0D2
),
548 DEF_MOD("imr0", 823, R8A7796_CLK_S0D2
),
549 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4
),
550 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4
),
551 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4
),
552 DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4
),
553 DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4
),
554 DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4
),
555 DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4
),
556 DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4
),
557 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2
),
558 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4
),
559 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4
),
560 DEF_MOD("rpc", 917, R8A7795_CLK_RPC
),
561 DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6
),
562 DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6
),
563 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP
),
564 DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6
),
565 DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6
),
566 DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2
),
567 DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2
),
568 DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2
),
569 DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4
),
570 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
571 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
572 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
573 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
574 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
575 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
576 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
577 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
578 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
579 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
580 DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4
),
581 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
582 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
583 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
584 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
585 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
586 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
587 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
588 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
589 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
590 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
591 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
592 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
593 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
594 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
602 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
604 *-------------------------------------------------------------------
605 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
606 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
607 * 0 0 1 0 Prohibited setting
608 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
609 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
610 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
611 * 0 1 1 0 Prohibited setting
612 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
613 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
614 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
615 * 1 0 1 0 Prohibited setting
616 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
617 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
618 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
619 * 1 1 1 0 Prohibited setting
620 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
622 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
623 (((md) & BIT(13)) >> 11) | \
624 (((md) & BIT(19)) >> 18) | \
625 (((md) & BIT(17)) >> 17))
627 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs
[16] = {
628 /* EXTAL div PLL1 mult PLL3 mult */
631 { 0, /* Prohibited setting */ },
635 { 0, /* Prohibited setting */ },
639 { 0, /* Prohibited setting */ },
643 { 0, /* Prohibited setting */ },
650 #define CPG_SD_STP_HCK BIT(9)
651 #define CPG_SD_STP_CK BIT(8)
653 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
654 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
656 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
658 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
659 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
660 ((sd_srcfc) << 2) | \
665 struct sd_div_table
{
672 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
673 *-------------------------------------------------------------------
678 * 1 0 4 (16) 1 (4) 64
683 * 1 0 4 (16) 0 (2) 32
685 static const struct sd_div_table cpg_sd_div_table
[] = {
686 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
687 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
688 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
689 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
690 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
691 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
692 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
693 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
694 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
695 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
696 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
699 static bool gen3_clk_is_mod(struct clk
*clk
)
701 return (clk
->id
>> 16) == CPG_MOD
;
704 static int gen3_clk_get_mod(struct clk
*clk
, const struct mssr_mod_clk
**mssr
)
706 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
707 const unsigned long clkid
= clk
->id
& 0xffff;
710 if (!gen3_clk_is_mod(clk
))
713 for (i
= 0; i
< priv
->mod_clk_size
; i
++) {
714 if (priv
->mod_clk
[i
].id
!= MOD_CLK_ID(clkid
))
717 *mssr
= &priv
->mod_clk
[i
];
724 static int gen3_clk_get_core(struct clk
*clk
, const struct cpg_core_clk
**core
)
726 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
727 const unsigned long clkid
= clk
->id
& 0xffff;
730 if (gen3_clk_is_mod(clk
))
733 for (i
= 0; i
< priv
->core_clk_size
; i
++) {
734 if (priv
->core_clk
[i
].id
!= clkid
)
737 *core
= &priv
->core_clk
[i
];
744 static int gen3_clk_get_parent(struct clk
*clk
, struct clk
*parent
)
746 const struct cpg_core_clk
*core
;
747 const struct mssr_mod_clk
*mssr
;
750 if (gen3_clk_is_mod(clk
)) {
751 ret
= gen3_clk_get_mod(clk
, &mssr
);
755 parent
->id
= mssr
->parent
;
757 ret
= gen3_clk_get_core(clk
, &core
);
761 if (core
->type
== CLK_TYPE_IN
)
762 parent
->id
= ~0; /* Top-level clock */
764 parent
->id
= core
->parent
;
767 parent
->dev
= clk
->dev
;
772 static int gen3_clk_setup_sdif_div(struct clk
*clk
)
774 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
775 const struct cpg_core_clk
*core
;
779 ret
= gen3_clk_get_parent(clk
, &parent
);
781 printf("%s[%i] parent fail, ret=%i\n", __func__
, __LINE__
, ret
);
785 if (gen3_clk_is_mod(&parent
))
788 ret
= gen3_clk_get_core(&parent
, &core
);
792 if (core
->type
!= CLK_TYPE_GEN3_SD
)
795 debug("%s[%i] SDIF offset=%x\n", __func__
, __LINE__
, core
->offset
);
797 writel(1, priv
->base
+ core
->offset
);
802 static int gen3_clk_endisable(struct clk
*clk
, bool enable
)
804 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
805 const unsigned long clkid
= clk
->id
& 0xffff;
806 const unsigned int reg
= clkid
/ 100;
807 const unsigned int bit
= clkid
% 100;
808 const u32 bitmask
= BIT(bit
);
811 if (!gen3_clk_is_mod(clk
))
814 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__
, __LINE__
,
815 clkid
, reg
, bit
, enable
? "ON" : "OFF");
818 ret
= gen3_clk_setup_sdif_div(clk
);
821 clrbits_le32(priv
->base
+ SMSTPCR(reg
), bitmask
);
822 return wait_for_bit("MSTP", priv
->base
+ MSTPSR(reg
),
825 setbits_le32(priv
->base
+ SMSTPCR(reg
), bitmask
);
830 static int gen3_clk_enable(struct clk
*clk
)
832 return gen3_clk_endisable(clk
, true);
835 static int gen3_clk_disable(struct clk
*clk
)
837 return gen3_clk_endisable(clk
, false);
840 static ulong
gen3_clk_get_rate(struct clk
*clk
)
842 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
844 const struct cpg_core_clk
*core
;
845 const struct rcar_gen3_cpg_pll_config
*pll_config
=
846 priv
->cpg_pll_config
;
847 u32 value
, mult
, prediv
, postdiv
, rate
= 0;
850 debug("%s[%i] Clock: id=%lu\n", __func__
, __LINE__
, clk
->id
);
852 ret
= gen3_clk_get_parent(clk
, &parent
);
854 printf("%s[%i] parent fail, ret=%i\n", __func__
, __LINE__
, ret
);
858 if (gen3_clk_is_mod(clk
)) {
859 rate
= gen3_clk_get_rate(&parent
);
860 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
861 __func__
, __LINE__
, parent
.id
, rate
);
865 ret
= gen3_clk_get_core(clk
, &core
);
869 switch (core
->type
) {
871 if (core
->id
== CLK_EXTAL
) {
872 rate
= clk_get_rate(&priv
->clk_extal
);
873 debug("%s[%i] EXTAL clk: rate=%u\n",
874 __func__
, __LINE__
, rate
);
878 if (core
->id
== CLK_EXTALR
) {
879 rate
= clk_get_rate(&priv
->clk_extalr
);
880 debug("%s[%i] EXTALR clk: rate=%u\n",
881 __func__
, __LINE__
, rate
);
887 case CLK_TYPE_GEN3_MAIN
:
888 rate
= gen3_clk_get_rate(&parent
) / pll_config
->extal_div
;
889 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
891 core
->parent
, pll_config
->extal_div
, rate
);
894 case CLK_TYPE_GEN3_PLL0
:
895 value
= readl(priv
->base
+ CPG_PLL0CR
);
896 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
897 rate
= gen3_clk_get_rate(&parent
) * mult
;
898 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
899 __func__
, __LINE__
, core
->parent
, mult
, rate
);
902 case CLK_TYPE_GEN3_PLL1
:
903 rate
= gen3_clk_get_rate(&parent
) * pll_config
->pll1_mult
;
904 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
906 core
->parent
, pll_config
->pll1_mult
, rate
);
909 case CLK_TYPE_GEN3_PLL2
:
910 value
= readl(priv
->base
+ CPG_PLL2CR
);
911 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
912 rate
= gen3_clk_get_rate(&parent
) * mult
;
913 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
914 __func__
, __LINE__
, core
->parent
, mult
, rate
);
917 case CLK_TYPE_GEN3_PLL3
:
918 rate
= gen3_clk_get_rate(&parent
) * pll_config
->pll3_mult
;
919 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
921 core
->parent
, pll_config
->pll3_mult
, rate
);
924 case CLK_TYPE_GEN3_PLL4
:
925 value
= readl(priv
->base
+ CPG_PLL4CR
);
926 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
927 rate
= gen3_clk_get_rate(&parent
) * mult
;
928 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
929 __func__
, __LINE__
, core
->parent
, mult
, rate
);
933 rate
= (gen3_clk_get_rate(&parent
) * core
->mult
) / core
->div
;
934 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
936 core
->parent
, core
->mult
, core
->div
, rate
);
939 case CLK_TYPE_GEN3_SD
: /* FIXME */
940 value
= readl(priv
->base
+ core
->offset
);
941 value
&= CPG_SD_STP_MASK
| CPG_SD_FC_MASK
;
943 for (i
= 0; i
< ARRAY_SIZE(cpg_sd_div_table
); i
++) {
944 if (cpg_sd_div_table
[i
].val
!= value
)
947 rate
= gen3_clk_get_rate(&parent
) /
948 cpg_sd_div_table
[i
].div
;
949 debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
951 core
->parent
, cpg_sd_div_table
[i
].div
, rate
);
958 case CLK_TYPE_GEN3_RPC
:
959 rate
= gen3_clk_get_rate(&parent
);
961 value
= readl(priv
->base
+ core
->offset
);
963 prediv
= (value
>> CPG_RPC_PREDIV_OFFSET
) &
967 else if (prediv
== 3)
972 postdiv
= (value
>> CPG_RPC_POSTDIV_OFFSET
) &
973 CPG_RPC_POSTDIV_MASK
;
976 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
978 core
->parent
, prediv
, postdiv
, rate
);
984 printf("%s[%i] unknown fail\n", __func__
, __LINE__
);
989 static ulong
gen3_clk_set_rate(struct clk
*clk
, ulong rate
)
991 return gen3_clk_get_rate(clk
);
994 static int gen3_clk_of_xlate(struct clk
*clk
, struct ofnode_phandle_args
*args
)
996 if (args
->args_count
!= 2) {
997 debug("Invaild args_count: %d\n", args
->args_count
);
1001 clk
->id
= (args
->args
[0] << 16) | args
->args
[1];
1006 static const struct clk_ops gen3_clk_ops
= {
1007 .enable
= gen3_clk_enable
,
1008 .disable
= gen3_clk_disable
,
1009 .get_rate
= gen3_clk_get_rate
,
1010 .set_rate
= gen3_clk_set_rate
,
1011 .of_xlate
= gen3_clk_of_xlate
,
1014 enum gen3_clk_model
{
1019 static int gen3_clk_probe(struct udevice
*dev
)
1021 struct gen3_clk_priv
*priv
= dev_get_priv(dev
);
1022 enum gen3_clk_model model
= dev_get_driver_data(dev
);
1023 fdt_addr_t rst_base
;
1027 priv
->base
= (struct gen3_base
*)devfdt_get_addr(dev
);
1033 priv
->core_clk
= r8a7795_core_clks
;
1034 priv
->core_clk_size
= ARRAY_SIZE(r8a7795_core_clks
);
1035 priv
->mod_clk
= r8a7795_mod_clks
;
1036 priv
->mod_clk_size
= ARRAY_SIZE(r8a7795_mod_clks
);
1037 ret
= fdt_node_offset_by_compatible(gd
->fdt_blob
, -1,
1038 "renesas,r8a7795-rst");
1043 priv
->core_clk
= r8a7796_core_clks
;
1044 priv
->core_clk_size
= ARRAY_SIZE(r8a7796_core_clks
);
1045 priv
->mod_clk
= r8a7796_mod_clks
;
1046 priv
->mod_clk_size
= ARRAY_SIZE(r8a7796_mod_clks
);
1047 ret
= fdt_node_offset_by_compatible(gd
->fdt_blob
, -1,
1048 "renesas,r8a7796-rst");
1056 rst_base
= fdtdec_get_addr(gd
->fdt_blob
, ret
, "reg");
1057 if (rst_base
== FDT_ADDR_T_NONE
)
1060 cpg_mode
= readl(rst_base
+ CPG_RST_MODEMR
);
1062 priv
->cpg_pll_config
= &cpg_pll_configs
[CPG_PLL_CONFIG_INDEX(cpg_mode
)];
1063 if (!priv
->cpg_pll_config
->extal_div
)
1066 ret
= clk_get_by_name(dev
, "extal", &priv
->clk_extal
);
1070 ret
= clk_get_by_name(dev
, "extalr", &priv
->clk_extalr
);
1077 static const struct udevice_id gen3_clk_ids
[] = {
1078 { .compatible
= "renesas,r8a7795-cpg-mssr", .data
= CLK_R8A7795
},
1079 { .compatible
= "renesas,r8a7796-cpg-mssr", .data
= CLK_R8A7796
},
1083 U_BOOT_DRIVER(clk_gen3
) = {
1086 .of_match
= gen3_clk_ids
,
1087 .priv_auto_alloc_size
= sizeof(struct gen3_clk_priv
),
1088 .ops
= &gen3_clk_ops
,
1089 .probe
= gen3_clk_probe
,