2 * Renesas RCar Gen3 CPG MSSR driver
4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <clk-uclass.h>
21 #include <dt-bindings/clock/renesas-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
25 #define CPG_RST_MODEMR 0x0060
27 #define CPG_PLL0CR 0x00d8
28 #define CPG_PLL2CR 0x002c
29 #define CPG_PLL4CR 0x01f4
31 #define CPG_RPC_PREDIV_MASK 0x3
32 #define CPG_RPC_PREDIV_OFFSET 3
33 #define CPG_RPC_POSTDIV_MASK 0x7
34 #define CPG_RPC_POSTDIV_OFFSET 0
37 * Module Standby and Software Reset register offets.
39 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
40 * R-Car Gen2, R-Car Gen3, and RZ/G1.
41 * These are NOT valid for R-Car Gen1 and RZ/A1!
45 * Module Stop Status Register offsets
48 static const u16 mstpsr
[] = {
49 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
50 0x9A0, 0x9A4, 0x9A8, 0x9AC,
53 #define MSTPSR(i) mstpsr[i]
57 * System Module Stop Control Register offsets
60 static const u16 smstpcr
[] = {
61 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
62 0x990, 0x994, 0x998, 0x99C,
65 #define SMSTPCR(i) smstpcr[i]
68 /* Realtime Module Stop Control Register offsets */
69 #define RMSTPCR(i) (smstpcr[i] - 0x20)
71 /* Modem Module Stop Control Register offsets (r8a73a4) */
72 #define MMSTPCR(i) (smstpcr[i] + 0x20)
74 /* Software Reset Clearing Register offsets */
75 #define SRSTCLR(i) (0x940 + (i) * 4)
82 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
84 *-------------------------------------------------------------------
85 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
86 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
87 * 0 0 1 0 Prohibited setting
88 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
89 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
90 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
91 * 0 1 1 0 Prohibited setting
92 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
93 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
94 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
95 * 1 0 1 0 Prohibited setting
96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
97 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
98 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
99 * 1 1 1 0 Prohibited setting
100 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
102 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
103 (((md) & BIT(13)) >> 11) | \
104 (((md) & BIT(19)) >> 18) | \
105 (((md) & BIT(17)) >> 17))
107 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs
[16] = {
108 /* EXTAL div PLL1 mult PLL3 mult */
111 { 0, /* Prohibited setting */ },
115 { 0, /* Prohibited setting */ },
119 { 0, /* Prohibited setting */ },
123 { 0, /* Prohibited setting */ },
130 #define CPG_SD_STP_HCK BIT(9)
131 #define CPG_SD_STP_CK BIT(8)
133 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
134 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
136 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
138 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
139 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
140 ((sd_srcfc) << 2) | \
145 struct sd_div_table
{
152 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
153 *-------------------------------------------------------------------
158 * 1 0 4 (16) 1 (4) 64
163 * 1 0 4 (16) 0 (2) 32
165 static const struct sd_div_table cpg_sd_div_table
[] = {
166 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
167 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
168 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
169 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
170 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
171 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
172 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
173 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
174 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
175 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
176 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
179 static bool gen3_clk_is_mod(struct clk
*clk
)
181 return (clk
->id
>> 16) == CPG_MOD
;
184 static int gen3_clk_get_mod(struct clk
*clk
, const struct mssr_mod_clk
**mssr
)
186 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
187 struct cpg_mssr_info
*info
= priv
->info
;
188 const unsigned long clkid
= clk
->id
& 0xffff;
191 if (!gen3_clk_is_mod(clk
))
194 for (i
= 0; i
< info
->mod_clk_size
; i
++) {
195 if (info
->mod_clk
[i
].id
!= MOD_CLK_ID(clkid
))
198 *mssr
= &info
->mod_clk
[i
];
205 static int gen3_clk_get_core(struct clk
*clk
, const struct cpg_core_clk
**core
)
207 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
208 struct cpg_mssr_info
*info
= priv
->info
;
209 const unsigned long clkid
= clk
->id
& 0xffff;
212 if (gen3_clk_is_mod(clk
))
215 for (i
= 0; i
< info
->core_clk_size
; i
++) {
216 if (info
->core_clk
[i
].id
!= clkid
)
219 *core
= &info
->core_clk
[i
];
226 static int gen3_clk_get_parent(struct clk
*clk
, struct clk
*parent
)
228 const struct cpg_core_clk
*core
;
229 const struct mssr_mod_clk
*mssr
;
232 if (gen3_clk_is_mod(clk
)) {
233 ret
= gen3_clk_get_mod(clk
, &mssr
);
237 parent
->id
= mssr
->parent
;
239 ret
= gen3_clk_get_core(clk
, &core
);
243 if (core
->type
== CLK_TYPE_IN
)
244 parent
->id
= ~0; /* Top-level clock */
246 parent
->id
= core
->parent
;
249 parent
->dev
= clk
->dev
;
254 static int gen3_clk_setup_sdif_div(struct clk
*clk
)
256 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
257 const struct cpg_core_clk
*core
;
261 ret
= gen3_clk_get_parent(clk
, &parent
);
263 printf("%s[%i] parent fail, ret=%i\n", __func__
, __LINE__
, ret
);
267 if (gen3_clk_is_mod(&parent
))
270 ret
= gen3_clk_get_core(&parent
, &core
);
274 if (core
->type
!= CLK_TYPE_GEN3_SD
)
277 debug("%s[%i] SDIF offset=%x\n", __func__
, __LINE__
, core
->offset
);
279 writel(1, priv
->base
+ core
->offset
);
284 static int gen3_clk_endisable(struct clk
*clk
, bool enable
)
286 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
287 const unsigned long clkid
= clk
->id
& 0xffff;
288 const unsigned int reg
= clkid
/ 100;
289 const unsigned int bit
= clkid
% 100;
290 const u32 bitmask
= BIT(bit
);
293 if (!gen3_clk_is_mod(clk
))
296 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__
, __LINE__
,
297 clkid
, reg
, bit
, enable
? "ON" : "OFF");
300 ret
= gen3_clk_setup_sdif_div(clk
);
303 clrbits_le32(priv
->base
+ SMSTPCR(reg
), bitmask
);
304 return wait_for_bit("MSTP", priv
->base
+ MSTPSR(reg
),
307 setbits_le32(priv
->base
+ SMSTPCR(reg
), bitmask
);
312 static int gen3_clk_enable(struct clk
*clk
)
314 return gen3_clk_endisable(clk
, true);
317 static int gen3_clk_disable(struct clk
*clk
)
319 return gen3_clk_endisable(clk
, false);
322 static ulong
gen3_clk_get_rate(struct clk
*clk
)
324 struct gen3_clk_priv
*priv
= dev_get_priv(clk
->dev
);
326 const struct cpg_core_clk
*core
;
327 const struct rcar_gen3_cpg_pll_config
*pll_config
=
328 priv
->cpg_pll_config
;
329 u32 value
, mult
, prediv
, postdiv
, rate
= 0;
332 debug("%s[%i] Clock: id=%lu\n", __func__
, __LINE__
, clk
->id
);
334 ret
= gen3_clk_get_parent(clk
, &parent
);
336 printf("%s[%i] parent fail, ret=%i\n", __func__
, __LINE__
, ret
);
340 if (gen3_clk_is_mod(clk
)) {
341 rate
= gen3_clk_get_rate(&parent
);
342 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
343 __func__
, __LINE__
, parent
.id
, rate
);
347 ret
= gen3_clk_get_core(clk
, &core
);
351 switch (core
->type
) {
353 if (core
->id
== CLK_EXTAL
) {
354 rate
= clk_get_rate(&priv
->clk_extal
);
355 debug("%s[%i] EXTAL clk: rate=%u\n",
356 __func__
, __LINE__
, rate
);
360 if (core
->id
== CLK_EXTALR
) {
361 rate
= clk_get_rate(&priv
->clk_extalr
);
362 debug("%s[%i] EXTALR clk: rate=%u\n",
363 __func__
, __LINE__
, rate
);
369 case CLK_TYPE_GEN3_MAIN
:
370 rate
= gen3_clk_get_rate(&parent
) / pll_config
->extal_div
;
371 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
373 core
->parent
, pll_config
->extal_div
, rate
);
376 case CLK_TYPE_GEN3_PLL0
:
377 value
= readl(priv
->base
+ CPG_PLL0CR
);
378 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
379 rate
= gen3_clk_get_rate(&parent
) * mult
;
380 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
381 __func__
, __LINE__
, core
->parent
, mult
, rate
);
384 case CLK_TYPE_GEN3_PLL1
:
385 rate
= gen3_clk_get_rate(&parent
) * pll_config
->pll1_mult
;
386 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
388 core
->parent
, pll_config
->pll1_mult
, rate
);
391 case CLK_TYPE_GEN3_PLL2
:
392 value
= readl(priv
->base
+ CPG_PLL2CR
);
393 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
394 rate
= gen3_clk_get_rate(&parent
) * mult
;
395 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
396 __func__
, __LINE__
, core
->parent
, mult
, rate
);
399 case CLK_TYPE_GEN3_PLL3
:
400 rate
= gen3_clk_get_rate(&parent
) * pll_config
->pll3_mult
;
401 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
403 core
->parent
, pll_config
->pll3_mult
, rate
);
406 case CLK_TYPE_GEN3_PLL4
:
407 value
= readl(priv
->base
+ CPG_PLL4CR
);
408 mult
= (((value
>> 24) & 0x7f) + 1) * 2;
409 rate
= gen3_clk_get_rate(&parent
) * mult
;
410 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
411 __func__
, __LINE__
, core
->parent
, mult
, rate
);
415 case CLK_TYPE_GEN3_PE
: /* FIXME */
416 rate
= (gen3_clk_get_rate(&parent
) * core
->mult
) / core
->div
;
417 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
419 core
->parent
, core
->mult
, core
->div
, rate
);
422 case CLK_TYPE_GEN3_SD
: /* FIXME */
423 value
= readl(priv
->base
+ core
->offset
);
424 value
&= CPG_SD_STP_MASK
| CPG_SD_FC_MASK
;
426 for (i
= 0; i
< ARRAY_SIZE(cpg_sd_div_table
); i
++) {
427 if (cpg_sd_div_table
[i
].val
!= value
)
430 rate
= gen3_clk_get_rate(&parent
) /
431 cpg_sd_div_table
[i
].div
;
432 debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
434 core
->parent
, cpg_sd_div_table
[i
].div
, rate
);
441 case CLK_TYPE_GEN3_RPC
:
442 rate
= gen3_clk_get_rate(&parent
);
444 value
= readl(priv
->base
+ core
->offset
);
446 prediv
= (value
>> CPG_RPC_PREDIV_OFFSET
) &
450 else if (prediv
== 3)
455 postdiv
= (value
>> CPG_RPC_POSTDIV_OFFSET
) &
456 CPG_RPC_POSTDIV_MASK
;
459 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n",
461 core
->parent
, prediv
, postdiv
, rate
);
467 printf("%s[%i] unknown fail\n", __func__
, __LINE__
);
472 static ulong
gen3_clk_set_rate(struct clk
*clk
, ulong rate
)
474 return gen3_clk_get_rate(clk
);
477 static int gen3_clk_of_xlate(struct clk
*clk
, struct ofnode_phandle_args
*args
)
479 if (args
->args_count
!= 2) {
480 debug("Invaild args_count: %d\n", args
->args_count
);
484 clk
->id
= (args
->args
[0] << 16) | args
->args
[1];
489 const struct clk_ops gen3_clk_ops
= {
490 .enable
= gen3_clk_enable
,
491 .disable
= gen3_clk_disable
,
492 .get_rate
= gen3_clk_get_rate
,
493 .set_rate
= gen3_clk_set_rate
,
494 .of_xlate
= gen3_clk_of_xlate
,
497 int gen3_clk_probe(struct udevice
*dev
)
499 struct gen3_clk_priv
*priv
= dev_get_priv(dev
);
500 struct cpg_mssr_info
*info
=
501 (struct cpg_mssr_info
*)dev_get_driver_data(dev
);
506 priv
->base
= (struct gen3_base
*)devfdt_get_addr(dev
);
511 ret
= fdt_node_offset_by_compatible(gd
->fdt_blob
, -1, info
->reset_node
);
515 rst_base
= fdtdec_get_addr(gd
->fdt_blob
, ret
, "reg");
516 if (rst_base
== FDT_ADDR_T_NONE
)
519 cpg_mode
= readl(rst_base
+ CPG_RST_MODEMR
);
521 priv
->cpg_pll_config
= &cpg_pll_configs
[CPG_PLL_CONFIG_INDEX(cpg_mode
)];
522 if (!priv
->cpg_pll_config
->extal_div
)
525 ret
= clk_get_by_name(dev
, "extal", &priv
->clk_extal
);
529 if (info
->extalr_node
) {
530 ret
= clk_get_by_name(dev
, info
->extalr_node
, &priv
->clk_extalr
);
538 int gen3_clk_remove(struct udevice
*dev
)
540 struct gen3_clk_priv
*priv
= dev_get_priv(dev
);
541 struct cpg_mssr_info
*info
= priv
->info
;
545 clrbits_le32(TMU_BASE
+ TSTR0
, TSTR0_STR0
);
547 /* Stop module clock */
548 for (i
= 0; i
< info
->mstp_table_size
; i
++) {
549 clrsetbits_le32(priv
->base
+ SMSTPCR(i
),
550 info
->mstp_table
[i
].dis
,
551 info
->mstp_table
[i
].en
);
552 clrsetbits_le32(priv
->base
+ RMSTPCR(i
),
553 info
->mstp_table
[i
].dis
, 0x0);