1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
7 #include <clk-uclass.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/cru_rk322x.h>
14 #include <asm/arch/hardware.h>
16 #include <dt-bindings/clock/rk3228-cru.h>
17 #include <linux/log2.h>
20 VCO_MAX_HZ
= 3200U * 1000000,
21 VCO_MIN_HZ
= 800 * 1000000,
22 OUTPUT_MAX_HZ
= 3200U * 1000000,
23 OUTPUT_MIN_HZ
= 24 * 1000000,
26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
32 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
33 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
34 #hz "Hz cannot be hit with PLL "\
35 "divisors on line " __stringify(__LINE__));
38 static const struct pll_div apll_init_cfg
= PLL_DIVISORS(APLL_HZ
, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2, 1);
41 static int rkclk_set_pll(struct rk322x_cru
*cru
, enum rk_clk_id clk_id
,
42 const struct pll_div
*div
)
44 int pll_id
= rk_pll_id(clk_id
);
45 struct rk322x_pll
*pll
= &cru
->pll
[pll_id
];
47 /* All PLLs have same VCO and output frequency range restrictions. */
48 uint vco_hz
= OSC_HZ
/ 1000 * div
->fbdiv
/ div
->refdiv
* 1000;
49 uint output_hz
= vco_hz
/ div
->postdiv1
/ div
->postdiv2
;
51 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
52 pll
, div
->fbdiv
, div
->refdiv
, div
->postdiv1
,
53 div
->postdiv2
, vco_hz
, output_hz
);
54 assert(vco_hz
>= VCO_MIN_HZ
&& vco_hz
<= VCO_MAX_HZ
&&
55 output_hz
>= OUTPUT_MIN_HZ
&& output_hz
<= OUTPUT_MAX_HZ
);
57 /* use integer mode */
58 rk_setreg(&pll
->con1
, 1 << PLL_DSMPD_SHIFT
);
60 rk_setreg(&pll
->con1
, 1 << PLL_PD_SHIFT
);
62 rk_clrsetreg(&pll
->con0
,
63 PLL_POSTDIV1_MASK
| PLL_FBDIV_MASK
,
64 (div
->postdiv1
<< PLL_POSTDIV1_SHIFT
) | div
->fbdiv
);
65 rk_clrsetreg(&pll
->con1
, PLL_POSTDIV2_MASK
| PLL_REFDIV_MASK
,
66 (div
->postdiv2
<< PLL_POSTDIV2_SHIFT
|
67 div
->refdiv
<< PLL_REFDIV_SHIFT
));
70 rk_clrreg(&pll
->con1
, 1 << PLL_PD_SHIFT
);
72 /* waiting for pll lock */
73 while (readl(&pll
->con1
) & (1 << PLL_LOCK_STATUS_SHIFT
))
79 static void rkclk_init(struct rk322x_cru
*cru
)
85 /* pll enter slow-mode */
86 rk_clrsetreg(&cru
->cru_mode_con
,
87 GPLL_MODE_MASK
| APLL_MODE_MASK
,
88 GPLL_MODE_SLOW
<< GPLL_MODE_SHIFT
|
89 APLL_MODE_SLOW
<< APLL_MODE_SHIFT
);
92 rkclk_set_pll(cru
, CLK_ARM
, &apll_init_cfg
);
93 rkclk_set_pll(cru
, CLK_GENERAL
, &gpll_init_cfg
);
96 * select apll as cpu/core clock pll source and
97 * set up dependent divisors for PERI and ACLK clocks.
98 * core hz : apll = 1:1
100 aclk_div
= APLL_HZ
/ CORE_ACLK_HZ
- 1;
101 assert((aclk_div
+ 1) * CORE_ACLK_HZ
== APLL_HZ
&& aclk_div
< 0x7);
103 pclk_div
= APLL_HZ
/ CORE_PERI_HZ
- 1;
104 assert((pclk_div
+ 1) * CORE_PERI_HZ
== APLL_HZ
&& pclk_div
< 0xf);
106 rk_clrsetreg(&cru
->cru_clksel_con
[0],
107 CORE_CLK_PLL_SEL_MASK
| CORE_DIV_CON_MASK
,
108 CORE_CLK_PLL_SEL_APLL
<< CORE_CLK_PLL_SEL_SHIFT
|
109 0 << CORE_DIV_CON_SHIFT
);
111 rk_clrsetreg(&cru
->cru_clksel_con
[1],
112 CORE_ACLK_DIV_MASK
| CORE_PERI_DIV_MASK
,
113 aclk_div
<< CORE_ACLK_DIV_SHIFT
|
114 pclk_div
<< CORE_PERI_DIV_SHIFT
);
117 * select gpll as pd_bus bus clock source and
118 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
120 aclk_div
= GPLL_HZ
/ BUS_ACLK_HZ
- 1;
121 assert((aclk_div
+ 1) * BUS_ACLK_HZ
== GPLL_HZ
&& aclk_div
<= 0x1f);
123 pclk_div
= BUS_ACLK_HZ
/ BUS_PCLK_HZ
- 1;
124 assert((pclk_div
+ 1) * BUS_PCLK_HZ
== GPLL_HZ
&& pclk_div
<= 0x7);
126 hclk_div
= BUS_ACLK_HZ
/ BUS_HCLK_HZ
- 1;
127 assert((hclk_div
+ 1) * BUS_HCLK_HZ
== GPLL_HZ
&& hclk_div
<= 0x3);
129 rk_clrsetreg(&cru
->cru_clksel_con
[0],
130 BUS_ACLK_PLL_SEL_MASK
| BUS_ACLK_DIV_MASK
,
131 BUS_ACLK_PLL_SEL_GPLL
<< BUS_ACLK_PLL_SEL_SHIFT
|
132 aclk_div
<< BUS_ACLK_DIV_SHIFT
);
134 rk_clrsetreg(&cru
->cru_clksel_con
[1],
135 BUS_PCLK_DIV_MASK
| BUS_HCLK_DIV_MASK
,
136 pclk_div
<< BUS_PCLK_DIV_SHIFT
|
137 hclk_div
<< BUS_HCLK_DIV_SHIFT
);
140 * select gpll as pd_peri bus clock source and
141 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
143 aclk_div
= GPLL_HZ
/ PERI_ACLK_HZ
- 1;
144 assert((aclk_div
+ 1) * PERI_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
146 hclk_div
= ilog2(PERI_ACLK_HZ
/ PERI_HCLK_HZ
);
147 assert((1 << hclk_div
) * PERI_HCLK_HZ
==
148 PERI_ACLK_HZ
&& (hclk_div
< 0x4));
150 pclk_div
= ilog2(PERI_ACLK_HZ
/ PERI_PCLK_HZ
);
151 assert((1 << pclk_div
) * PERI_PCLK_HZ
==
152 PERI_ACLK_HZ
&& pclk_div
< 0x8);
154 rk_clrsetreg(&cru
->cru_clksel_con
[10],
155 PERI_PLL_SEL_MASK
| PERI_PCLK_DIV_MASK
|
156 PERI_HCLK_DIV_MASK
| PERI_ACLK_DIV_MASK
,
157 PERI_PLL_GPLL
<< PERI_PLL_SEL_SHIFT
|
158 pclk_div
<< PERI_PCLK_DIV_SHIFT
|
159 hclk_div
<< PERI_HCLK_DIV_SHIFT
|
160 aclk_div
<< PERI_ACLK_DIV_SHIFT
);
162 /* PLL enter normal-mode */
163 rk_clrsetreg(&cru
->cru_mode_con
,
164 GPLL_MODE_MASK
| APLL_MODE_MASK
,
165 GPLL_MODE_NORM
<< GPLL_MODE_SHIFT
|
166 APLL_MODE_NORM
<< APLL_MODE_SHIFT
);
169 /* Get pll rate by id */
170 static uint32_t rkclk_pll_get_rate(struct rk322x_cru
*cru
,
171 enum rk_clk_id clk_id
)
173 uint32_t refdiv
, fbdiv
, postdiv1
, postdiv2
;
175 int pll_id
= rk_pll_id(clk_id
);
176 struct rk322x_pll
*pll
= &cru
->pll
[pll_id
];
177 static u8 clk_shift
[CLK_COUNT
] = {
178 0xff, APLL_MODE_SHIFT
, DPLL_MODE_SHIFT
, 0xff,
179 GPLL_MODE_SHIFT
, 0xff
181 static u32 clk_mask
[CLK_COUNT
] = {
182 0xff, APLL_MODE_MASK
, DPLL_MODE_MASK
, 0xff,
188 con
= readl(&cru
->cru_mode_con
);
189 shift
= clk_shift
[clk_id
];
190 mask
= clk_mask
[clk_id
];
192 switch ((con
& mask
) >> shift
) {
198 con
= readl(&pll
->con0
);
199 postdiv1
= (con
& PLL_POSTDIV1_MASK
) >> PLL_POSTDIV1_SHIFT
;
200 fbdiv
= (con
& PLL_FBDIV_MASK
) >> PLL_FBDIV_SHIFT
;
201 con
= readl(&pll
->con1
);
202 postdiv2
= (con
& PLL_POSTDIV2_MASK
) >> PLL_POSTDIV2_SHIFT
;
203 refdiv
= (con
& PLL_REFDIV_MASK
) >> PLL_REFDIV_SHIFT
;
204 return (24 * fbdiv
/ (refdiv
* postdiv1
* postdiv2
)) * 1000000;
210 static ulong
rockchip_mmc_get_clk(struct rk322x_cru
*cru
, uint clk_general_rate
,
220 con
= readl(&cru
->cru_clksel_con
[11]);
221 mux
= (con
& EMMC_PLL_MASK
) >> EMMC_PLL_SHIFT
;
222 con
= readl(&cru
->cru_clksel_con
[12]);
223 div
= (con
& EMMC_DIV_MASK
) >> EMMC_DIV_SHIFT
;
227 con
= readl(&cru
->cru_clksel_con
[11]);
228 mux
= (con
& MMC0_PLL_MASK
) >> MMC0_PLL_SHIFT
;
229 div
= (con
& MMC0_DIV_MASK
) >> MMC0_DIV_SHIFT
;
235 src_rate
= mux
== EMMC_SEL_24M
? OSC_HZ
: clk_general_rate
;
236 return DIV_TO_RATE(src_rate
, div
) / 2;
239 static ulong
rk322x_mac_set_clk(struct rk322x_cru
*cru
, uint freq
)
244 * The gmac clock can be derived either from an external clock
245 * or can be generated from internally by a divider from SCLK_MAC.
247 if (readl(&cru
->cru_clksel_con
[5]) & BIT(5)) {
248 /* An external clock will always generate the right rate... */
251 u32 con
= readl(&cru
->cru_clksel_con
[5]);
255 if ((con
>> MAC_PLL_SEL_SHIFT
) & MAC_PLL_SEL_MASK
)
258 /* CPLL is not set */
261 div
= DIV_ROUND_UP(pll_rate
, freq
) - 1;
263 rk_clrsetreg(&cru
->cru_clksel_con
[5], CLK_MAC_DIV_MASK
,
264 div
<< CLK_MAC_DIV_SHIFT
);
266 debug("Unsupported div for gmac:%d\n", div
);
268 return DIV_TO_RATE(pll_rate
, div
);
274 static ulong
rockchip_mmc_set_clk(struct rk322x_cru
*cru
, uint clk_general_rate
,
275 int periph
, uint freq
)
280 debug("%s: clk_general_rate=%u\n", __func__
, clk_general_rate
);
282 /* mmc clock defaulg div 2 internal, need provide double in cru */
283 src_clk_div
= DIV_ROUND_UP(clk_general_rate
/ 2, freq
);
285 if (src_clk_div
> 128) {
286 src_clk_div
= DIV_ROUND_UP(OSC_HZ
/ 2, freq
);
287 assert(src_clk_div
- 1 < 128);
296 rk_clrsetreg(&cru
->cru_clksel_con
[11],
298 mux
<< EMMC_PLL_SHIFT
);
299 rk_clrsetreg(&cru
->cru_clksel_con
[12],
301 (src_clk_div
- 1) << EMMC_DIV_SHIFT
);
305 rk_clrsetreg(&cru
->cru_clksel_con
[11],
306 MMC0_PLL_MASK
| MMC0_DIV_MASK
,
307 mux
<< MMC0_PLL_SHIFT
|
308 (src_clk_div
- 1) << MMC0_DIV_SHIFT
);
314 return rockchip_mmc_get_clk(cru
, clk_general_rate
, periph
);
317 static int rk322x_ddr_set_clk(struct rk322x_cru
*cru
, unsigned int set_rate
)
319 struct pll_div dpll_cfg
;
321 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
324 dpll_cfg
= (struct pll_div
)
325 {.refdiv
= 1, .fbdiv
= 50, .postdiv1
= 3, .postdiv2
= 1};
328 dpll_cfg
= (struct pll_div
)
329 {.refdiv
= 1, .fbdiv
= 75, .postdiv1
= 3, .postdiv2
= 1};
332 dpll_cfg
= (struct pll_div
)
333 {.refdiv
= 1, .fbdiv
= 100, .postdiv1
= 3, .postdiv2
= 1};
337 /* pll enter slow-mode */
338 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
,
339 DPLL_MODE_SLOW
<< DPLL_MODE_SHIFT
);
340 rkclk_set_pll(cru
, CLK_DDR
, &dpll_cfg
);
341 /* PLL enter normal-mode */
342 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
,
343 DPLL_MODE_NORM
<< DPLL_MODE_SHIFT
);
347 static ulong
rk322x_clk_get_rate(struct clk
*clk
)
349 struct rk322x_clk_priv
*priv
= dev_get_priv(clk
->dev
);
350 ulong rate
, gclk_rate
;
352 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
355 rate
= rkclk_pll_get_rate(priv
->cru
, clk
->id
);
361 rate
= rockchip_mmc_get_clk(priv
->cru
, gclk_rate
, clk
->id
);
370 static ulong
rk322x_clk_set_rate(struct clk
*clk
, ulong rate
)
372 struct rk322x_clk_priv
*priv
= dev_get_priv(clk
->dev
);
373 ulong new_rate
, gclk_rate
;
375 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
381 new_rate
= rockchip_mmc_set_clk(priv
->cru
, gclk_rate
,
385 new_rate
= rk322x_ddr_set_clk(priv
->cru
, rate
);
388 new_rate
= rk322x_mac_set_clk(priv
->cru
, rate
);
399 static int rk322x_gmac_set_parent(struct clk
*clk
, struct clk
*parent
)
401 struct rk322x_clk_priv
*priv
= dev_get_priv(clk
->dev
);
402 struct rk322x_cru
*cru
= priv
->cru
;
405 * If the requested parent is in the same clock-controller and the id
406 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
408 if ((parent
->dev
== clk
->dev
) && (parent
->id
== SCLK_MAC_SRC
)) {
409 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__
);
410 rk_clrsetreg(&cru
->cru_clksel_con
[5], BIT(5), 0);
415 * If the requested parent is in the same clock-controller and the id
416 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
418 if ((parent
->dev
== clk
->dev
) && (parent
->id
== SCLK_MAC_EXTCLK
)) {
419 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__
);
420 rk_clrsetreg(&cru
->cru_clksel_con
[5], BIT(5), BIT(5));
427 static int rk322x_gmac_extclk_set_parent(struct clk
*clk
, struct clk
*parent
)
429 struct rk322x_clk_priv
*priv
= dev_get_priv(clk
->dev
);
430 const char *clock_output_name
;
431 struct rk322x_cru
*cru
= priv
->cru
;
434 ret
= dev_read_string_index(parent
->dev
, "clock-output-names",
435 parent
->id
, &clock_output_name
);
439 if (!strcmp(clock_output_name
, "ext_gmac")) {
440 debug("%s: switching gmac extclk to ext_gmac\n", __func__
);
441 rk_clrsetreg(&cru
->cru_clksel_con
[29], BIT(10), 0);
443 } else if (!strcmp(clock_output_name
, "phy_50m_out")) {
444 debug("%s: switching gmac extclk to phy_50m_out\n", __func__
);
445 rk_clrsetreg(&cru
->cru_clksel_con
[29], BIT(10), BIT(10));
452 static int rk322x_clk_set_parent(struct clk
*clk
, struct clk
*parent
)
456 return rk322x_gmac_set_parent(clk
, parent
);
457 case SCLK_MAC_EXTCLK
:
458 return rk322x_gmac_extclk_set_parent(clk
, parent
);
461 debug("%s: unsupported clk %ld\n", __func__
, clk
->id
);
465 static struct clk_ops rk322x_clk_ops
= {
466 .get_rate
= rk322x_clk_get_rate
,
467 .set_rate
= rk322x_clk_set_rate
,
468 .set_parent
= rk322x_clk_set_parent
,
471 static int rk322x_clk_ofdata_to_platdata(struct udevice
*dev
)
473 struct rk322x_clk_priv
*priv
= dev_get_priv(dev
);
475 priv
->cru
= dev_read_addr_ptr(dev
);
480 static int rk322x_clk_probe(struct udevice
*dev
)
482 struct rk322x_clk_priv
*priv
= dev_get_priv(dev
);
484 rkclk_init(priv
->cru
);
489 static int rk322x_clk_bind(struct udevice
*dev
)
492 struct udevice
*sys_child
;
493 struct sysreset_reg
*priv
;
495 /* The reset driver does not have a device node, so bind it here */
496 ret
= device_bind_driver(dev
, "rockchip_sysreset", "sysreset",
499 debug("Warning: No sysreset driver: ret=%d\n", ret
);
501 priv
= malloc(sizeof(struct sysreset_reg
));
502 priv
->glb_srst_fst_value
= offsetof(struct rk322x_cru
,
503 cru_glb_srst_fst_value
);
504 priv
->glb_srst_snd_value
= offsetof(struct rk322x_cru
,
505 cru_glb_srst_snd_value
);
506 sys_child
->priv
= priv
;
509 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
510 ret
= offsetof(struct rk322x_cru
, cru_softrst_con
[0]);
511 ret
= rockchip_reset_bind(dev
, ret
, 9);
513 debug("Warning: software reset driver bind faile\n");
519 static const struct udevice_id rk322x_clk_ids
[] = {
520 { .compatible
= "rockchip,rk3228-cru" },
524 U_BOOT_DRIVER(rockchip_rk322x_cru
) = {
525 .name
= "clk_rk322x",
527 .of_match
= rk322x_clk_ids
,
528 .priv_auto_alloc_size
= sizeof(struct rk322x_clk_priv
),
529 .ofdata_to_platdata
= rk322x_clk_ofdata_to_platdata
,
530 .ops
= &rk322x_clk_ops
,
531 .bind
= rk322x_clk_bind
,
532 .probe
= rk322x_clk_probe
,