2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cru_rk3368.h>
17 #include <asm/arch/hardware.h>
20 #include <dt-bindings/clock/rk3368-cru.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
25 struct rk3368_clk_plat
{
26 struct dtd_rockchip_rk3368_cru dtd
;
36 #define OSC_HZ (24 * 1000 * 1000)
37 #define APLL_L_HZ (800 * 1000 * 1000)
38 #define APLL_B_HZ (816 * 1000 * 1000)
39 #define GPLL_HZ (576 * 1000 * 1000)
40 #define CPLL_HZ (400 * 1000 * 1000)
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
44 #define PLL_DIVISORS(hz, _nr, _no) { \
45 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
46 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
47 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
48 "divisors on line " __stringify(__LINE__));
50 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
51 static const struct pll_div apll_l_init_cfg
= PLL_DIVISORS(APLL_L_HZ
, 12, 2);
52 static const struct pll_div apll_b_init_cfg
= PLL_DIVISORS(APLL_B_HZ
, 1, 2);
53 #if !defined(CONFIG_TPL_BUILD)
54 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 1, 2);
55 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 6);
59 static ulong
rk3368_clk_get_rate(struct clk
*clk
);
61 /* Get pll rate by id */
62 static uint32_t rkclk_pll_get_rate(struct rk3368_cru
*cru
,
63 enum rk3368_pll_id pll_id
)
67 struct rk3368_pll
*pll
= &cru
->pll
[pll_id
];
69 con
= readl(&pll
->con3
);
71 switch ((con
& PLL_MODE_MASK
) >> PLL_MODE_SHIFT
) {
75 con
= readl(&pll
->con0
);
76 no
= ((con
& PLL_OD_MASK
) >> PLL_OD_SHIFT
) + 1;
77 nr
= ((con
& PLL_NR_MASK
) >> PLL_NR_SHIFT
) + 1;
78 con
= readl(&pll
->con1
);
79 nf
= ((con
& PLL_NF_MASK
) >> PLL_NF_SHIFT
) + 1;
81 return (24 * nf
/ (nr
* no
)) * 1000000;
82 case PLL_MODE_DEEP_SLOW
:
88 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
89 static int rkclk_set_pll(struct rk3368_cru
*cru
, enum rk3368_pll_id pll_id
,
90 const struct pll_div
*div
)
92 struct rk3368_pll
*pll
= &cru
->pll
[pll_id
];
93 /* All PLLs have same VCO and output frequency range restrictions*/
94 uint vco_hz
= OSC_HZ
/ 1000 * div
->nf
/ div
->nr
* 1000;
95 uint output_hz
= vco_hz
/ div
->no
;
97 debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
98 pll
, div
->nf
, div
->nr
, div
->no
, vco_hz
, output_hz
);
100 /* enter slow mode and reset pll */
101 rk_clrsetreg(&pll
->con3
, PLL_MODE_MASK
| PLL_RESET_MASK
,
102 PLL_RESET
<< PLL_RESET_SHIFT
);
104 rk_clrsetreg(&pll
->con0
, PLL_NR_MASK
| PLL_OD_MASK
,
105 ((div
->nr
- 1) << PLL_NR_SHIFT
) |
106 ((div
->no
- 1) << PLL_OD_SHIFT
));
107 writel((div
->nf
- 1) << PLL_NF_SHIFT
, &pll
->con1
);
109 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
110 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
112 clrsetbits_le32(&pll
->con2
, PLL_BWADJ_MASK
, (div
->nf
>> 1) - 1);
116 /* return from reset */
117 rk_clrreg(&pll
->con3
, PLL_RESET_MASK
);
119 /* waiting for pll lock */
120 while (!(readl(&pll
->con1
) & PLL_LOCK_STA
))
123 rk_clrsetreg(&pll
->con3
, PLL_MODE_MASK
,
124 PLL_MODE_NORMAL
<< PLL_MODE_SHIFT
);
130 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
131 static void rkclk_init(struct rk3368_cru
*cru
)
133 u32 apllb
, aplll
, dpll
, cpll
, gpll
;
135 rkclk_set_pll(cru
, APLLB
, &apll_b_init_cfg
);
136 rkclk_set_pll(cru
, APLLL
, &apll_l_init_cfg
);
137 #if !defined(CONFIG_TPL_BUILD)
139 * If we plan to return to the boot ROM, we can't increase the
140 * GPLL rate from the SPL stage.
142 rkclk_set_pll(cru
, GPLL
, &gpll_init_cfg
);
143 rkclk_set_pll(cru
, CPLL
, &cpll_init_cfg
);
146 apllb
= rkclk_pll_get_rate(cru
, APLLB
);
147 aplll
= rkclk_pll_get_rate(cru
, APLLL
);
148 dpll
= rkclk_pll_get_rate(cru
, DPLL
);
149 cpll
= rkclk_pll_get_rate(cru
, CPLL
);
150 gpll
= rkclk_pll_get_rate(cru
, GPLL
);
152 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
153 __func__
, apllb
, aplll
, dpll
, cpll
, gpll
);
157 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
158 static ulong
rk3368_mmc_get_clk(struct rk3368_cru
*cru
, uint clk_id
)
160 u32 div
, con
, con_id
, rate
;
177 con
= readl(&cru
->clksel_con
[con_id
]);
178 switch (con
& MMC_PLL_SEL_MASK
) {
179 case MMC_PLL_SEL_GPLL
:
180 pll_rate
= rkclk_pll_get_rate(cru
, GPLL
);
182 case MMC_PLL_SEL_24M
:
185 case MMC_PLL_SEL_CPLL
:
186 pll_rate
= rkclk_pll_get_rate(cru
, CPLL
);
188 case MMC_PLL_SEL_USBPHY_480M
:
192 div
= (con
& MMC_CLK_DIV_MASK
) >> MMC_CLK_DIV_SHIFT
;
193 rate
= DIV_TO_RATE(pll_rate
, div
);
195 debug("%s: raw rate %d (post-divide by 2)\n", __func__
, rate
);
199 static ulong
rk3368_mmc_find_best_rate_and_parent(struct clk
*clk
,
206 const ulong MHz
= 1000000;
211 { .mux
= MMC_PLL_SEL_CPLL
, .rate
= CPLL_HZ
},
212 { .mux
= MMC_PLL_SEL_GPLL
, .rate
= GPLL_HZ
},
213 { .mux
= MMC_PLL_SEL_24M
, .rate
= 24 * MHz
}
216 debug("%s: target rate %ld\n", __func__
, rate
);
217 for (i
= 0; i
< ARRAY_SIZE(parents
); ++i
) {
219 * Find the largest rate no larger than the target-rate for
220 * the current parent.
222 ulong parent_rate
= parents
[i
].rate
;
223 u32 div
= DIV_ROUND_UP(parent_rate
, rate
);
225 ulong new_rate
= parent_rate
/ adj_div
;
227 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
228 __func__
, rate
, parents
[i
].mux
, parents
[i
].rate
, div
);
230 /* Skip, if not representable */
231 if ((div
- 1) > MMC_CLK_DIV_MASK
)
234 /* Skip, if we already have a better (or equal) solution */
235 if (new_rate
<= best_rate
)
238 /* This is our new best rate. */
239 best_rate
= new_rate
;
240 *best_mux
= parents
[i
].mux
;
244 debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
245 __func__
, *best_mux
, *best_div
, best_rate
);
250 static ulong
rk3368_mmc_set_clk(struct clk
*clk
, ulong rate
)
252 struct rk3368_clk_priv
*priv
= dev_get_priv(clk
->dev
);
253 struct rk3368_cru
*cru
= priv
->cru
;
254 ulong clk_id
= clk
->id
;
255 u32 con_id
, mux
= 0, div
= 0;
257 /* Find the best parent and rate */
258 rk3368_mmc_find_best_rate_and_parent(clk
, rate
<< 1, &mux
, &div
);
274 rk_clrsetreg(&cru
->clksel_con
[con_id
],
275 MMC_PLL_SEL_MASK
| MMC_CLK_DIV_MASK
,
278 return rk3368_mmc_get_clk(cru
, clk_id
);
282 #if IS_ENABLED(CONFIG_TPL_BUILD)
283 static ulong
rk3368_ddr_set_clk(struct rk3368_cru
*cru
, ulong set_rate
)
285 const struct pll_div
*dpll_cfg
= NULL
;
286 const ulong MHz
= 1000000;
288 /* Fout = ((Fin /NR) * NF )/ NO */
289 static const struct pll_div dpll_1200
= PLL_DIVISORS(1200 * MHz
, 1, 1);
290 static const struct pll_div dpll_1332
= PLL_DIVISORS(1332 * MHz
, 2, 1);
291 static const struct pll_div dpll_1600
= PLL_DIVISORS(1600 * MHz
, 3, 2);
295 dpll_cfg
= &dpll_1200
;
298 dpll_cfg
= &dpll_1332
;
301 dpll_cfg
= &dpll_1600
;
304 error("Unsupported SDRAM frequency!,%ld\n", set_rate
);
306 rkclk_set_pll(cru
, DPLL
, dpll_cfg
);
312 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
313 static ulong
rk3368_gmac_set_clk(struct rk3368_cru
*cru
,
314 ulong clk_id
, ulong set_rate
)
317 * This models the 'assigned-clock-parents = <&ext_gmac>' from
318 * the DTS and switches to the 'ext_gmac' clock parent.
320 rk_setreg(&cru
->clksel_con
[43], GMAC_MUX_SEL_EXTCLK
);
326 * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
327 * to select either CPLL or GPLL as the clock-parent. The location within
328 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
332 uint8_t reg
; /* CLKSEL_CON[reg] register in CRU */
338 * The entries are numbered relative to their offset from SCLK_SPI0.
340 static const struct spi_clkreg spi_clkregs
[] = {
341 [0] = { .reg
= 45, .div_shift
= 0, .sel_shift
= 7, },
342 [1] = { .reg
= 45, .div_shift
= 8, .sel_shift
= 15, },
343 [2] = { .reg
= 46, .div_shift
= 8, .sel_shift
= 15, },
346 static inline u32
extract_bits(u32 val
, unsigned width
, unsigned shift
)
348 return (val
>> shift
) & ((1 << width
) - 1);
351 static ulong
rk3368_spi_get_clk(struct rk3368_cru
*cru
, ulong clk_id
)
353 const struct spi_clkreg
*spiclk
= NULL
;
357 case SCLK_SPI0
... SCLK_SPI2
:
358 spiclk
= &spi_clkregs
[clk_id
- SCLK_SPI0
];
362 error("%s: SPI clk-id %ld not supported\n", __func__
, clk_id
);
366 val
= readl(&cru
->clksel_con
[spiclk
->reg
]);
367 div
= extract_bits(val
, 7, spiclk
->div_shift
);
369 debug("%s: div 0x%x\n", __func__
, div
);
370 return DIV_TO_RATE(GPLL_HZ
, div
);
373 static ulong
rk3368_spi_set_clk(struct rk3368_cru
*cru
, ulong clk_id
, uint hz
)
375 const struct spi_clkreg
*spiclk
= NULL
;
378 src_clk_div
= DIV_ROUND_UP(GPLL_HZ
, hz
);
379 assert(src_clk_div
< 127);
382 case SCLK_SPI0
... SCLK_SPI2
:
383 spiclk
= &spi_clkregs
[clk_id
- SCLK_SPI0
];
387 error("%s: SPI clk-id %ld not supported\n", __func__
, clk_id
);
391 rk_clrsetreg(&cru
->clksel_con
[spiclk
->reg
],
392 ((0x7f << spiclk
->div_shift
) |
393 (0x1 << spiclk
->sel_shift
)),
394 ((src_clk_div
<< spiclk
->div_shift
) |
395 (1 << spiclk
->sel_shift
)));
397 return rk3368_spi_get_clk(cru
, clk_id
);
400 static ulong
rk3368_clk_get_rate(struct clk
*clk
)
402 struct rk3368_clk_priv
*priv
= dev_get_priv(clk
->dev
);
405 debug("%s: id %ld\n", __func__
, clk
->id
);
408 rate
= rkclk_pll_get_rate(priv
->cru
, CPLL
);
411 rate
= rkclk_pll_get_rate(priv
->cru
, GPLL
);
413 case SCLK_SPI0
... SCLK_SPI2
:
414 rate
= rk3368_spi_get_clk(priv
->cru
, clk
->id
);
416 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
419 rate
= rk3368_mmc_get_clk(priv
->cru
, clk
->id
);
429 static ulong
rk3368_clk_set_rate(struct clk
*clk
, ulong rate
)
431 __maybe_unused
struct rk3368_clk_priv
*priv
= dev_get_priv(clk
->dev
);
434 debug("%s id:%ld rate:%ld\n", __func__
, clk
->id
, rate
);
436 case SCLK_SPI0
... SCLK_SPI2
:
437 ret
= rk3368_spi_set_clk(priv
->cru
, clk
->id
, rate
);
439 #if IS_ENABLED(CONFIG_TPL_BUILD)
441 ret
= rk3368_ddr_set_clk(priv
->cru
, rate
);
444 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
447 ret
= rk3368_mmc_set_clk(clk
, rate
);
450 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
452 /* select the external clock */
453 ret
= rk3368_gmac_set_clk(priv
->cru
, clk
->id
, rate
);
463 static struct clk_ops rk3368_clk_ops
= {
464 .get_rate
= rk3368_clk_get_rate
,
465 .set_rate
= rk3368_clk_set_rate
,
468 static int rk3368_clk_probe(struct udevice
*dev
)
470 struct rk3368_clk_priv __maybe_unused
*priv
= dev_get_priv(dev
);
471 #if CONFIG_IS_ENABLED(OF_PLATDATA)
472 struct rk3368_clk_plat
*plat
= dev_get_platdata(dev
);
474 priv
->cru
= map_sysmem(plat
->dtd
.reg
[0], plat
->dtd
.reg
[1]);
476 #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
477 rkclk_init(priv
->cru
);
483 static int rk3368_clk_ofdata_to_platdata(struct udevice
*dev
)
485 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
486 struct rk3368_clk_priv
*priv
= dev_get_priv(dev
);
488 priv
->cru
= (struct rk3368_cru
*)devfdt_get_addr(dev
);
494 static int rk3368_clk_bind(struct udevice
*dev
)
498 /* The reset driver does not have a device node, so bind it here */
499 ret
= device_bind_driver(gd
->dm_root
, "rk3368_sysreset", "reset", &dev
);
501 error("bind RK3368 reset driver failed: ret=%d\n", ret
);
506 static const struct udevice_id rk3368_clk_ids
[] = {
507 { .compatible
= "rockchip,rk3368-cru" },
511 U_BOOT_DRIVER(rockchip_rk3368_cru
) = {
512 .name
= "rockchip_rk3368_cru",
514 .of_match
= rk3368_clk_ids
,
515 .priv_auto_alloc_size
= sizeof(struct rk3368_clk_priv
),
516 #if CONFIG_IS_ENABLED(OF_PLATDATA)
517 .platdata_auto_alloc_size
= sizeof(struct rk3368_clk_plat
),
519 .ofdata_to_platdata
= rk3368_clk_ofdata_to_platdata
,
520 .ops
= &rk3368_clk_ops
,
521 .bind
= rk3368_clk_bind
,
522 .probe
= rk3368_clk_probe
,