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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/clk/sunxi/clk_r40.c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
8 #include <clk-uclass.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-r40-ccu.h>
13 #include <dt-bindings/reset/sun8i-r40-ccu.h>
15 static struct ccu_clk_gate r40_gates
[] = {
16 [CLK_BUS_MMC0
] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1
] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2
] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3
] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0
] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1
] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2
] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3
] = GATE(0x060, BIT(23)),
24 [CLK_BUS_OTG
] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0
] = GATE(0x060, BIT(26)),
26 [CLK_BUS_EHCI1
] = GATE(0x060, BIT(27)),
27 [CLK_BUS_EHCI2
] = GATE(0x060, BIT(28)),
28 [CLK_BUS_OHCI0
] = GATE(0x060, BIT(29)),
29 [CLK_BUS_OHCI1
] = GATE(0x060, BIT(30)),
30 [CLK_BUS_OHCI2
] = GATE(0x060, BIT(31)),
32 [CLK_BUS_GMAC
] = GATE(0x064, BIT(17)),
34 [CLK_BUS_UART0
] = GATE(0x06c, BIT(16)),
35 [CLK_BUS_UART1
] = GATE(0x06c, BIT(17)),
36 [CLK_BUS_UART2
] = GATE(0x06c, BIT(18)),
37 [CLK_BUS_UART3
] = GATE(0x06c, BIT(19)),
38 [CLK_BUS_UART4
] = GATE(0x06c, BIT(20)),
39 [CLK_BUS_UART5
] = GATE(0x06c, BIT(21)),
40 [CLK_BUS_UART6
] = GATE(0x06c, BIT(22)),
41 [CLK_BUS_UART7
] = GATE(0x06c, BIT(23)),
43 [CLK_SPI0
] = GATE(0x0a0, BIT(31)),
44 [CLK_SPI1
] = GATE(0x0a4, BIT(31)),
45 [CLK_SPI2
] = GATE(0x0a8, BIT(31)),
46 [CLK_SPI3
] = GATE(0x0ac, BIT(31)),
48 [CLK_USB_PHY0
] = GATE(0x0cc, BIT(8)),
49 [CLK_USB_PHY1
] = GATE(0x0cc, BIT(9)),
50 [CLK_USB_PHY2
] = GATE(0x0cc, BIT(10)),
51 [CLK_USB_OHCI0
] = GATE(0x0cc, BIT(16)),
52 [CLK_USB_OHCI1
] = GATE(0x0cc, BIT(17)),
53 [CLK_USB_OHCI2
] = GATE(0x0cc, BIT(18)),
56 static struct ccu_reset r40_resets
[] = {
57 [RST_USB_PHY0
] = RESET(0x0cc, BIT(0)),
58 [RST_USB_PHY1
] = RESET(0x0cc, BIT(1)),
59 [RST_USB_PHY2
] = RESET(0x0cc, BIT(2)),
61 [RST_BUS_MMC0
] = RESET(0x2c0, BIT(8)),
62 [RST_BUS_MMC1
] = RESET(0x2c0, BIT(9)),
63 [RST_BUS_MMC2
] = RESET(0x2c0, BIT(10)),
64 [RST_BUS_MMC3
] = RESET(0x2c0, BIT(11)),
65 [RST_BUS_SPI0
] = RESET(0x2c0, BIT(20)),
66 [RST_BUS_SPI1
] = RESET(0x2c0, BIT(21)),
67 [RST_BUS_SPI2
] = RESET(0x2c0, BIT(22)),
68 [RST_BUS_SPI3
] = RESET(0x2c0, BIT(23)),
69 [RST_BUS_OTG
] = RESET(0x2c0, BIT(25)),
70 [RST_BUS_EHCI0
] = RESET(0x2c0, BIT(26)),
71 [RST_BUS_EHCI1
] = RESET(0x2c0, BIT(27)),
72 [RST_BUS_EHCI2
] = RESET(0x2c0, BIT(28)),
73 [RST_BUS_OHCI0
] = RESET(0x2c0, BIT(29)),
74 [RST_BUS_OHCI1
] = RESET(0x2c0, BIT(30)),
75 [RST_BUS_OHCI2
] = RESET(0x2c0, BIT(31)),
77 [RST_BUS_GMAC
] = RESET(0x2c4, BIT(17)),
79 [RST_BUS_UART0
] = RESET(0x2d8, BIT(16)),
80 [RST_BUS_UART1
] = RESET(0x2d8, BIT(17)),
81 [RST_BUS_UART2
] = RESET(0x2d8, BIT(18)),
82 [RST_BUS_UART3
] = RESET(0x2d8, BIT(19)),
83 [RST_BUS_UART4
] = RESET(0x2d8, BIT(20)),
84 [RST_BUS_UART5
] = RESET(0x2d8, BIT(21)),
85 [RST_BUS_UART6
] = RESET(0x2d8, BIT(22)),
86 [RST_BUS_UART7
] = RESET(0x2d8, BIT(23)),
89 static const struct ccu_desc r40_ccu_desc
= {
94 static int r40_clk_bind(struct udevice
*dev
)
96 return sunxi_reset_bind(dev
, ARRAY_SIZE(r40_resets
));
99 static const struct udevice_id r40_clk_ids
[] = {
100 { .compatible
= "allwinner,sun8i-r40-ccu",
101 .data
= (ulong
)&r40_ccu_desc
},
105 U_BOOT_DRIVER(clk_sun8i_r40
) = {
106 .name
= "sun8i_r40_ccu",
108 .of_match
= r40_clk_ids
,
109 .priv_auto_alloc_size
= sizeof(struct ccu_priv
),
110 .ops
= &sunxi_clk_ops
,
111 .probe
= sunxi_clk_probe
,
112 .bind
= r40_clk_bind
,