drivers/crypto/mv_cesa.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MV_CRYPTO_H__
   3 #define __MV_CRYPTO_H__
   4
   5 #define DIGEST_INITIAL_VAL_A    0xdd00
   6 #define DIGEST_INITIAL_VAL_B    0xdd04
   7 #define DIGEST_INITIAL_VAL_C    0xdd08
   8 #define DIGEST_INITIAL_VAL_D    0xdd0c
   9 #define DIGEST_INITIAL_VAL_E    0xdd10
  10 #define DES_CMD_REG             0xdd58
  11
  12 #define SEC_ACCEL_CMD           0xde00
  13 #define SEC_CMD_EN_SEC_ACCL0    (1 << 0)
  14 #define SEC_CMD_EN_SEC_ACCL1    (1 << 1)
  15 #define SEC_CMD_DISABLE_SEC     (1 << 2)
  16
  17 #define SEC_ACCEL_DESC_P0       0xde04
  18 #define SEC_DESC_P0_PTR(x)      (x)
  19
  20 #define SEC_ACCEL_DESC_P1       0xde14
  21 #define SEC_DESC_P1_PTR(x)      (x)
  22
  23 #define SEC_ACCEL_CFG           0xde08
  24 #define SEC_CFG_STOP_DIG_ERR    (1 << 0)
  25 #define SEC_CFG_CH0_W_IDMA      (1 << 7)
  26 #define SEC_CFG_CH1_W_IDMA      (1 << 8)
  27 #define SEC_CFG_ACT_CH0_IDMA    (1 << 9)
  28 #define SEC_CFG_ACT_CH1_IDMA    (1 << 10)
  29
  30 #define SEC_ACCEL_STATUS        0xde0c
  31 #define SEC_ST_ACT_0            (1 << 0)
  32 #define SEC_ST_ACT_1            (1 << 1)
  33
  34 /*
  35  * FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
  36  * 4.12. It looks like that it was part of an IRQ-controller in FPGA and
  37  * someone forgot to remove  it while switching to the core and moving to
  38  * SEC_ACCEL_INT_STATUS.
  39  */
  40 #define FPGA_INT_STATUS         0xdd68
  41 #define SEC_ACCEL_INT_STATUS    0xde20
  42 #define SEC_INT_AUTH_DONE       (1 << 0)
  43 #define SEC_INT_DES_E_DONE      (1 << 1)
  44 #define SEC_INT_AES_E_DONE      (1 << 2)
  45 #define SEC_INT_AES_D_DONE      (1 << 3)
  46 #define SEC_INT_ENC_DONE        (1 << 4)
  47 #define SEC_INT_ACCEL0_DONE     (1 << 5)
  48 #define SEC_INT_ACCEL1_DONE     (1 << 6)
  49 #define SEC_INT_ACC0_IDMA_DONE  (1 << 7)
  50 #define SEC_INT_ACC1_IDMA_DONE  (1 << 8)
  51
  52 #define SEC_ACCEL_INT_MASK      0xde24
  53
  54 #define AES_KEY_LEN     (8 * 4)
  55
  56 struct sec_accel_config {
  57
  58         u32 config;
  59 #define CFG_OP_MAC_ONLY         0
  60 #define CFG_OP_CRYPT_ONLY       1
  61 #define CFG_OP_MAC_CRYPT        2
  62 #define CFG_OP_CRYPT_MAC        3
  63 #define CFG_MACM_MD5            (4 << 4)
  64 #define CFG_MACM_SHA1           (5 << 4)
  65 #define CFG_MACM_HMAC_MD5       (6 << 4)
  66 #define CFG_MACM_HMAC_SHA1      (7 << 4)
  67 #define CFG_ENCM_DES            (1 << 8)
  68 #define CFG_ENCM_3DES           (2 << 8)
  69 #define CFG_ENCM_AES            (3 << 8)
  70 #define CFG_DIR_ENC             (0 << 12)
  71 #define CFG_DIR_DEC             (1 << 12)
  72 #define CFG_ENC_MODE_ECB        (0 << 16)
  73 #define CFG_ENC_MODE_CBC        (1 << 16)
  74 #define CFG_3DES_EEE            (0 << 20)
  75 #define CFG_3DES_EDE            (1 << 20)
  76 #define CFG_AES_LEN_128         (0 << 24)
  77 #define CFG_AES_LEN_192         (1 << 24)
  78 #define CFG_AES_LEN_256         (2 << 24)
  79 #define CFG_NOT_FRAG            (0 << 30)
  80 #define CFG_FIRST_FRAG          (1 << 30)
  81 #define CFG_LAST_FRAG           (2 << 30)
  82 #define CFG_MID_FRAG            (3 << 30)
  83
  84         u32 enc_p;
  85 #define ENC_P_SRC(x)            (x)
  86 #define ENC_P_DST(x)            ((x) << 16)
  87
  88         u32 enc_len;
  89 #define ENC_LEN(x)              (x)
  90
  91         u32 enc_key_p;
  92 #define ENC_KEY_P(x)            (x)
  93
  94         u32 enc_iv;
  95 #define ENC_IV_POINT(x)         ((x) << 0)
  96 #define ENC_IV_BUF_POINT(x)     ((x) << 16)
  97
  98         u32 mac_src_p;
  99 #define MAC_SRC_DATA_P(x)       (x)
 100 #define MAC_SRC_TOTAL_LEN(x)    ((x) << 16)
 101
 102         u32 mac_digest;
 103 #define MAC_DIGEST_P(x) (x)
 104 #define MAC_FRAG_LEN(x) ((x) << 16)
 105         u32 mac_iv;
 106 #define MAC_INNER_IV_P(x)       (x)
 107 #define MAC_OUTER_IV_P(x)       ((x) << 16)
 108 }__attribute__ ((packed));
 109         /*
 110          * /-----------\ 0
 111          * | ACCEL CFG |        4 * 8
 112          * |-----------| 0x20
 113          * | CRYPT KEY |        8 * 4
 114          * |-----------| 0x40
 115          * |  IV   IN  |        4 * 4
 116          * |-----------| 0x40 (inplace)
 117          * |  IV BUF   |        4 * 4
 118          * |-----------| 0x80
 119          * |  DATA IN  |        16 * x (max ->max_req_size)
 120          * |-----------| 0x80 (inplace operation)
 121          * |  DATA OUT |        16 * x (max ->max_req_size)
 122          * \-----------/ SRAM size
 123          */
 124
 125         /* Hashing memory map:
 126          * /-----------\ 0
 127          * | ACCEL CFG |        4 * 8
 128          * |-----------| 0x20
 129          * | Inner IV  |        5 * 4
 130          * |-----------| 0x34
 131          * | Outer IV  |        5 * 4
 132          * |-----------| 0x48
 133          * | Output BUF|        5 * 4
 134          * |-----------| 0x80
 135          * |  DATA IN  |        64 * x (max ->max_req_size)
 136          * \-----------/ SRAM size
 137          */
 138 #define SRAM_CONFIG             0x00
 139 #define SRAM_DATA_KEY_P         0x20
 140 #define SRAM_DATA_IV            0x40
 141 #define SRAM_DATA_IV_BUF        0x40
 142 #define SRAM_DATA_IN_START      0x80
 143 #define SRAM_DATA_OUT_START     0x80
 144
 145 #define SRAM_HMAC_IV_IN         0x20
 146 #define SRAM_HMAC_IV_OUT        0x34
 147 #define SRAM_DIGEST_BUF         0x48
 148
 149 #define SRAM_CFG_SPACE          0x80
 150
 151 #endif