drivers/ct69000.c

   1 /* ported from ctfb.c (linux kernel):
   2  * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
   3  *
   4  * Ported to U-Boot:
   5  * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 #ifdef CONFIG_VIDEO
  29
  30 #include <pci.h>
  31 #include <video_fb.h>
  32 #include "videomodes.h"
  33
  34 #ifdef CONFIG_VIDEO_CT69000
  35
  36 /* debug */
  37 #undef VGA_DEBUG
  38 #undef VGA_DUMP_REG
  39 #ifdef VGA_DEBUG
  40 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  41 #else
  42 #define PRINTF(fmt,args...)
  43 #endif
  44
  45 /* Macros */
  46 #ifndef min
  47 #define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
  48 #endif
  49 #ifndef max
  50 #define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
  51 #endif
  52 #ifdef minmax
  53 #error "term minmax already used."
  54 #endif
  55 #define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
  56 #define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
  57
  58 /* CT Register Offsets */
  59 #define CT_AR_O                 0x3c0   /* Index and Data write port of the attribute Registers */
  60 #define CT_GR_O                 0x3ce   /* Index port of the Graphic Controller Registers */
  61 #define CT_SR_O                 0x3c4   /* Index port of the Sequencer Controller */
  62 #define CT_CR_O                 0x3d4   /* Index port of the CRT Controller */
  63 #define CT_XR_O                 0x3d6   /* Extended Register index */
  64 #define CT_MSR_W_O              0x3c2   /* Misc. Output Register (write only) */
  65 #define CT_LUT_MASK_O           0x3c6   /* Color Palette Mask */
  66 #define CT_LUT_START_O          0x3c8   /* Color Palette Write Mode Index */
  67 #define CT_LUT_RGB_O            0x3c9   /* Color Palette Data Port */
  68 #define CT_STATUS_REG0_O        0x3c2   /* Status Register 0 (read only) */
  69 #define CT_STATUS_REG1_O        0x3da   /* Input Status Register 1 (read only) */
  70
  71 #define CT_FP_O                 0x3d0   /* Index port of the Flat panel Registers */
  72 #define CT_MR_O                 0x3d2   /* Index Port of the Multimedia Extension */
  73
  74 /* defines for the memory mapped registers */
  75 #define BR00_o          0x400000        /* Source and Destination Span Register */
  76 #define BR01_o          0x400004        /* Pattern/Source Expansion Background Color & Transparency Key Register */
  77 #define BR02_o          0x400008        /* Pattern/Source Expansion Foreground Color Register */
  78 #define BR03_o          0x40000C        /* Monochrome Source Control Register */
  79 #define BR04_o          0x400010        /* BitBLT Control Register */
  80 #define BR05_o          0x400014        /* Pattern Address Registe */
  81 #define BR06_o          0x400018        /* Source Address Register */
  82 #define BR07_o          0x40001C        /* Destination Address Register */
  83 #define BR08_o          0x400020        /* Destination Width & Height Register */
  84 #define BR09_o          0x400024        /* Source Expansion Background Color & Transparency Key Register */
  85 #define BR0A_o          0x400028        /* Source Expansion Foreground Color Register */
  86
  87 #define CURSOR_SIZE     0x1000  /* in KByte for HW Cursor */
  88 #define PATTERN_ADR     (pGD->dprBase + CURSOR_SIZE)    /* pattern Memory after Cursor Memory */
  89 #define PATTERN_SIZE    8*8*4   /* 4 Bytes per Pixel 8 x 8 Pixel */
  90 #define ACCELMEMORY     (CURSOR_SIZE + PATTERN_SIZE)    /* reserved Memory for BITBlt and hw cursor */
  91
  92 /* Some Mode definitions */
  93 #define FB_SYNC_HOR_HIGH_ACT    1       /* horizontal sync high active  */
  94 #define FB_SYNC_VERT_HIGH_ACT   2       /* vertical sync high active    */
  95 #define FB_SYNC_EXT             4       /* external sync                */
  96 #define FB_SYNC_COMP_HIGH_ACT   8       /* composite sync high active   */
  97 #define FB_SYNC_BROADCAST       16      /* broadcast video timings      */
  98                                         /* vtotal = 144d/288n/576i => PAL  */
  99                                         /* vtotal = 121d/242n/484i => NTSC */
 100 #define FB_SYNC_ON_GREEN        32      /* sync on green */
 101
 102 #define FB_VMODE_NONINTERLACED  0       /* non interlaced */
 103 #define FB_VMODE_INTERLACED     1       /* interlaced   */
 104 #define FB_VMODE_DOUBLE         2       /* double scan */
 105 #define FB_VMODE_MASK           255
 106
 107 #define FB_VMODE_YWRAP          256     /* ywrap instead of panning     */
 108 #define FB_VMODE_SMOOTH_XPAN    512     /* smooth xpan possible (internally used) */
 109 #define FB_VMODE_CONUPDATE      512     /* don't update x/yoffset       */
 110
 111 #define text                    0
 112 #define fntwidth                8
 113
 114 /* table for VGA Initialization  */
 115 typedef struct {
 116         const unsigned char reg;
 117         const unsigned char val;
 118 } CT_CFG_TABLE;
 119
 120 /* this table provides some basic initialisations such as Memory Clock etc */
 121 static CT_CFG_TABLE xreg[] = {
 122         {0x09, 0x01},           /* CRT Controller Extensions Enable */
 123         {0x0A, 0x02},           /* Frame Buffer Mapping */
 124         {0x0B, 0x01},           /* PCI Write Burst support */
 125         {0x20, 0x00},           /* BitBLT Configuration */
 126         {0x40, 0x03},           /* Memory Access Control */
 127         {0x60, 0x00},           /* Video Pin Control */
 128         {0x61, 0x00},           /* DPMS Synch control */
 129         {0x62, 0x00},           /* GPIO Pin Control */
 130         {0x63, 0xBD},           /* GPIO Pin Data */
 131         {0x67, 0x00},           /* Pin Tri-State */
 132         {0x80, 0x80},           /* Pixel Pipeline Config 0 register */
 133         {0xA0, 0x00},           /* Cursor 1 Control Reg */
 134         {0xA1, 0x00},           /* Cursor 1 Vertical Extension Reg */
 135         {0xA2, 0x00},           /* Cursor 1 Base Address Low */
 136         {0xA3, 0x00},           /* Cursor 1 Base Address High */
 137         {0xA4, 0x00},           /* Cursor 1 X-Position Low */
 138         {0xA5, 0x00},           /* Cursor 1 X-Position High */
 139         {0xA6, 0x00},           /* Cursor 1 Y-Position Low */
 140         {0xA7, 0x00},           /* Cursor 1 Y-Position High */
 141         {0xA8, 0x00},           /* Cursor 2 Control Reg */
 142         {0xA9, 0x00},           /* Cursor 2 Vertical Extension Reg */
 143         {0xAA, 0x00},           /* Cursor 2 Base Address Low */
 144         {0xAB, 0x00},           /* Cursor 2 Base Address High */
 145         {0xAC, 0x00},           /* Cursor 2 X-Position Low */
 146         {0xAD, 0x00},           /* Cursor 2 X-Position High */
 147         {0xAE, 0x00},           /* Cursor 2 Y-Position Low */
 148         {0xAF, 0x00},           /* Cursor 2 Y-Position High */
 149         {0xC0, 0x7D},           /* Dot Clock 0 VCO M-Divisor */
 150         {0xC1, 0x07},           /* Dot Clock 0 VCO N-Divisor */
 151         {0xC3, 0x34},           /* Dot Clock 0 Divisor select */
 152         {0xC4, 0x55},           /* Dot Clock 1 VCO M-Divisor */
 153         {0xC5, 0x09},           /* Dot Clock 1 VCO N-Divisor */
 154         {0xC7, 0x24},           /* Dot Clock 1 Divisor select */
 155         {0xC8, 0x7D},           /* Dot Clock 2 VCO M-Divisor */
 156         {0xC9, 0x07},           /* Dot Clock 2 VCO N-Divisor */
 157         {0xCB, 0x34},           /* Dot Clock 2 Divisor select */
 158         {0xCC, 0x38},           /* Memory Clock 0 VCO M-Divisor */
 159         {0xCD, 0x03},           /* Memory Clock 0 VCO N-Divisor */
 160         {0xCE, 0x90},           /* Memory Clock 0 Divisor select */
 161         {0xCF, 0x06},           /* Clock Config */
 162         {0xD0, 0x0F},           /* Power Down */
 163         {0xD1, 0x01},           /* Power Down BitBLT */
 164         {0xFF, 0xFF}            /* end of table */
 165 };
 166 /* Clock Config:
 167  * =============
 168  *
 169  * PD Registers:
 170  * -------------
 171  * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
 172  * They are encoded as follows:
 173  *
 174  * +---+--------------+
 175  * | 2 | Loop Divisor |
 176  * +---+--------------+
 177  * | 1 | 1            |
 178  * +---+--------------+
 179  * | 0 | 4            |
 180  * +---+--------------+
 181  * Note: The Memory Clock does not have a Loop Divisor.
 182  * +---+---+---+--------------+
 183  * | 6 | 5 | 4 | Post Divisor |
 184  * +---+---+---+--------------+
 185  * | 0 | 0 | 0 | 1            |
 186  * +---+---+---+--------------+
 187  * | 0 | 0 | 1 | 2            |
 188  * +---+---+---+--------------+
 189  * | 0 | 1 | 0 | 4            |
 190  * +---+---+---+--------------+
 191  * | 0 | 1 | 1 | 8            |
 192  * +---+---+---+--------------+
 193  * | 1 | 0 | 0 | 16           |
 194  * +---+---+---+--------------+
 195  * | 1 | 0 | 1 | 32           |
 196  * +---+---+---+--------------+
 197  * | 1 | 1 | X | reserved     |
 198  * +---+---+---+--------------+
 199  *
 200  * All other bits are reserved in these registers.
 201  *
 202  * Clock VCO M Registers:
 203  * ----------------------
 204  * These Registers contain the M Value -2.
 205  *
 206  * Clock VCO N Registers:
 207  * ----------------------
 208  * These Registers contain the N Value -2.
 209  *
 210  * Formulas:
 211  * ---------
 212  * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
 213  * Fout = Fvco / Post Divisor
 214  *
 215  * Dot Clk0 (default 25MHz):
 216  * -------------------------
 217  * Fvco = 14.318 * 127 / 9 = 202.045MHz
 218  * Fout = 202.045MHz / 8 = 25.25MHz
 219  * Post Divisor = 8
 220  * Loop Divisor = 1
 221  * XRC0 = (M - 2) = 125 = 0x7D
 222  * XRC1 = (N - 2) = 7   = 0x07
 223  * XRC3 =                 0x34
 224  *
 225  * Dot Clk1 (default 28MHz):
 226  * -------------------------
 227  * Fvco = 14.318 * 87 / 11 = 113.24MHz
 228  * Fout = 113.24MHz / 4 = 28.31MHz
 229  * Post Divisor = 4
 230  * Loop Divisor = 1
 231  * XRC4 = (M - 2) = 85 = 0x55
 232  * XRC5 = (N - 2) = 9  = 0x09
 233  * XRC7 =                0x24
 234  *
 235  * Dot Clk2 (variable for extended modes set to 25MHz):
 236  * ----------------------------------------------------
 237  * Fvco = 14.318 * 127 / 9 = 202.045MHz
 238  * Fout = 202.045MHz / 8 = 25.25MHz
 239  * Post Divisor = 8
 240  * Loop Divisor = 1
 241  * XRC8 = (M - 2) = 125 = 0x7D
 242  * XRC9 = (N - 2) = 7   = 0x07
 243  * XRCB =                 0x34
 244  *
 245  * Memory Clk for most modes >50MHz:
 246  * ----------------------------------
 247  * Fvco = 14.318 * 58 / 5 = 166MHz
 248  * Fout = 166MHz / 2      = 83MHz
 249  * Post Divisor = 2
 250  * XRCC = (M - 2) = 57  = 0x38
 251  * XRCD = (N - 2) = 3   = 0x03
 252  * XRCE =                 0x90
 253  *
 254  * Note Bit7 enables the clock source from the VCO
 255  *
 256  */
 257
 258 /*******************************************************************
 259  * Chips struct
 260  *******************************************************************/
 261 struct ctfb_chips_properties {
 262         int device_id;          /* PCI Device ID */
 263         unsigned long max_mem;  /* memory for frame buffer */
 264         int vld_set;            /* value of VLD if bit2 in clock control is set */
 265         int vld_not_set;        /* value of VLD if bit2 in clock control is set */
 266         int mn_diff;            /* difference between M/N Value + mn_diff = M/N Register */
 267         int mn_min;             /* min value of M/N Value */
 268         int mn_max;             /* max value of M/N Value */
 269         int vco_min;            /* VCO Min in MHz */
 270         int vco_max;            /* VCO Max in MHz */
 271 };
 272
 273 static const struct ctfb_chips_properties chips[] = {
 274         {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
 275 #ifdef CONFIG_USE_CPCIDVI
 276         {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
 277 #endif
 278         {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220},  /* NOT TESTED */
 279         {0, 0, 0, 0, 0, 0, 0, 0, 0}     /* Terminator */
 280 };
 281
 282 /*
 283  * The Graphic Device
 284  */
 285 GraphicDevice ctfb;
 286
 287 /*******************************************************************************
 288 *
 289 * Low Level Routines
 290 */
 291
 292 /*******************************************************************************
 293 *
 294 * Read CT ISA register
 295 */
 296 #ifdef VGA_DEBUG
 297 static unsigned char
 298 ctRead (unsigned short index)
 299 {
 300         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 301         if (index == CT_AR_O)
 302                 /* synch the Flip Flop */
 303                 in8 (pGD->isaBase + CT_STATUS_REG1_O);
 304
 305         return (in8 (pGD->isaBase + index));
 306 }
 307 #endif
 308 /*******************************************************************************
 309 *
 310 * Write CT ISA register
 311 */
 312 static void
 313 ctWrite (unsigned short index, unsigned char val)
 314 {
 315         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 316
 317         out8 ((pGD->isaBase + index), val);
 318 }
 319
 320 /*******************************************************************************
 321 *
 322 * Read CT ISA register indexed
 323 */
 324 static unsigned char
 325 ctRead_i (unsigned short index, char reg)
 326 {
 327         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 328         if (index == CT_AR_O)
 329                 /* synch the Flip Flop */
 330                 in8 (pGD->isaBase + CT_STATUS_REG1_O);
 331         out8 ((pGD->isaBase + index), reg);
 332         return (in8 (pGD->isaBase + index + 1));
 333 }
 334
 335 /*******************************************************************************
 336 *
 337 * Write CT ISA register indexed
 338 */
 339 static void
 340 ctWrite_i (unsigned short index, char reg, char val)
 341 {
 342         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 343         if (index == CT_AR_O) {
 344                 /* synch the Flip Flop */
 345                 in8 (pGD->isaBase + CT_STATUS_REG1_O);
 346                 out8 ((pGD->isaBase + index), reg);
 347                 out8 ((pGD->isaBase + index), val);
 348         } else {
 349                 out8 ((pGD->isaBase + index), reg);
 350                 out8 ((pGD->isaBase + index + 1), val);
 351         }
 352 }
 353
 354 /*******************************************************************************
 355 *
 356 * Write a table of CT ISA register
 357 */
 358 static void
 359 ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
 360 {
 361         while (regTab->reg != 0xFF) {
 362                 ctWrite_i (index, regTab->reg, regTab->val);
 363                 regTab++;
 364         }
 365 }
 366
 367 /*****************************************************************************/
 368 static void
 369 SetArRegs (void)
 370 {
 371         int i, tmp;
 372
 373         for (i = 0; i < 0x10; i++)
 374                 ctWrite_i (CT_AR_O, i, i);
 375         if (text)
 376                 tmp = 0x04;
 377         else
 378                 tmp = 0x41;
 379
 380         ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
 381         ctWrite_i (CT_AR_O, 0x11, 0x00);        /* Overscan Color Register */
 382         ctWrite_i (CT_AR_O, 0x12, 0x0f);        /* Memory Plane Enable Register */
 383         if (fntwidth == 9)
 384                 tmp = 0x08;
 385         else
 386                 tmp = 0x00;
 387         ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
 388         ctWrite_i (CT_AR_O, 0x14, 0x00);        /* Color Select Register    */
 389         ctWrite (CT_AR_O, 0x20);        /* enable video             */
 390 }
 391
 392 /*****************************************************************************/
 393 static void
 394 SetGrRegs (void)
 395 {                               /* Set Graphics Mode */
 396         int i;
 397
 398         for (i = 0; i < 0x05; i++)
 399                 ctWrite_i (CT_GR_O, i, 0);
 400         if (text) {
 401                 ctWrite_i (CT_GR_O, 0x05, 0x10);
 402                 ctWrite_i (CT_GR_O, 0x06, 0x02);
 403         } else {
 404                 ctWrite_i (CT_GR_O, 0x05, 0x40);
 405                 ctWrite_i (CT_GR_O, 0x06, 0x05);
 406         }
 407         ctWrite_i (CT_GR_O, 0x07, 0x0f);
 408         ctWrite_i (CT_GR_O, 0x08, 0xff);
 409 }
 410
 411 /*****************************************************************************/
 412 static void
 413 SetSrRegs (void)
 414 {
 415         int tmp = 0;
 416
 417         ctWrite_i (CT_SR_O, 0x00, 0x00);        /* reset */
 418         /*rr( sr, 0x01, tmp );
 419            if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
 420            wr( sr, 0x01, tmp );  */
 421         if (fntwidth == 8)
 422                 ctWrite_i (CT_SR_O, 0x01, 0x01);        /* Clocking Mode Register */
 423         else
 424                 ctWrite_i (CT_SR_O, 0x01, 0x00);        /* Clocking Mode Register */
 425         ctWrite_i (CT_SR_O, 0x02, 0x0f);        /* Enable CPU wr access to given memory plane */
 426         ctWrite_i (CT_SR_O, 0x03, 0x00);        /* Character Map Select Register */
 427         if (text)
 428                 tmp = 0x02;
 429         else
 430                 tmp = 0x0e;
 431         ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
 432                                            total VGA memory beyond the first 64KB and set
 433                                            fb mapping mode. */
 434         ctWrite_i (CT_SR_O, 0x00, 0x03);        /* enable */
 435 }
 436
 437 /*****************************************************************************/
 438 static void
 439 SetBitsPerPixelIntoXrRegs (int bpp)
 440 {
 441         unsigned int n = (bpp >> 3), tmp;       /* only for 15, 8, 16, 24 bpp */
 442         static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
 443         static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 };    /* mask */
 444         static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
 445         if (bpp == 15)
 446                 n = 0;
 447         tmp = ctRead_i (CT_XR_O, 0x20);
 448         tmp &= off[n];
 449         tmp |= on[n];
 450         ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
 451         ctWrite_i (CT_XR_O, 0x81, md[n]);
 452 }
 453
 454 /*****************************************************************************/
 455 static void
 456 SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
 457 {                               /* he -le-   ht|0    hd -ri- hs     -h-      he */
 458         unsigned char cr[0x7a];
 459         int i, tmp;
 460         unsigned int hd, hs, he, ht, hbe;       /* Horizontal.  */
 461         unsigned int vd, vs, ve, vt;    /* vertical */
 462         unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
 463         unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
 464         unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
 465         unsigned int HorizontalEqualizationPulses;
 466         unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
 467
 468         const int LineCompare = 0x3ff;
 469         unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor   */
 470         unsigned int RAMDAC_BlankPedestalEnable = 0;    /* 1=en-, 0=disable, see XR82 */
 471
 472         hd = (var->xres) / 8;   /* HDisp.  */
 473         hs = (var->xres + var->right_margin) / 8;       /* HsStrt  */
 474         he = (var->xres + var->right_margin + var->hsync_len) / 8;      /* HsEnd   */
 475         ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8;   /* HTotal  */
 476         hbe = ht - 1;           /* HBlankEnable todo docu wants ht here, but it does not work */
 477         /* ve -up-  vt|0    vd -lo- vs     -v-      ve */
 478         vd = var->yres;         /* VDisplay   */
 479         vs = var->yres + var->lower_margin;     /* VSyncStart */
 480         ve = var->yres + var->lower_margin + var->vsync_len;    /* VSyncEnd */
 481         vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;        /* VTotal  */
 482         bpp = bits_per_pixel;
 483         dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
 484         interlaced = var->vmode & FB_VMODE_INTERLACED;
 485         bcast = var->sync & FB_SYNC_BROADCAST;
 486         CrtHalfLine = bcast ? (hd >> 1) : 0;
 487         BlDelayCtrl = bcast ? 1 : 0;
 488         CompSyncCharClkDelay = 0;       /* 2 bit */
 489         CompSyncPixelClkDelay = 0;      /* 3 bit */
 490         if (bcast) {
 491                 NTSC_PAL_HorizontalPulseWidth = 7;      /*( var->hsync_len >> 1 ) + 1 */
 492                 HorizontalEqualizationPulses = 0;       /* inverse value */
 493                 HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
 494                 HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
 495         } else {
 496                 NTSC_PAL_HorizontalPulseWidth = 0;
 497                 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
 498                  * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
 499                 HorizontalEqualizationPulses = 1;       /* inverse value */
 500                 HorizontalSerration1Start = 0;  /* ( ht >> 1 ) */
 501                 HorizontalSerration2Start = 0;  /* ( ht >> 1 ) */
 502         }
 503
 504         if (bpp == 15)
 505                 bpp = 16;
 506         wd = var->xres * bpp / 64;      /* double words per line */
 507         if (interlaced) {       /* we divide all vertical timings, exept vd */
 508                 vs >>= 1;
 509                 ve >>= 1;
 510                 vt >>= 1;
 511         }
 512         memset (cr, 0, sizeof (cr));
 513         cr[0x00] = 0xff & (ht - 5);
 514         cr[0x01] = hd - 1;      /* soll:4f ist 59 */
 515         cr[0x02] = hd;
 516         cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd  */
 517         cr[0x04] = hs;
 518         cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
 519         cr[0x06] = (vt - 2) & 0xFF;
 520         cr[0x30] = (vt - 2) >> 8;
 521         cr[0x07] = ((vt & 0x100) >> 8)
 522             | ((vd & 0x100) >> 7)
 523             | ((vs & 0x100) >> 6)
 524             | ((vs & 0x100) >> 5)
 525             | ((LineCompare & 0x100) >> 4)
 526             | ((vt & 0x200) >> 4)
 527             | ((vd & 0x200) >> 3)
 528             | ((vs & 0x200) >> 2);
 529         cr[0x08] = 0x00;
 530         cr[0x09] = (dblscan << 7)
 531             | ((LineCompare & 0x200) >> 3)
 532             | ((vs & 0x200) >> 4)
 533             | (TextScanLines - 1);
 534         cr[0x10] = vs & 0xff;   /* VSyncPulseStart */
 535         cr[0x32] = (vs & 0xf00) >> 8;   /* VSyncPulseStart */
 536         cr[0x11] = (ve & 0x0f); /* | 0x20;      */
 537         cr[0x12] = (vd - 1) & 0xff;     /* LineCount  */
 538         cr[0x31] = ((vd - 1) & 0xf00) >> 8;     /* LineCount */
 539         cr[0x13] = wd & 0xff;
 540         cr[0x41] = (wd & 0xf00) >> 8;
 541         cr[0x15] = vs & 0xff;
 542         cr[0x33] = (vs & 0xf00) >> 8;
 543         cr[0x38] = (0x100 & (ht - 5)) >> 8;
 544         cr[0x3C] = 0xc0 & hbe;
 545         cr[0x16] = (vt - 1) & 0xff;     /* vbe - docu wants vt here, */
 546         cr[0x17] = 0xe3;        /* but it does not work */
 547         cr[0x18] = 0xff & LineCompare;
 548         cr[0x22] = 0xff;        /* todo? */
 549         cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00;    /* check:0xa6  */
 550         cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
 551             | (BlDelayCtrl << 5)
 552             | ((0x03 & CompSyncCharClkDelay) << 3)
 553             | (0x07 & CompSyncPixelClkDelay);   /* todo: see XR82 */
 554         cr[0x72] = HorizontalSerration1Start;
 555         cr[0x73] = HorizontalSerration2Start;
 556         cr[0x74] = (HorizontalEqualizationPulses << 5)
 557             | NTSC_PAL_HorizontalPulseWidth;
 558         /* todo: ct69000 has also 0x75-79 */
 559         /* now set the registers */
 560         for (i = 0; i <= 0x0d; i++) {   /*CR00 .. CR0D */
 561                 ctWrite_i (CT_CR_O, i, cr[i]);
 562         }
 563         for (i = 0x10; i <= 0x18; i++) {        /*CR10 .. CR18 */
 564                 ctWrite_i (CT_CR_O, i, cr[i]);
 565         }
 566         i = 0x22;               /*CR22 */
 567         ctWrite_i (CT_CR_O, i, cr[i]);
 568         for (i = 0x30; i <= 0x33; i++) {        /*CR30 .. CR33 */
 569                 ctWrite_i (CT_CR_O, i, cr[i]);
 570         }
 571         i = 0x38;               /*CR38 */
 572         ctWrite_i (CT_CR_O, i, cr[i]);
 573         i = 0x3C;               /*CR3C */
 574         ctWrite_i (CT_CR_O, i, cr[i]);
 575         for (i = 0x40; i <= 0x41; i++) {        /*CR40 .. CR41 */
 576                 ctWrite_i (CT_CR_O, i, cr[i]);
 577         }
 578         for (i = 0x70; i <= 0x74; i++) {        /*CR70 .. CR74 */
 579                 ctWrite_i (CT_CR_O, i, cr[i]);
 580         }
 581         tmp = ctRead_i (CT_CR_O, 0x40);
 582         tmp &= 0x0f;
 583         tmp |= 0x80;
 584         ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
 585 }
 586
 587 /* pixelclock control */
 588
 589 /*****************************************************************************
 590  We have a rational number p/q and need an m/n which is very close to p/q
 591  but has m and n within mnmin and mnmax. We have no floating point in the
 592  kernel. We can use long long without divide. And we have time to compute...
 593 ******************************************************************************/
 594 static unsigned int
 595 FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
 596                      unsigned int mnmax, unsigned int *pm, unsigned int *pn)
 597 {
 598         /* this code is not for general purpose usable but good for our number ranges */
 599         unsigned int n = mnmin, m = 0;
 600         long long int L = 0, P = p, Q = q, H = P >> 1;
 601         long long int D = 0x7ffffffffffffffLL;
 602         for (n = mnmin; n <= mnmax; n++) {
 603                 m = mnmin;      /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
 604                 L = P * n - m * Q;      /* n * vco - m * fref should be near 0 */
 605                 while (L > 0 && m < mnmax) {
 606                         L -= q; /* difference is greater as 0 subtract fref */
 607                         m++;    /* and increment m */
 608                 }
 609                 /* difference is less or equal than 0 or m > maximum */
 610                 if (m > mnmax)
 611                         break;  /* no solution: if we increase n we get the same situation */
 612                 /* L is <= 0 now */
 613                 if (-L > H && m > mnmin) {      /* if difference > the half fref */
 614                         L += q; /* we take the situation before */
 615                         m--;    /* because its closer to 0 */
 616                 }
 617                 L = (L < 0) ? -L : +L;  /* absolute value */
 618                 if (D < L)      /* if last difference was better take next n */
 619                         continue;
 620                 D = L;
 621                 *pm = m;
 622                 *pn = n;        /*  keep improved data */
 623                 if (D == 0)
 624                         break;  /* best result we can get */
 625         }
 626         return (unsigned int) (0xffffffff & D);
 627 }
 628
 629 /* that is the hardware < 69000 we have to manage
 630  +---------+  +-------------------+  +----------------------+  +--+
 631  | REFCLK  |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
 632  | 14.3MHz |  |(NTSCDS) (÷1, ÷5)  |  |Select (RDS) (÷1, ÷4) |  |  |  |
 633  +---------+  +-------------------+  +----------------------+  +--+  |
 634   ___________________________________________________________________|
 635  |
 636  |                                    fvco                      fout
 637  | +--------+  +------------+  +-----+     +-------------------+   +----+
 638  +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
 639  +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
 640  | +--------+  +------------+  +-----+  |  +-------------------+   +----+
 641  |                                      |
 642  |    +--+   +---------------+          |
 643  |____|÷M|___|VCO Loop Divide|__________|
 644       |  |   |(VLD)(÷4, ÷16) |
 645       +--+   +---------------+
 646 ****************************************************************************
 647   that is the hardware >= 69000 we have to manage
 648  +---------+  +--+
 649  | REFCLK  |__|÷N|__
 650  | 14.3MHz |  |  |  |
 651  +---------+  +--+  |
 652   __________________|
 653  |
 654  |                                    fvco                      fout
 655  | +--------+  +------------+  +-----+     +-------------------+   +----+
 656  +-| Phase  |__|Charge Pump |__| VCO |_____|Post Divisor (PD)  |___|CLK |--->
 657  +-| Detect |  |& Filter VCO|  |     |  |  |÷1, 2, 4, 8, 16, 32|   |    |
 658  | +--------+  +------------+  +-----+  |  +-------------------+   +----+
 659  |                                      |
 660  |    +--+   +---------------+          |
 661  |____|÷M|___|VCO Loop Divide|__________|
 662       |  |   |(VLD)(÷1, ÷4)  |
 663       +--+   +---------------+
 664
 665
 666 */
 667
 668 #define VIDEO_FREF 14318180;    /* Hz  */
 669 /*****************************************************************************/
 670 static int
 671 ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
 672 {
 673         unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
 674         i = 0;
 675         pixclock = -1;
 676         fref = VIDEO_FREF;
 677         m = ctRead_i (CT_XR_O, 0xc8);
 678         n = ctRead_i (CT_XR_O, 0xc9);
 679         m -= param->mn_diff;
 680         n -= param->mn_diff;
 681         xr_cb = ctRead_i (CT_XR_O, 0xcb);
 682         PD = (0x70 & xr_cb) >> 4;
 683         pd = 1;
 684         for (i = 0; i < PD; i++) {
 685                 pd *= 2;
 686         }
 687         vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
 688         if (n * vld * m) {
 689                 unsigned long long p = 1000000000000LL * pd * n;
 690                 unsigned long long q = (long long) fref * vld * m;
 691                 while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
 692                         p >>= 1;        /* can't divide with long long so we scale down */
 693                         q >>= 1;
 694                 }
 695                 pixclock = (unsigned) p / (unsigned) q;
 696         } else
 697                 printf ("Invalid data in xr regs.\n");
 698         return pixclock;
 699 }
 700
 701 /*****************************************************************************/
 702 static void
 703 FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
 704                               struct ctfb_chips_properties *param)
 705 {
 706         unsigned int m, n, vld, pd, PD, fref, xr_cb;
 707         unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
 708         unsigned int pfreq, fvco, new_pixclock;
 709         unsigned int D,nback,mback;
 710
 711         fref = VIDEO_FREF;
 712         pd = 1;
 713         PD = 0;
 714         fvcomin = param->vco_min;
 715         fvcomax = param->vco_max;       /* MHz */
 716         pclckmin = 1000000 / fvcomax + 1;       /*   4546 */
 717         pclckmax = 32000000 / fvcomin - 1;      /* 666665 */
 718         pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
 719         pfreq = 250 * (4000000000U / pclk);
 720         fvco = pfreq;           /* Hz */
 721         new_pixclock = 0;
 722         while (fvco < fvcomin * 1000000) {
 723                 /* double VCO starting with the pixelclock frequency
 724                  * as long as it is lower than the minimal VCO frequency */
 725                 fvco *= 2;
 726                 pd *= 2;
 727                 PD++;
 728         }
 729         /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
 730         /* first try */
 731         vld = param->vld_set;
 732         D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
 733         mback=m;
 734         nback=n;
 735         /* second try */
 736         vld = param->vld_not_set;
 737         if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) {    /* rds = 1 */
 738                 /* first try was better */
 739                 m=mback;
 740                 n=nback;
 741                 vld = param->vld_set;
 742         }
 743         m += param->mn_diff;
 744         n += param->mn_diff;
 745         PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
 746         xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
 747         /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
 748          * written, and in order from XRC8 to XRCB, before the hardware will
 749          * update the synthesizer s settings.
 750          */
 751         ctWrite_i (CT_XR_O, 0xc8, m);
 752         ctWrite_i (CT_XR_O, 0xc9, n);   /* xrca does not exist in CT69000 and CT69030 */
 753         ctWrite_i (CT_XR_O, 0xca, 0);   /* because of a hw bug I guess, but we write */
 754         ctWrite_i (CT_XR_O, 0xcb, xr_cb);       /* 0 to it for savety */
 755         new_pixclock = ReadPixClckFromXrRegsBack (param);
 756         PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
 757                 pixelclock, new_pixclock);
 758 }
 759
 760 /*****************************************************************************/
 761 static void
 762 SetMsrRegs (struct ctfb_res_modes *mode)
 763 {
 764         unsigned char h_synch_high, v_synch_high;
 765
 766         h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40;  /* horizontal Synch High active */
 767         v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
 768         ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
 769         /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
 770          * Selects the upper 64KB page.Bit5=1
 771          * CLK2 (left reserved in standard VGA) Bit3|2=1|0
 772          * Disables CPU access to frame buffer. Bit1=0
 773          * Sets the I/O address decode for ST01, FCR, and all CR registers
 774          * to the 3Dx I/O address range (CGA emulation). Bit0=1
 775          */
 776 }
 777
 778 /************************************************************************************/
 779 #ifdef VGA_DUMP_REG
 780
 781 static void
 782 ctDispRegs (unsigned short index, int from, int to)
 783 {
 784         unsigned char status;
 785         int i;
 786
 787         for (i = from; i < to; i++) {
 788                 status = ctRead_i (index, i);
 789                 printf ("%02X: is %02X\n", i, status);
 790         }
 791 }
 792
 793 void
 794 video_dump_reg (void)
 795 {
 796         int i;
 797
 798         printf ("Extended Regs:\n");
 799         ctDispRegs (CT_XR_O, 0, 0xC);
 800         ctDispRegs (CT_XR_O, 0xe, 0xf);
 801         ctDispRegs (CT_XR_O, 0x20, 0x21);
 802         ctDispRegs (CT_XR_O, 0x40, 0x50);
 803         ctDispRegs (CT_XR_O, 0x60, 0x64);
 804         ctDispRegs (CT_XR_O, 0x67, 0x68);
 805         ctDispRegs (CT_XR_O, 0x70, 0x72);
 806         ctDispRegs (CT_XR_O, 0x80, 0x83);
 807         ctDispRegs (CT_XR_O, 0xA0, 0xB0);
 808         ctDispRegs (CT_XR_O, 0xC0, 0xD3);
 809         printf ("Sequencer Regs:\n");
 810         ctDispRegs (CT_SR_O, 0, 0x8);
 811         printf ("Graphic Regs:\n");
 812         ctDispRegs (CT_GR_O, 0, 0x9);
 813         printf ("CRT Regs:\n");
 814         ctDispRegs (CT_CR_O, 0, 0x19);
 815         ctDispRegs (CT_CR_O, 0x22, 0x23);
 816         ctDispRegs (CT_CR_O, 0x30, 0x34);
 817         ctDispRegs (CT_CR_O, 0x38, 0x39);
 818         ctDispRegs (CT_CR_O, 0x3C, 0x3D);
 819         ctDispRegs (CT_CR_O, 0x40, 0x42);
 820         ctDispRegs (CT_CR_O, 0x70, 0x80);
 821         /* don't display the attributes */
 822 }
 823
 824 #endif
 825
 826 #ifdef CONFIG_VIDEO_HW_CURSOR
 827 /***************************************************************
 828  * Set Hardware Cursor in Pixel
 829  */
 830 void
 831 video_set_hw_cursor (int x, int y)
 832 {
 833         int sig_x = 0, sig_y = 0;
 834         if (x < 0) {
 835                 x *= -1;
 836                 sig_x = 1;
 837         }
 838         if (y < 0) {
 839                 y *= -1;
 840                 sig_y = 1;
 841         }
 842         ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
 843         ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
 844         ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
 845         ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
 846 }
 847
 848 /***************************************************************
 849  * Init Hardware Cursor. To know the size of the Cursor,
 850  * we have to know the Font size.
 851  */
 852 void
 853 video_init_hw_cursor (int font_width, int font_height)
 854 {
 855         unsigned char xr_80;
 856         unsigned long *curs, pattern;
 857         int i;
 858         int cursor_start;
 859         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 860
 861         cursor_start = pGD->dprBase;
 862         xr_80 = ctRead_i (CT_XR_O, 0x80);
 863         /* set start address */
 864         ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
 865         ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
 866         /* set cursor shape */
 867         curs = (unsigned long *) cursor_start;
 868         i = 0;
 869         while (i < 0x400) {
 870                 curs[i++] = 0xffffffff; /* AND mask */
 871                 curs[i++] = 0xffffffff; /* AND mask */
 872                 curs[i++] = 0;  /* XOR mask */
 873                 curs[i++] = 0;  /* XOR mask */
 874                 /* Transparent */
 875         }
 876         pattern = 0xffffffff >> font_width;
 877         i = 0;
 878         while (i < (font_height * 2)) {
 879                 curs[i++] = pattern;    /* AND mask */
 880                 curs[i++] = pattern;    /* AND mask */
 881                 curs[i++] = 0;  /* XOR mask */
 882                 curs[i++] = 0;  /* XOR mask */
 883                 /* Cursor Color 0 */
 884         }
 885         /* set blink rate */
 886         ctWrite_i (CT_FP_O, 0x19, 0xf);
 887
 888         /* set cursors colors */
 889         xr_80 = ctRead_i (CT_XR_O, 0x80);
 890         xr_80 |= 0x1;           /* alternate palette select */
 891         ctWrite_i (CT_XR_O, 0x80, xr_80);
 892         video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
 893         /* position 4 is color 0 cursor 0 */
 894         xr_80 &= 0xfe;          /* normal palette select */
 895         ctWrite_i (CT_XR_O, 0x80, xr_80);
 896         /* cursor enable */
 897         ctWrite_i (CT_XR_O, 0xa0, 0x91);
 898         xr_80 |= 0x10;          /* enable hwcursor */
 899         ctWrite_i (CT_XR_O, 0x80, xr_80);
 900         video_set_hw_cursor (0, 0);
 901 }
 902 #endif                          /* CONFIG_VIDEO_HW_CURSOR */
 903
 904 /***************************************************************
 905  * Wait for BitBlt ready
 906  */
 907 static int
 908 video_wait_bitblt (unsigned long addr)
 909 {
 910         unsigned long br04;
 911         int i = 0;
 912         br04 = in32r (addr);
 913         while (br04 & 0x80000000) {
 914                 udelay (1);
 915                 br04 = in32r (addr);
 916                 if (i++ > 1000000) {
 917                         printf ("ERROR Timeout %lx\n", br04);
 918                         return 1;
 919                 }
 920         }
 921         return 0;
 922 }
 923
 924 /***************************************************************
 925  * Set up BitBlt Registrs
 926  */
 927 static void
 928 SetDrawingEngine (int bits_per_pixel)
 929 {
 930         unsigned long br04, br00;
 931         unsigned char tmp;
 932
 933         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 934
 935         tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
 936         tmp |= 0x02;            /* reset BitBLT */
 937         ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
 938         udelay (10);
 939         tmp &= 0xfd;            /* release reset BitBLT */
 940         ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
 941         video_wait_bitblt (pGD->pciBase + BR04_o);
 942
 943         /* set pattern Address */
 944         out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
 945         br04 = 0;
 946         if (bits_per_pixel == 1) {
 947                 br04 |= 0x00040000;     /* monochome Pattern */
 948                 br04 |= 0x00001000;     /* monochome source */
 949         }
 950         br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP);   /* bytes per scanline */
 951         out32r (pGD->pciBase + BR00_o, br00);   /* */
 952         out32r (pGD->pciBase + BR08_o, (10 << 16) + 10);        /* dummy */
 953         out32r (pGD->pciBase + BR04_o, br04);   /* write all 0 */
 954         out32r (pGD->pciBase + BR07_o, 0);      /* destination */
 955         video_wait_bitblt (pGD->pciBase + BR04_o);
 956 }
 957
 958 /****************************************************************************
 959 * supported Video Chips
 960 */
 961 static struct pci_device_id supported[] = {
 962         {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
 963 #ifdef CONFIG_USE_CPCIDVI
 964         {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
 965 #endif
 966         {}
 967 };
 968
 969 /*******************************************************************************
 970 *
 971 * Init video chip
 972 */
 973 void *
 974 video_hw_init (void)
 975 {
 976         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
 977         unsigned short device_id;
 978         pci_dev_t devbusfn;
 979         int videomode;
 980         unsigned long t1, hsynch, vsynch;
 981         unsigned int pci_mem_base, *vm;
 982         int tmp, i, bits_per_pixel;
 983         char *penv;
 984         struct ctfb_res_modes *res_mode;
 985         struct ctfb_res_modes var_mode;
 986         struct ctfb_chips_properties *chips_param;
 987         /* Search for video chip */
 988
 989         if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
 990 #ifdef CONFIG_VIDEO_ONBOARD
 991                 printf ("Video: Controller not found !\n");
 992 #endif
 993                 return (NULL);
 994         }
 995
 996         /* PCI setup */
 997         pci_write_config_dword (devbusfn, PCI_COMMAND,
 998                                 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 999         pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
1000         pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
1001         pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
1002
1003         /* get chips params */
1004         for (chips_param = (struct ctfb_chips_properties *) &chips[0];
1005              chips_param->device_id != 0; chips_param++) {
1006                 if (chips_param->device_id == device_id)
1007                         break;
1008         }
1009         if (chips_param->device_id == 0) {
1010 #ifdef CONFIG_VIDEO_ONBOARD
1011                 printf ("Video: controller 0x%X not supported\n", device_id);
1012 #endif
1013                 return NULL;
1014         }
1015         /* supported Video controller found */
1016         printf ("Video: ");
1017
1018         tmp = 0;
1019         videomode = 0x301;
1020         /* get video mode via environment */
1021         if ((penv = getenv ("videomode")) != NULL) {
1022                 /* deceide if it is a string */
1023                 if (penv[0] <= '9') {
1024                         videomode = (int) simple_strtoul (penv, NULL, 16);
1025                         tmp = 1;
1026                 }
1027         } else {
1028                 tmp = 1;
1029         }
1030         if (tmp) {
1031                 /* parameter are vesa modes */
1032                 /* search params */
1033                 for (i = 0; i < VESA_MODES_COUNT; i++) {
1034                         if (vesa_modes[i].vesanr == videomode)
1035                                 break;
1036                 }
1037                 if (i == VESA_MODES_COUNT) {
1038                         printf ("no VESA Mode found, switching to mode 0x301 ");
1039                         i = 0;
1040                 }
1041                 res_mode =
1042                     (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
1043                                                              resindex];
1044                 bits_per_pixel = vesa_modes[i].bits_per_pixel;
1045         } else {
1046
1047                 res_mode = (struct ctfb_res_modes *) &var_mode;
1048                 bits_per_pixel = video_get_params (res_mode, penv);
1049         }
1050
1051         /* calculate available color depth for controller memory */
1052         if (bits_per_pixel == 15)
1053                 tmp = 2;
1054         else
1055                 tmp = bits_per_pixel >> 3;      /* /8 */
1056         if (((chips_param->max_mem -
1057               ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
1058                 tmp =
1059                     ((chips_param->max_mem -
1060                       ACCELMEMORY) / (res_mode->xres * res_mode->yres));
1061                 if (tmp == 0) {
1062                         printf
1063                             ("No matching videomode found .-> reduce resolution\n");
1064                         return NULL;
1065                 } else {
1066                         printf ("Switching back to %d Bits per Pixel ",
1067                                 tmp << 3);
1068                         bits_per_pixel = tmp << 3;
1069                 }
1070         }
1071
1072         /* calculate hsynch and vsynch freq (info only) */
1073         t1 = (res_mode->left_margin + res_mode->xres +
1074               res_mode->right_margin + res_mode->hsync_len) / 8;
1075         t1 *= 8;
1076         t1 *= res_mode->pixclock;
1077         t1 /= 1000;
1078         hsynch = 1000000000L / t1;
1079         t1 *=
1080             (res_mode->upper_margin + res_mode->yres +
1081              res_mode->lower_margin + res_mode->vsync_len);
1082         t1 /= 1000;
1083         vsynch = 1000000000L / t1;
1084
1085         /* fill in Graphic device struct */
1086         sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
1087                  res_mode->yres, bits_per_pixel, (hsynch / 1000),
1088                  (vsynch / 1000));
1089         printf ("%s\n", pGD->modeIdent);
1090         pGD->winSizeX = res_mode->xres;
1091         pGD->winSizeY = res_mode->yres;
1092         pGD->plnSizeX = res_mode->xres;
1093         pGD->plnSizeY = res_mode->yres;
1094         switch (bits_per_pixel) {
1095         case 8:
1096                 pGD->gdfBytesPP = 1;
1097                 pGD->gdfIndex = GDF__8BIT_INDEX;
1098                 break;
1099         case 15:
1100                 pGD->gdfBytesPP = 2;
1101                 pGD->gdfIndex = GDF_15BIT_555RGB;
1102                 break;
1103         case 16:
1104                 pGD->gdfBytesPP = 2;
1105                 pGD->gdfIndex = GDF_16BIT_565RGB;
1106                 break;
1107         case 24:
1108                 pGD->gdfBytesPP = 3;
1109                 pGD->gdfIndex = GDF_24BIT_888RGB;
1110                 break;
1111         }
1112         pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
1113         pGD->pciBase = pci_mem_base;
1114         pGD->frameAdrs = pci_mem_base;
1115         pGD->memSize = chips_param->max_mem;
1116         /* Cursor Start Address */
1117         pGD->dprBase =
1118             (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
1119         if ((pGD->dprBase & 0x0fff) != 0) {
1120                 /* allign it */
1121                 pGD->dprBase &= 0xfffff000;
1122                 pGD->dprBase += 0x00001000;
1123         }
1124         PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
1125                 PATTERN_ADR);
1126         pGD->vprBase = pci_mem_base;    /* Dummy */
1127         pGD->cprBase = pci_mem_base;    /* Dummy */
1128         /* set up Hardware */
1129
1130 #ifdef CONFIG_USE_CPCIDVI
1131         if (device_id == PCI_DEVICE_ID_CT_69030) {
1132                 ctWrite (CT_MSR_W_O, 0x0b);
1133                 ctWrite (0x3cd, 0x13);
1134                 ctWrite_i (CT_FP_O, 0x02, 0x00);
1135                 ctWrite_i (CT_FP_O, 0x05, 0x00);
1136                 ctWrite_i (CT_FP_O, 0x06, 0x00);
1137                 ctWrite (0x3c2, 0x0b);
1138                 ctWrite_i (CT_FP_O, 0x02, 0x10);
1139                 ctWrite_i (CT_FP_O, 0x01, 0x09);
1140         } else {
1141                 ctWrite (CT_MSR_W_O, 0x01);
1142         }
1143 #else
1144         ctWrite (CT_MSR_W_O, 0x01);
1145 #endif
1146
1147         /* set the extended Registers */
1148         ctLoadRegs (CT_XR_O, xreg);
1149         /* set atribute registers */
1150         SetArRegs ();
1151         /* set Graphics register */
1152         SetGrRegs ();
1153         /* set sequencer */
1154         SetSrRegs ();
1155
1156         /* set msr */
1157         SetMsrRegs (res_mode);
1158
1159         /* set CRT Registers */
1160         SetCrRegs (res_mode, bits_per_pixel);
1161         /* set color mode */
1162         SetBitsPerPixelIntoXrRegs (bits_per_pixel);
1163
1164         /* set PLL */
1165         FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
1166
1167         ctWrite_i (CT_SR_O, 0, 0x03);   /* clear synchronous reset */
1168         /* Clear video memory */
1169         i = pGD->memSize / 4;
1170         vm = (unsigned int *) pGD->pciBase;
1171         while (i--)
1172                 *vm++ = 0;
1173         SetDrawingEngine (bits_per_pixel);
1174 #ifdef VGA_DUMP_REG
1175         video_dump_reg ();
1176 #endif
1177
1178         return ((void *) &ctfb);
1179 }
1180
1181  /*******************************************************************************
1182 *
1183 * Set a RGB color in the LUT (8 bit index)
1184 */
1185 void
1186 video_set_lut (unsigned int index,      /* color number */
1187                unsigned char r, /* red */
1188                unsigned char g, /* green */
1189                unsigned char b  /* blue */
1190     )
1191 {
1192
1193         ctWrite (CT_LUT_MASK_O, 0xff);
1194
1195         ctWrite (CT_LUT_START_O, (char) index);
1196
1197         ctWrite (CT_LUT_RGB_O, r);      /* red */
1198         ctWrite (CT_LUT_RGB_O, g);      /* green */
1199         ctWrite (CT_LUT_RGB_O, b);      /* blue */
1200         udelay (1);
1201         ctWrite (CT_LUT_MASK_O, 0xff);
1202 }
1203
1204 /*******************************************************************************
1205 *
1206 * Drawing engine fill on screen region
1207 */
1208 void
1209 video_hw_rectfill (unsigned int bpp,    /* bytes per pixel */
1210                    unsigned int dst_x,  /* dest pos x */
1211                    unsigned int dst_y,  /* dest pos y */
1212                    unsigned int dim_x,  /* frame width */
1213                    unsigned int dim_y,  /* frame height */
1214                    unsigned int color   /* fill color */
1215     )
1216 {
1217         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1218         unsigned long *p, br04;
1219
1220         video_wait_bitblt (pGD->pciBase + BR04_o);
1221
1222         p = (unsigned long *) PATTERN_ADR;
1223         dim_x *= bpp;
1224         if (bpp == 3)
1225                 bpp++;          /* 24Bit needs a 32bit pattern */
1226         memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8));      /* 8 x 8 pattern data */
1227         out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP);    /* destination */
1228         br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
1229         br04 |= 0xF0;           /* write Pattern P -> D */
1230         out32r (pGD->pciBase + BR04_o, br04);   /* */
1231         out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x);  /* starts the BITBlt */
1232         video_wait_bitblt (pGD->pciBase + BR04_o);
1233 }
1234
1235 /*******************************************************************************
1236 *
1237 * Drawing engine bitblt with screen region
1238 */
1239 void
1240 video_hw_bitblt (unsigned int bpp,      /* bytes per pixel */
1241                  unsigned int src_x,    /* source pos x */
1242                  unsigned int src_y,    /* source pos y */
1243                  unsigned int dst_x,    /* dest pos x */
1244                  unsigned int dst_y,    /* dest pos y */
1245                  unsigned int dim_x,    /* frame width */
1246                  unsigned int dim_y     /* frame height */
1247     )
1248 {
1249         GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1250         unsigned long br04;
1251
1252         br04 = in32r (pGD->pciBase + BR04_o);
1253
1254         /* to prevent data corruption due to overlap, we have to
1255          * find out if, and how the frames overlaps */
1256         if (src_x < dst_x) {
1257                 /* src is more left than dest
1258                  * the frame may overlap -> start from right to left */
1259                 br04 |= 0x00000100;     /* set bit 8 */
1260                 src_x += dim_x;
1261                 dst_x += dim_x;
1262         } else {
1263                 br04 &= 0xfffffeff;     /* clear bit 8 left to right */
1264         }
1265         if (src_y < dst_y) {
1266                 /* src is higher than dst
1267                  * the frame may overlap => start from bottom */
1268                 br04 |= 0x00000200;     /* set bit 9 */
1269                 src_y += dim_y;
1270                 dst_y += dim_y;
1271         } else {
1272                 br04 &= 0xfffffdff;     /* clear bit 9 top to bottom */
1273         }
1274         dim_x *= bpp;
1275         out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP);    /* source */
1276         out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP);    /* destination */
1277         br04 &= 0xffffff00;
1278         br04 |= 0x000000CC;     /* S -> D */
1279         out32r (pGD->pciBase + BR04_o, br04);   /* */
1280         out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x);  /* start the BITBlt */
1281         video_wait_bitblt (pGD->pciBase + BR04_o);
1282 }
1283
1284 #endif                          /* CONFIG_CT69000 */
1285
1286 #endif                          /* CONFIG_VIDEO */