2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager
*sdr_rw_load_mgr_regs
=
18 (struct socfpga_sdr_rw_load_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager
*sdr_rw_load_jump_mgr_regs
=
21 (struct socfpga_sdr_rw_load_jump_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0xC00);
23 static struct socfpga_sdr_reg_file
*sdr_reg_file
=
24 (struct socfpga_sdr_reg_file
*)SDR_PHYGRP_REGFILEGRP_ADDRESS
;
26 static struct socfpga_sdr_scc_mgr
*sdr_scc_mgr
=
27 (struct socfpga_sdr_scc_mgr
*)(SDR_PHYGRP_SCCGRP_ADDRESS
| 0xe00);
29 static struct socfpga_phy_mgr_cmd
*phy_mgr_cmd
=
30 (struct socfpga_phy_mgr_cmd
*)SDR_PHYGRP_PHYMGRGRP_ADDRESS
;
32 static struct socfpga_phy_mgr_cfg
*phy_mgr_cfg
=
33 (struct socfpga_phy_mgr_cfg
*)(SDR_PHYGRP_PHYMGRGRP_ADDRESS
| 0x40);
35 static struct socfpga_data_mgr
*data_mgr
=
36 (struct socfpga_data_mgr
*)SDR_PHYGRP_DATAMGRGRP_ADDRESS
;
38 static struct socfpga_sdr_ctrl
*sdr_ctrl
=
39 (struct socfpga_sdr_ctrl
*)SDR_CTRLGRP_ADDRESS
;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps
;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask
; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type
*param
;
81 uint32_t curr_shadow_reg
;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn
,
84 uint32_t write_group
, uint32_t use_dm
,
85 uint32_t all_correct
, uint32_t *bit_chk
, uint32_t all_ranks
);
87 static void set_failing_group_stage(uint32_t group
, uint32_t stage
,
91 * Only set the global stage if there was not been any other
94 if (gbl
->error_stage
== CAL_STAGE_NIL
) {
95 gbl
->error_substage
= substage
;
96 gbl
->error_stage
= stage
;
97 gbl
->error_group
= group
;
101 static void reg_file_set_group(u16 set_group
)
103 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff0000, set_group
<< 16);
106 static void reg_file_set_stage(u8 set_stage
)
108 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff, set_stage
& 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage
)
113 set_sub_stage
&= 0xff;
114 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xff00, set_sub_stage
<< 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__
, __LINE__
);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg
->mux_sel
);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg
->reset_mem_stbl
);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg
->cal_status
);
141 writel(0, &phy_mgr_cfg
->cal_debug_info
);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
)
147 ratio
= RW_MGR_MEM_DQ_PER_READ_DQS
/
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
;
149 param
->read_correct_mask_vg
= (1 << ratio
) - 1;
150 param
->write_correct_mask_vg
= (1 << ratio
) - 1;
151 param
->read_correct_mask
= (1 << RW_MGR_MEM_DQ_PER_READ_DQS
) - 1;
152 param
->write_correct_mask
= (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS
) - 1;
153 ratio
= RW_MGR_MEM_DATA_WIDTH
/
154 RW_MGR_MEM_DATA_MASK_WIDTH
;
155 param
->dm_correct_mask
= (1 << ratio
) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank
, const u32 odt_mode
)
171 if (odt_mode
== RW_MGR_ODT_MODE_OFF
) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS
) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
== 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0
= 0x3 & ~(1 << rank
);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1
= 0x3 & (1 << rank
);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask
= (0xFF & ~(1 << rank
)) |
256 ((0xFF & odt_mask_0
) << 8) |
257 ((0xFF & odt_mask_1
) << 16);
258 writel(cs_and_odt_mask
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off
, u32 grp
, u32 val
)
272 writel(val
, SDR_PHYGRP_SCCGRP_ADDRESS
| off
| (grp
<< 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i
= 0; i
< 16; i
++) {
291 debug_cond(DLEVEL
== 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__
, __LINE__
, i
);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET
, 0, i
);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group
, uint32_t phase
)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
, write_group
, phase
);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group
, uint32_t delay
)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET
, read_group
, delay
);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group
, uint32_t phase
)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET
, read_group
, phase
);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group
, uint32_t delay
)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET
, read_group
, delay
);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay
)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group
, uint32_t delay
)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, dq_in_group
, delay
);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group
, uint32_t delay
)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, dq_in_group
, delay
);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay
)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm
, uint32_t delay
)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS
+ 1 + dm
,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs
)
349 writel(dqs
, &sdr_scc_mgr
->dqs_ena
);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group
)
361 writel(dq_in_group
, &sdr_scc_mgr
->dq_ena
);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm
)
367 writel(dm
, &sdr_scc_mgr
->dm_ena
);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off
, const u32 grp
, const u32 val
,
385 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
386 r
+= NUM_RANKS_PER_SHADOW_REG
) {
387 scc_mgr_set(off
, grp
, val
);
389 if (update
|| (r
== 0)) {
390 writel(grp
, &sdr_scc_mgr
->dqs_ena
);
391 writel(0, &sdr_scc_mgr
->update
);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group
, u32 phase
)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET
,
407 read_group
, phase
, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group
,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
,
422 write_group
, phase
, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group
,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET
,
437 read_group
, delay
, 1);
438 writel(0, &sdr_scc_mgr
->update
);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group
, const u32 delay
)
450 const int ratio
= RW_MGR_MEM_IF_READ_DQS_WIDTH
/
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
;
452 const int base
= write_group
* ratio
;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i
= 0; i
< ratio
; i
++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET
, base
+ i
, delay
);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value
= (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
|
484 SCC_MGR_HHP_GLOBALS_OFFSET
|
485 SCC_MGR_HHP_EXTRAS_OFFSET
;
487 debug_cond(DLEVEL
== 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL
== 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
508 r
+= NUM_RANKS_PER_SHADOW_REG
) {
509 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i
, IO_DQS_IN_RESERVE
);
516 scc_mgr_set_dqs_en_phase(i
, 0);
517 scc_mgr_set_dqs_en_delay(i
, 0);
520 for (i
= 0; i
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; i
++) {
521 scc_mgr_set_dqdqs_output_phase(i
, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i
, IO_DQS_OUT_RESERVE
);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
529 writel(0, &sdr_scc_mgr
->update
);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group
)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr
->dq_ena
);
542 writel(0xff, &sdr_scc_mgr
->dm_ena
);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
547 /* Update the DQS logic. */
548 writel(write_group
, &sdr_scc_mgr
->dqs_ena
);
551 writel(0, &sdr_scc_mgr
->update
);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group
)
562 const int ratio
= RW_MGR_MEM_IF_READ_DQS_WIDTH
/
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
;
564 const int base
= write_group
* ratio
;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i
= 0; i
< ratio
; i
++)
574 writel(base
+ i
, &sdr_scc_mgr
->dqs_ena
);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group
, const int out_only
)
586 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
587 r
+= NUM_RANKS_PER_SHADOW_REG
) {
588 /* Zero all DQ config settings. */
589 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
590 scc_mgr_set_dq_out1_delay(i
, 0);
592 scc_mgr_set_dq_in_delay(i
, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr
->dq_ena
);
598 /* Zero all DM config settings. */
599 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
600 scc_mgr_set_dm_out1_delay(i
, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr
->dm_ena
);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE
);
611 scc_mgr_set_oct_out1_delay(write_group
, IO_DQS_OUT_RESERVE
);
612 scc_mgr_load_dqs_for_write_group(write_group
);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr
->update
);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn
, uint32_t delay
)
630 for (i
= 0, p
= group_bgn
; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++, p
++) {
631 scc_mgr_set_dq_in_delay(p
, delay
);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay
)
646 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
647 scc_mgr_set_dq_out1_delay(i
, delay
);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1
)
657 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++) {
658 scc_mgr_set_dm_out1_delay(i
, delay1
);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group
,
668 scc_mgr_set_dqs_out1_delay(delay
);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group
, delay
);
672 scc_mgr_load_dqs_for_write_group(write_group
);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group
,
688 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++)
692 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
696 new_delay
= READ_SCC_DQS_IO_OUT2_DELAY
+ delay
;
697 if (new_delay
> IO_IO_OUT2_DELAY_MAX
) {
698 debug_cond(DLEVEL
== 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__
, __LINE__
, write_group
, delay
, new_delay
,
701 IO_IO_OUT2_DELAY_MAX
,
702 new_delay
- IO_IO_OUT2_DELAY_MAX
);
703 new_delay
-= IO_IO_OUT2_DELAY_MAX
;
704 scc_mgr_set_dqs_out1_delay(new_delay
);
707 scc_mgr_load_dqs_io();
710 new_delay
= READ_SCC_OCT_OUT2_DELAY
+ delay
;
711 if (new_delay
> IO_IO_OUT2_DELAY_MAX
) {
712 debug_cond(DLEVEL
== 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__
, __LINE__
, write_group
, delay
,
715 new_delay
, IO_IO_OUT2_DELAY_MAX
,
716 new_delay
- IO_IO_OUT2_DELAY_MAX
);
717 new_delay
-= IO_IO_OUT2_DELAY_MAX
;
718 scc_mgr_set_oct_out1_delay(write_group
, new_delay
);
721 scc_mgr_load_dqs_for_write_group(write_group
);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group
,
737 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
738 r
+= NUM_RANKS_PER_SHADOW_REG
) {
739 scc_mgr_apply_group_all_out_delay_add(write_group
, delay
);
740 writel(0, &sdr_scc_mgr
->update
);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs
->load_cntr0
);
758 writel(RW_MGR_RETURN
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks
)
772 debug("%s:%d: clocks=%u ... start\n", __func__
, __LINE__
, clocks
);
775 afi_clocks
= (clocks
+ AFI_RATE_RATIO
-1) / AFI_RATE_RATIO
;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks
== 0) {
787 } else if (afi_clocks
<= 0x100) {
788 inner
= afi_clocks
-1;
791 } else if (afi_clocks
<= 0x10000) {
793 outer
= (afi_clocks
-1) >> 8;
798 c_loop
= (afi_clocks
-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks
<= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
820 &sdr_rw_load_mgr_regs
->load_cntr1
);
822 writel(RW_MGR_IDLE_LOOP1
,
823 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
825 writel(RW_MGR_IDLE_LOOP1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
829 &sdr_rw_load_mgr_regs
->load_cntr0
);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer
),
832 &sdr_rw_load_mgr_regs
->load_cntr1
);
834 writel(RW_MGR_IDLE_LOOP2
,
835 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
837 writel(RW_MGR_IDLE_LOOP2
,
838 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks
<= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
847 writel(RW_MGR_IDLE_LOOP2
,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS
|
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
850 } while (c_loop
-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__
, __LINE__
, clocks
);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0
, u32 cntr1
, u32 cntr2
, u32 jump
)
867 uint32_t grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0
),
872 &sdr_rw_load_mgr_regs
->load_cntr0
);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1
),
874 &sdr_rw_load_mgr_regs
->load_cntr1
);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2
),
876 &sdr_rw_load_mgr_regs
->load_cntr2
);
878 /* Load jump address */
879 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
880 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
881 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
883 /* Execute count instruction */
884 writel(jump
, grpaddr
);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1
, const u32 fin2
,
898 u32 grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
902 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
; r
++) {
903 if (param
->skip_ranks
[r
]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL
, grpaddr
);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING
>> r
) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR
, grpaddr
);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR
, grpaddr
);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR
, grpaddr
);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1
, grpaddr
);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2
, grpaddr
);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3
, grpaddr
);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1
, grpaddr
);
940 set_jump_as_return();
941 writel(fin2
, grpaddr
);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL
, grpaddr
);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__
, __LINE__
);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL
, SEQ_TINIT_CNTR1_VAL
,
993 RW_MGR_INIT_RESET_0_CKE_0
);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg
->reset_mem_stbl
);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL
, SEQ_TRESET_CNTR1_VAL
,
1013 SEQ_TRESET_CNTR2_VAL
,
1014 RW_MGR_INIT_RESET_1_CKE_0
);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR
, RW_MGR_MRS0_DLL_RESET
,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR
, RW_MGR_MRS0_USER
, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn
, const u32 group
,
1050 const u32 all_ranks
)
1052 const u32 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1054 const u32 addr_offset
=
1055 (group
* RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
) << 2;
1056 const u32 rank_end
= all_ranks
?
1057 RW_MGR_MEM_NUMBER_OF_RANKS
:
1058 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1059 const u32 shift_ratio
= RW_MGR_MEM_DQ_PER_READ_DQS
/
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
;
1061 const u32 correct_mask_vg
= param
->read_correct_mask_vg
;
1063 u32 tmp_bit_chk
, base_rw_mgr
, bit_chk
;
1067 bit_chk
= param
->read_correct_mask
;
1069 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1070 /* Request to skip the rank */
1071 if (param
->skip_ranks
[r
])
1075 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1079 writel(RW_MGR_GUARANTEED_READ
,
1080 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1082 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1083 writel(RW_MGR_GUARANTEED_READ_CONT
,
1084 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1087 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
- 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd
->fifo_reset
);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1093 writel(RW_MGR_GUARANTEED_READ
,
1094 addr
+ addr_offset
+ (vg
<< 2));
1096 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1097 tmp_bit_chk
<<= shift_ratio
;
1098 tmp_bit_chk
|= correct_mask_vg
& ~base_rw_mgr
;
1101 bit_chk
&= tmp_bit_chk
;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE
, addr
+ (group
<< 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1108 if (bit_chk
!= param
->read_correct_mask
)
1111 debug_cond(DLEVEL
== 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__
, __LINE__
, group
, bit_chk
,
1114 param
->read_correct_mask
, ret
);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn
,
1127 const int all_ranks
)
1129 const u32 rank_end
= all_ranks
?
1130 RW_MGR_MEM_NUMBER_OF_RANKS
:
1131 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1134 debug("%s:%d\n", __func__
, __LINE__
);
1136 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1137 if (param
->skip_ranks
[r
])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0
,
1148 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1150 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1
,
1153 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1155 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr2
);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2
,
1158 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1160 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr3
);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3
,
1163 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1165 writel(RW_MGR_GUARANTEED_WRITE
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1173 * try a read and see if it returns correct data back. has dummy reads
1174 * inserted into the mix used to align dqs enable. has more thorough checks
1175 * than the regular read test.
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn
, uint32_t group
,
1178 uint32_t num_tries
, uint32_t all_correct
, uint32_t *bit_chk
,
1179 uint32_t all_groups
, uint32_t all_ranks
)
1182 uint32_t correct_mask_vg
;
1183 uint32_t tmp_bit_chk
;
1184 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
1185 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1187 uint32_t base_rw_mgr
;
1189 *bit_chk
= param
->read_correct_mask
;
1190 correct_mask_vg
= param
->read_correct_mask_vg
;
1194 uint32_t quick_read_mode
= (((STATIC_CALIB_STEPS
) &
1195 CALIB_SKIP_DELAY_SWEEPS
) && ENABLE_SUPER_QUICK_CALIBRATION
);
1197 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1198 if (param
->skip_ranks
[r
])
1199 /* request to skip the rank */
1203 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1205 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr1
);
1207 writel(RW_MGR_READ_B2B_WAIT1
,
1208 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1210 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr2
);
1211 writel(RW_MGR_READ_B2B_WAIT2
,
1212 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1214 if (quick_read_mode
)
1215 writel(0x1, &sdr_rw_load_mgr_regs
->load_cntr0
);
1216 /* need at least two (1+1) reads to capture failures */
1217 else if (all_groups
)
1218 writel(0x06, &sdr_rw_load_mgr_regs
->load_cntr0
);
1220 writel(0x32, &sdr_rw_load_mgr_regs
->load_cntr0
);
1222 writel(RW_MGR_READ_B2B
,
1223 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1225 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH
*
1226 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
- 1,
1227 &sdr_rw_load_mgr_regs
->load_cntr3
);
1229 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr3
);
1231 writel(RW_MGR_READ_B2B
,
1232 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1235 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
-1; ; vg
--) {
1236 /* reset the fifos to get pointers to known state */
1237 writel(0, &phy_mgr_cmd
->fifo_reset
);
1238 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1239 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1241 tmp_bit_chk
= tmp_bit_chk
<< (RW_MGR_MEM_DQ_PER_READ_DQS
1242 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
);
1245 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_ALL_GROUPS_OFFSET
;
1247 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1249 writel(RW_MGR_READ_B2B
, addr
+
1250 ((group
* RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
+
1253 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1254 tmp_bit_chk
= tmp_bit_chk
| (correct_mask_vg
& ~(base_rw_mgr
));
1259 *bit_chk
&= tmp_bit_chk
;
1262 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1263 writel(RW_MGR_CLEAR_DQS_ENABLE
, addr
+ (group
<< 2));
1265 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1268 ret
= (*bit_chk
== param
->read_correct_mask
);
1269 debug_cond(DLEVEL
== 2,
1270 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1271 __func__
, __LINE__
, group
, all_groups
, *bit_chk
,
1272 param
->read_correct_mask
, ret
);
1274 ret
= (*bit_chk
!= 0x00);
1275 debug_cond(DLEVEL
== 2,
1276 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1277 __func__
, __LINE__
, group
, all_groups
, *bit_chk
,
1285 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1286 * @grp: Read/Write group
1287 * @num_tries: Number of retries of the test
1288 * @all_correct: All bits must be correct in the mask
1289 * @all_groups: Test all R/W groups
1291 * Perform a READ test across all memory ranks.
1294 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp
, const u32 num_tries
,
1295 const u32 all_correct
,
1296 const u32 all_groups
)
1299 return rw_mgr_mem_calibrate_read_test(0, grp
, num_tries
, all_correct
,
1300 &bit_chk
, all_groups
, 1);
1304 * rw_mgr_incr_vfifo() - Increase VFIFO value
1305 * @grp: Read/Write group
1307 * Increase VFIFO value.
1309 static void rw_mgr_incr_vfifo(const u32 grp
)
1311 writel(grp
, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
1315 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1316 * @grp: Read/Write group
1318 * Decrease VFIFO value.
1320 static void rw_mgr_decr_vfifo(const u32 grp
)
1324 for (i
= 0; i
< VFIFO_SIZE
- 1; i
++)
1325 rw_mgr_incr_vfifo(grp
);
1329 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1330 * @grp: Read/Write group
1332 * Push VFIFO until a failing read happens.
1334 static int find_vfifo_failing_read(const u32 grp
)
1336 u32 v
, ret
, fail_cnt
= 0;
1338 for (v
= 0; v
< VFIFO_SIZE
; v
++) {
1339 debug_cond(DLEVEL
== 2, "%s:%d: vfifo %u\n",
1340 __func__
, __LINE__
, v
);
1341 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1350 /* Fiddle with FIFO. */
1351 rw_mgr_incr_vfifo(grp
);
1354 /* No failing read found! Something must have gone wrong. */
1355 debug_cond(DLEVEL
== 2, "%s:%d: vfifo failed\n", __func__
, __LINE__
);
1360 * sdr_find_phase_delay() - Find DQS enable phase or delay
1361 * @working: If 1, look for working phase/delay, if 0, look for non-working
1362 * @delay: If 1, look for delay, if 0, look for phase
1363 * @grp: Read/Write group
1364 * @work: Working window position
1365 * @work_inc: Working window increment
1366 * @pd: DQS Phase/Delay Iterator
1368 * Find working or non-working DQS enable phase setting.
1370 static int sdr_find_phase_delay(int working
, int delay
, const u32 grp
,
1371 u32
*work
, const u32 work_inc
, u32
*pd
)
1373 const u32 max
= delay
? IO_DQS_EN_DELAY_MAX
: IO_DQS_EN_PHASE_MAX
;
1376 for (; *pd
<= max
; (*pd
)++) {
1378 scc_mgr_set_dqs_en_delay_all_ranks(grp
, *pd
);
1380 scc_mgr_set_dqs_en_phase_all_ranks(grp
, *pd
);
1382 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1397 * sdr_find_phase() - Find DQS enable phase
1398 * @working: If 1, look for working phase, if 0, look for non-working phase
1399 * @grp: Read/Write group
1400 * @work: Working window position
1402 * @p: DQS Phase Iterator
1404 * Find working or non-working DQS enable phase setting.
1406 static int sdr_find_phase(int working
, const u32 grp
, u32
*work
,
1409 const u32 end
= VFIFO_SIZE
+ (working
? 0 : 1);
1412 for (; *i
< end
; (*i
)++) {
1416 ret
= sdr_find_phase_delay(working
, 0, grp
, work
,
1417 IO_DELAY_PER_OPA_TAP
, p
);
1421 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1422 /* Fiddle with FIFO. */
1423 rw_mgr_incr_vfifo(grp
);
1433 * sdr_working_phase() - Find working DQS enable phase
1434 * @grp: Read/Write group
1435 * @work_bgn: Working window start position
1436 * @d: dtaps output value
1437 * @p: DQS Phase Iterator
1440 * Find working DQS enable phase setting.
1442 static int sdr_working_phase(const u32 grp
, u32
*work_bgn
, u32
*d
,
1445 const u32 dtaps_per_ptap
= IO_DELAY_PER_OPA_TAP
/
1446 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1451 for (*d
= 0; *d
<= dtaps_per_ptap
; (*d
)++) {
1453 scc_mgr_set_dqs_en_delay_all_ranks(grp
, *d
);
1454 ret
= sdr_find_phase(1, grp
, work_bgn
, i
, p
);
1457 *work_bgn
+= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1460 /* Cannot find working solution */
1461 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1462 __func__
, __LINE__
);
1467 * sdr_backup_phase() - Find DQS enable backup phase
1468 * @grp: Read/Write group
1469 * @work_bgn: Working window start position
1470 * @p: DQS Phase Iterator
1472 * Find DQS enable backup phase setting.
1474 static void sdr_backup_phase(const u32 grp
, u32
*work_bgn
, u32
*p
)
1479 /* Special case code for backing up a phase */
1481 *p
= IO_DQS_EN_PHASE_MAX
;
1482 rw_mgr_decr_vfifo(grp
);
1486 tmp_delay
= *work_bgn
- IO_DELAY_PER_OPA_TAP
;
1487 scc_mgr_set_dqs_en_phase_all_ranks(grp
, *p
);
1489 for (d
= 0; d
<= IO_DQS_EN_DELAY_MAX
&& tmp_delay
< *work_bgn
; d
++) {
1490 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1492 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1495 *work_bgn
= tmp_delay
;
1499 tmp_delay
+= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1502 /* Restore VFIFO to old state before we decremented it (if needed). */
1504 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1506 rw_mgr_incr_vfifo(grp
);
1509 scc_mgr_set_dqs_en_delay_all_ranks(grp
, 0);
1513 * sdr_nonworking_phase() - Find non-working DQS enable phase
1514 * @grp: Read/Write group
1515 * @work_end: Working window end position
1516 * @p: DQS Phase Iterator
1519 * Find non-working DQS enable phase setting.
1521 static int sdr_nonworking_phase(const u32 grp
, u32
*work_end
, u32
*p
, u32
*i
)
1526 *work_end
+= IO_DELAY_PER_OPA_TAP
;
1527 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1528 /* Fiddle with FIFO. */
1530 rw_mgr_incr_vfifo(grp
);
1533 ret
= sdr_find_phase(0, grp
, work_end
, i
, p
);
1535 /* Cannot see edge of failing read. */
1536 debug_cond(DLEVEL
== 2, "%s:%d: end: failed\n",
1537 __func__
, __LINE__
);
1544 * sdr_find_window_center() - Find center of the working DQS window.
1545 * @grp: Read/Write group
1546 * @work_bgn: First working settings
1547 * @work_end: Last working settings
1549 * Find center of the working DQS enable window.
1551 static int sdr_find_window_center(const u32 grp
, const u32 work_bgn
,
1558 work_mid
= (work_bgn
+ work_end
) / 2;
1560 debug_cond(DLEVEL
== 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1561 work_bgn
, work_end
, work_mid
);
1562 /* Get the middle delay to be less than a VFIFO delay */
1563 tmp_delay
= (IO_DQS_EN_PHASE_MAX
+ 1) * IO_DELAY_PER_OPA_TAP
;
1565 debug_cond(DLEVEL
== 2, "vfifo ptap delay %d\n", tmp_delay
);
1566 work_mid
%= tmp_delay
;
1567 debug_cond(DLEVEL
== 2, "new work_mid %d\n", work_mid
);
1569 tmp_delay
= rounddown(work_mid
, IO_DELAY_PER_OPA_TAP
);
1570 if (tmp_delay
> IO_DQS_EN_PHASE_MAX
* IO_DELAY_PER_OPA_TAP
)
1571 tmp_delay
= IO_DQS_EN_PHASE_MAX
* IO_DELAY_PER_OPA_TAP
;
1572 p
= tmp_delay
/ IO_DELAY_PER_OPA_TAP
;
1574 debug_cond(DLEVEL
== 2, "new p %d, tmp_delay=%d\n", p
, tmp_delay
);
1576 d
= DIV_ROUND_UP(work_mid
- tmp_delay
, IO_DELAY_PER_DQS_EN_DCHAIN_TAP
);
1577 if (d
> IO_DQS_EN_DELAY_MAX
)
1578 d
= IO_DQS_EN_DELAY_MAX
;
1579 tmp_delay
+= d
* IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1581 debug_cond(DLEVEL
== 2, "new d %d, tmp_delay=%d\n", d
, tmp_delay
);
1583 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1584 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1587 * push vfifo until we can successfully calibrate. We can do this
1588 * because the largest possible margin in 1 VFIFO cycle.
1590 for (i
= 0; i
< VFIFO_SIZE
; i
++) {
1591 debug_cond(DLEVEL
== 2, "find_dqs_en_phase: center\n");
1592 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1595 debug_cond(DLEVEL
== 2,
1596 "%s:%d center: found: ptap=%u dtap=%u\n",
1597 __func__
, __LINE__
, p
, d
);
1601 /* Fiddle with FIFO. */
1602 rw_mgr_incr_vfifo(grp
);
1605 debug_cond(DLEVEL
== 2, "%s:%d center: failed.\n",
1606 __func__
, __LINE__
);
1611 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1612 * @grp: Read/Write Group
1614 * Find a good DQS enable to use.
1616 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp
)
1620 u32 work_bgn
, work_end
;
1621 u32 found_passing_read
, found_failing_read
, initial_failing_dtap
;
1624 debug("%s:%d %u\n", __func__
, __LINE__
, grp
);
1626 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
1628 scc_mgr_set_dqs_en_delay_all_ranks(grp
, 0);
1629 scc_mgr_set_dqs_en_phase_all_ranks(grp
, 0);
1631 /* Step 0: Determine number of delay taps for each phase tap. */
1632 dtaps_per_ptap
= IO_DELAY_PER_OPA_TAP
/ IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1634 /* Step 1: First push vfifo until we get a failing read. */
1635 find_vfifo_failing_read(grp
);
1637 /* Step 2: Find first working phase, increment in ptaps. */
1639 ret
= sdr_working_phase(grp
, &work_bgn
, &d
, &p
, &i
);
1643 work_end
= work_bgn
;
1646 * If d is 0 then the working window covers a phase tap and we can
1647 * follow the old procedure. Otherwise, we've found the beginning
1648 * and we need to increment the dtaps until we find the end.
1652 * Step 3a: If we have room, back off by one and
1653 * increment in dtaps.
1655 sdr_backup_phase(grp
, &work_bgn
, &p
);
1658 * Step 4a: go forward from working phase to non working
1659 * phase, increment in ptaps.
1661 ret
= sdr_nonworking_phase(grp
, &work_end
, &p
, &i
);
1665 /* Step 5a: Back off one from last, increment in dtaps. */
1667 /* Special case code for backing up a phase */
1669 p
= IO_DQS_EN_PHASE_MAX
;
1670 rw_mgr_decr_vfifo(grp
);
1675 work_end
-= IO_DELAY_PER_OPA_TAP
;
1676 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1680 debug_cond(DLEVEL
== 2, "%s:%d p: ptap=%u\n",
1681 __func__
, __LINE__
, p
);
1684 /* The dtap increment to find the failing edge is done here. */
1685 sdr_find_phase_delay(0, 1, grp
, &work_end
,
1686 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
, &d
);
1688 /* Go back to working dtap */
1690 work_end
-= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1692 debug_cond(DLEVEL
== 2,
1693 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1694 __func__
, __LINE__
, p
, d
- 1, work_end
);
1696 if (work_end
< work_bgn
) {
1698 debug_cond(DLEVEL
== 2, "%s:%d end-2: failed\n",
1699 __func__
, __LINE__
);
1703 debug_cond(DLEVEL
== 2, "%s:%d found range [%u,%u]\n",
1704 __func__
, __LINE__
, work_bgn
, work_end
);
1707 * We need to calculate the number of dtaps that equal a ptap.
1708 * To do that we'll back up a ptap and re-find the edge of the
1709 * window using dtaps
1711 debug_cond(DLEVEL
== 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1712 __func__
, __LINE__
);
1714 /* Special case code for backing up a phase */
1716 p
= IO_DQS_EN_PHASE_MAX
;
1717 rw_mgr_decr_vfifo(grp
);
1718 debug_cond(DLEVEL
== 2, "%s:%d backedup cycle/phase: p=%u\n",
1719 __func__
, __LINE__
, p
);
1722 debug_cond(DLEVEL
== 2, "%s:%d backedup phase only: p=%u",
1723 __func__
, __LINE__
, p
);
1726 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1729 * Increase dtap until we first see a passing read (in case the
1730 * window is smaller than a ptap), and then a failing read to
1731 * mark the edge of the window again.
1734 /* Find a passing read. */
1735 debug_cond(DLEVEL
== 2, "%s:%d find passing read\n",
1736 __func__
, __LINE__
);
1738 initial_failing_dtap
= d
;
1740 found_passing_read
= !sdr_find_phase_delay(1, 1, grp
, NULL
, 0, &d
);
1741 if (found_passing_read
) {
1742 /* Find a failing read. */
1743 debug_cond(DLEVEL
== 2, "%s:%d find failing read\n",
1744 __func__
, __LINE__
);
1746 found_failing_read
= !sdr_find_phase_delay(0, 1, grp
, NULL
, 0,
1749 debug_cond(DLEVEL
== 1,
1750 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1751 __func__
, __LINE__
);
1755 * The dynamically calculated dtaps_per_ptap is only valid if we
1756 * found a passing/failing read. If we didn't, it means d hit the max
1757 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1758 * statically calculated value.
1760 if (found_passing_read
&& found_failing_read
)
1761 dtaps_per_ptap
= d
- initial_failing_dtap
;
1763 writel(dtaps_per_ptap
, &sdr_reg_file
->dtaps_per_ptap
);
1764 debug_cond(DLEVEL
== 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1765 __func__
, __LINE__
, d
, initial_failing_dtap
, dtaps_per_ptap
);
1767 /* Step 6: Find the centre of the window. */
1768 ret
= sdr_find_window_center(grp
, work_bgn
, work_end
);
1773 /* per-bit deskew DQ and center */
1774 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn
,
1775 uint32_t write_group
, uint32_t read_group
, uint32_t test_bgn
,
1776 uint32_t use_read_test
, uint32_t update_fom
)
1778 uint32_t i
, p
, d
, min_index
;
1780 * Store these as signed since there are comparisons with
1784 uint32_t sticky_bit_chk
;
1785 int32_t left_edge
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1786 int32_t right_edge
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1787 int32_t final_dq
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1789 int32_t orig_mid_min
, mid_min
;
1790 int32_t new_dqs
, start_dqs
, start_dqs_en
, shift_dq
, final_dqs
,
1792 int32_t dq_margin
, dqs_margin
;
1794 uint32_t temp_dq_in_delay1
, temp_dq_in_delay2
;
1797 debug("%s:%d: %u %u", __func__
, __LINE__
, read_group
, test_bgn
);
1799 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_DQS_IN_DELAY_OFFSET
;
1800 start_dqs
= readl(addr
+ (read_group
<< 2));
1801 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
)
1802 start_dqs_en
= readl(addr
+ ((read_group
<< 2)
1803 - IO_DQS_EN_DELAY_OFFSET
));
1805 /* set the left and right edge of each bit to an illegal value */
1806 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1808 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1809 left_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1810 right_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1813 /* Search for the left edge of the window for each bit */
1814 for (d
= 0; d
<= IO_IO_IN_DELAY_MAX
; d
++) {
1815 scc_mgr_apply_group_dq_in_delay(write_group
, test_bgn
, d
);
1817 writel(0, &sdr_scc_mgr
->update
);
1820 * Stop searching when the read test doesn't pass AND when
1821 * we've seen a passing read on every bit.
1823 if (use_read_test
) {
1824 stop
= !rw_mgr_mem_calibrate_read_test(rank_bgn
,
1825 read_group
, NUM_READ_PB_TESTS
, PASS_ONE_BIT
,
1828 rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
1831 bit_chk
= bit_chk
>> (RW_MGR_MEM_DQ_PER_READ_DQS
*
1832 (read_group
- (write_group
*
1833 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
1834 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
)));
1835 stop
= (bit_chk
== 0);
1837 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
1838 stop
= stop
&& (sticky_bit_chk
== param
->read_correct_mask
);
1839 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1840 && %u", __func__
, __LINE__
, d
,
1842 param
->read_correct_mask
, stop
);
1847 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1849 /* Remember a passing test as the
1853 /* If a left edge has not been seen yet,
1854 then a future passing test will mark
1855 this edge as the right edge */
1857 IO_IO_IN_DELAY_MAX
+ 1) {
1858 right_edge
[i
] = -(d
+ 1);
1861 bit_chk
= bit_chk
>> 1;
1866 /* Reset DQ delay chains to 0 */
1867 scc_mgr_apply_group_dq_in_delay(test_bgn
, 0);
1869 for (i
= RW_MGR_MEM_DQ_PER_READ_DQS
- 1;; i
--) {
1870 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: left_edge[%u]: \
1871 %d right_edge[%u]: %d\n", __func__
, __LINE__
,
1872 i
, left_edge
[i
], i
, right_edge
[i
]);
1875 * Check for cases where we haven't found the left edge,
1876 * which makes our assignment of the the right edge invalid.
1877 * Reset it to the illegal value.
1879 if ((left_edge
[i
] == IO_IO_IN_DELAY_MAX
+ 1) && (
1880 right_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1)) {
1881 right_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1882 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: reset \
1883 right_edge[%u]: %d\n", __func__
, __LINE__
,
1888 * Reset sticky bit (except for bits where we have seen
1889 * both the left and right edge).
1891 sticky_bit_chk
= sticky_bit_chk
<< 1;
1892 if ((left_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1) &&
1893 (right_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1)) {
1894 sticky_bit_chk
= sticky_bit_chk
| 1;
1901 /* Search for the right edge of the window for each bit */
1902 for (d
= 0; d
<= IO_DQS_IN_DELAY_MAX
- start_dqs
; d
++) {
1903 scc_mgr_set_dqs_bus_in_delay(read_group
, d
+ start_dqs
);
1904 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
1905 uint32_t delay
= d
+ start_dqs_en
;
1906 if (delay
> IO_DQS_EN_DELAY_MAX
)
1907 delay
= IO_DQS_EN_DELAY_MAX
;
1908 scc_mgr_set_dqs_en_delay(read_group
, delay
);
1910 scc_mgr_load_dqs(read_group
);
1912 writel(0, &sdr_scc_mgr
->update
);
1915 * Stop searching when the read test doesn't pass AND when
1916 * we've seen a passing read on every bit.
1918 if (use_read_test
) {
1919 stop
= !rw_mgr_mem_calibrate_read_test(rank_bgn
,
1920 read_group
, NUM_READ_PB_TESTS
, PASS_ONE_BIT
,
1923 rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
1926 bit_chk
= bit_chk
>> (RW_MGR_MEM_DQ_PER_READ_DQS
*
1927 (read_group
- (write_group
*
1928 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
1929 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
)));
1930 stop
= (bit_chk
== 0);
1932 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
1933 stop
= stop
&& (sticky_bit_chk
== param
->read_correct_mask
);
1935 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1936 %u && %u", __func__
, __LINE__
, d
,
1937 sticky_bit_chk
, param
->read_correct_mask
, stop
);
1942 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1944 /* Remember a passing test as
1949 /* If a right edge has not been
1950 seen yet, then a future passing
1951 test will mark this edge as the
1953 if (right_edge
[i
] ==
1954 IO_IO_IN_DELAY_MAX
+ 1) {
1955 left_edge
[i
] = -(d
+ 1);
1958 /* d = 0 failed, but it passed
1959 when testing the left edge,
1960 so it must be marginal,
1962 if (right_edge
[i
] ==
1963 IO_IO_IN_DELAY_MAX
+ 1 &&
1969 /* If a right edge has not been
1970 seen yet, then a future passing
1971 test will mark this edge as the
1973 else if (right_edge
[i
] ==
1974 IO_IO_IN_DELAY_MAX
+
1976 left_edge
[i
] = -(d
+ 1);
1981 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center[r,\
1982 d=%u]: ", __func__
, __LINE__
, d
);
1983 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d ",
1984 (int)(bit_chk
& 1), i
, left_edge
[i
]);
1985 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
1987 bit_chk
= bit_chk
>> 1;
1992 /* Check that all bits have a window */
1993 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1994 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: left_edge[%u]: \
1995 %d right_edge[%u]: %d", __func__
, __LINE__
,
1996 i
, left_edge
[i
], i
, right_edge
[i
]);
1997 if ((left_edge
[i
] == IO_IO_IN_DELAY_MAX
+ 1) || (right_edge
[i
]
1998 == IO_IO_IN_DELAY_MAX
+ 1)) {
2000 * Restore delay chain settings before letting the loop
2001 * in rw_mgr_mem_calibrate_vfifo to retry different
2002 * dqs/ck relationships.
2004 scc_mgr_set_dqs_bus_in_delay(read_group
, start_dqs
);
2005 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2006 scc_mgr_set_dqs_en_delay(read_group
,
2009 scc_mgr_load_dqs(read_group
);
2010 writel(0, &sdr_scc_mgr
->update
);
2012 debug_cond(DLEVEL
== 1, "%s:%d vfifo_center: failed to \
2013 find edge [%u]: %d %d", __func__
, __LINE__
,
2014 i
, left_edge
[i
], right_edge
[i
]);
2015 if (use_read_test
) {
2016 set_failing_group_stage(read_group
*
2017 RW_MGR_MEM_DQ_PER_READ_DQS
+ i
,
2019 CAL_SUBSTAGE_VFIFO_CENTER
);
2021 set_failing_group_stage(read_group
*
2022 RW_MGR_MEM_DQ_PER_READ_DQS
+ i
,
2023 CAL_STAGE_VFIFO_AFTER_WRITES
,
2024 CAL_SUBSTAGE_VFIFO_CENTER
);
2030 /* Find middle of window for each DQ bit */
2031 mid_min
= left_edge
[0] - right_edge
[0];
2033 for (i
= 1; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
2034 mid
= left_edge
[i
] - right_edge
[i
];
2035 if (mid
< mid_min
) {
2042 * -mid_min/2 represents the amount that we need to move DQS.
2043 * If mid_min is odd and positive we'll need to add one to
2044 * make sure the rounding in further calculations is correct
2045 * (always bias to the right), so just add 1 for all positive values.
2050 mid_min
= mid_min
/ 2;
2052 debug_cond(DLEVEL
== 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2053 __func__
, __LINE__
, mid_min
, min_index
);
2055 /* Determine the amount we can change DQS (which is -mid_min) */
2056 orig_mid_min
= mid_min
;
2057 new_dqs
= start_dqs
- mid_min
;
2058 if (new_dqs
> IO_DQS_IN_DELAY_MAX
)
2059 new_dqs
= IO_DQS_IN_DELAY_MAX
;
2060 else if (new_dqs
< 0)
2063 mid_min
= start_dqs
- new_dqs
;
2064 debug_cond(DLEVEL
== 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2067 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2068 if (start_dqs_en
- mid_min
> IO_DQS_EN_DELAY_MAX
)
2069 mid_min
+= start_dqs_en
- mid_min
- IO_DQS_EN_DELAY_MAX
;
2070 else if (start_dqs_en
- mid_min
< 0)
2071 mid_min
+= start_dqs_en
- mid_min
;
2073 new_dqs
= start_dqs
- mid_min
;
2075 debug_cond(DLEVEL
== 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2076 new_dqs=%d mid_min=%d\n", start_dqs
,
2077 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
? start_dqs_en
: -1,
2080 /* Initialize data for export structures */
2081 dqs_margin
= IO_IO_IN_DELAY_MAX
+ 1;
2082 dq_margin
= IO_IO_IN_DELAY_MAX
+ 1;
2084 /* add delay to bring centre of all DQ windows to the same "level" */
2085 for (i
= 0, p
= test_bgn
; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++, p
++) {
2086 /* Use values before divide by 2 to reduce round off error */
2087 shift_dq
= (left_edge
[i
] - right_edge
[i
] -
2088 (left_edge
[min_index
] - right_edge
[min_index
]))/2 +
2089 (orig_mid_min
- mid_min
);
2091 debug_cond(DLEVEL
== 2, "vfifo_center: before: \
2092 shift_dq[%u]=%d\n", i
, shift_dq
);
2094 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_IN_DELAY_OFFSET
;
2095 temp_dq_in_delay1
= readl(addr
+ (p
<< 2));
2096 temp_dq_in_delay2
= readl(addr
+ (i
<< 2));
2098 if (shift_dq
+ (int32_t)temp_dq_in_delay1
>
2099 (int32_t)IO_IO_IN_DELAY_MAX
) {
2100 shift_dq
= (int32_t)IO_IO_IN_DELAY_MAX
- temp_dq_in_delay2
;
2101 } else if (shift_dq
+ (int32_t)temp_dq_in_delay1
< 0) {
2102 shift_dq
= -(int32_t)temp_dq_in_delay1
;
2104 debug_cond(DLEVEL
== 2, "vfifo_center: after: \
2105 shift_dq[%u]=%d\n", i
, shift_dq
);
2106 final_dq
[i
] = temp_dq_in_delay1
+ shift_dq
;
2107 scc_mgr_set_dq_in_delay(p
, final_dq
[i
]);
2110 debug_cond(DLEVEL
== 2, "vfifo_center: margin[%u]=[%d,%d]\n", i
,
2111 left_edge
[i
] - shift_dq
+ (-mid_min
),
2112 right_edge
[i
] + shift_dq
- (-mid_min
));
2113 /* To determine values for export structures */
2114 if (left_edge
[i
] - shift_dq
+ (-mid_min
) < dq_margin
)
2115 dq_margin
= left_edge
[i
] - shift_dq
+ (-mid_min
);
2117 if (right_edge
[i
] + shift_dq
- (-mid_min
) < dqs_margin
)
2118 dqs_margin
= right_edge
[i
] + shift_dq
- (-mid_min
);
2121 final_dqs
= new_dqs
;
2122 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
)
2123 final_dqs_en
= start_dqs_en
- mid_min
;
2126 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2127 scc_mgr_set_dqs_en_delay(read_group
, final_dqs_en
);
2128 scc_mgr_load_dqs(read_group
);
2132 scc_mgr_set_dqs_bus_in_delay(read_group
, final_dqs
);
2133 scc_mgr_load_dqs(read_group
);
2134 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: dq_margin=%d \
2135 dqs_margin=%d", __func__
, __LINE__
,
2136 dq_margin
, dqs_margin
);
2139 * Do not remove this line as it makes sure all of our decisions
2140 * have been applied. Apply the update bit.
2142 writel(0, &sdr_scc_mgr
->update
);
2144 return (dq_margin
>= 0) && (dqs_margin
>= 0);
2148 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2149 * @rw_group: Read/Write Group
2150 * @phase: DQ/DQS phase
2152 * Because initially no communication ca be reliably performed with the memory
2153 * device, the sequencer uses a guaranteed write mechanism to write data into
2154 * the memory device.
2156 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group
,
2161 /* Set a particular DQ/DQS phase. */
2162 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group
, phase
);
2164 debug_cond(DLEVEL
== 1, "%s:%d guaranteed write: g=%u p=%u\n",
2165 __func__
, __LINE__
, rw_group
, phase
);
2168 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2169 * Load up the patterns used by read calibration using the
2170 * current DQDQS phase.
2172 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2174 if (gbl
->phy_debug_mode_flags
& PHY_DEBUG_DISABLE_GUARANTEED_READ
)
2178 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2179 * Back-to-Back reads of the patterns used for calibration.
2181 ret
= rw_mgr_mem_calibrate_read_test_patterns(0, rw_group
, 1);
2183 debug_cond(DLEVEL
== 1,
2184 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2185 __func__
, __LINE__
, rw_group
, phase
);
2190 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2191 * @rw_group: Read/Write Group
2192 * @test_bgn: Rank at which the test begins
2194 * DQS enable calibration ensures reliable capture of the DQ signal without
2195 * glitches on the DQS line.
2197 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group
,
2201 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2202 * DQS and DQS Eanble Signal Relationships.
2205 /* We start at zero, so have one less dq to devide among */
2206 const u32 delay_step
= IO_IO_IN_DELAY_MAX
/
2207 (RW_MGR_MEM_DQ_PER_READ_DQS
- 1);
2211 debug("%s:%d (%u,%u)\n", __func__
, __LINE__
, rw_group
, test_bgn
);
2213 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2214 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2215 r
+= NUM_RANKS_PER_SHADOW_REG
) {
2216 for (i
= 0, p
= test_bgn
, d
= 0;
2217 i
< RW_MGR_MEM_DQ_PER_READ_DQS
;
2218 i
++, p
++, d
+= delay_step
) {
2219 debug_cond(DLEVEL
== 1,
2220 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2221 __func__
, __LINE__
, rw_group
, r
, i
, p
, d
);
2223 scc_mgr_set_dq_in_delay(p
, d
);
2227 writel(0, &sdr_scc_mgr
->update
);
2231 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2232 * dq_in_delay values
2234 ret
= rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group
);
2236 debug_cond(DLEVEL
== 1,
2237 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2238 __func__
, __LINE__
, rw_group
, !ret
);
2240 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2241 r
+= NUM_RANKS_PER_SHADOW_REG
) {
2242 scc_mgr_apply_group_dq_in_delay(test_bgn
, 0);
2243 writel(0, &sdr_scc_mgr
->update
);
2250 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2251 * @rw_group: Read/Write Group
2252 * @test_bgn: Rank at which the test begins
2253 * @use_read_test: Perform a read test
2254 * @update_fom: Update FOM
2256 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2260 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group
, const u32 test_bgn
,
2261 const int use_read_test
,
2262 const int update_fom
)
2265 int ret
, grp_calibrated
;
2269 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2270 * Read per-bit deskew can be done on a per shadow register basis.
2273 for (rank_bgn
= 0, sr
= 0;
2274 rank_bgn
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2275 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, sr
++) {
2276 /* Check if this set of ranks should be skipped entirely. */
2277 if (param
->skip_shadow_regs
[sr
])
2280 ret
= rw_mgr_mem_calibrate_vfifo_center(rank_bgn
, rw_group
,
2290 if (!grp_calibrated
)
2297 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2298 * @rw_group: Read/Write Group
2299 * @test_bgn: Rank at which the test begins
2301 * Stage 1: Calibrate the read valid prediction FIFO.
2303 * This function implements UniPHY calibration Stage 1, as explained in
2304 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2306 * - read valid prediction will consist of finding:
2307 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2308 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2309 * - we also do a per-bit deskew on the DQ lines.
2311 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group
, const u32 test_bgn
)
2314 uint32_t dtaps_per_ptap
;
2315 uint32_t failed_substage
;
2319 debug("%s:%d: %u %u\n", __func__
, __LINE__
, rw_group
, test_bgn
);
2321 /* Update info for sims */
2322 reg_file_set_group(rw_group
);
2323 reg_file_set_stage(CAL_STAGE_VFIFO
);
2324 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ
);
2326 failed_substage
= CAL_SUBSTAGE_GUARANTEED_READ
;
2328 /* USER Determine number of delay taps for each phase tap. */
2329 dtaps_per_ptap
= DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP
,
2330 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
) - 1;
2332 for (d
= 0; d
<= dtaps_per_ptap
; d
+= 2) {
2334 * In RLDRAMX we may be messing the delay of pins in
2335 * the same write rw_group but outside of the current read
2336 * the rw_group, but that's ok because we haven't calibrated
2340 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2344 for (p
= 0; p
<= IO_DQDQS_OUT_PHASE_MAX
; p
++) {
2345 /* 1) Guaranteed Write */
2346 ret
= rw_mgr_mem_calibrate_guaranteed_write(rw_group
, p
);
2350 /* 2) DQS Enable Calibration */
2351 ret
= rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group
,
2354 failed_substage
= CAL_SUBSTAGE_DQS_EN_PHASE
;
2358 /* 3) Centering DQ/DQS */
2360 * If doing read after write calibration, do not update
2361 * FOM now. Do it then.
2363 ret
= rw_mgr_mem_calibrate_dq_dqs_centering(rw_group
,
2366 failed_substage
= CAL_SUBSTAGE_VFIFO_CENTER
;
2375 /* Calibration Stage 1 failed. */
2376 set_failing_group_stage(rw_group
, CAL_STAGE_VFIFO
, failed_substage
);
2379 /* Calibration Stage 1 completed OK. */
2382 * Reset the delay chains back to zero if they have moved > 1
2383 * (check for > 1 because loop will increase d even when pass in
2387 scc_mgr_zero_group(rw_group
, 1);
2392 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2393 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group
,
2396 uint32_t rank_bgn
, sr
;
2397 uint32_t grp_calibrated
;
2398 uint32_t write_group
;
2400 debug("%s:%d %u %u", __func__
, __LINE__
, read_group
, test_bgn
);
2402 /* update info for sims */
2404 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES
);
2405 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
2407 write_group
= read_group
;
2409 /* update info for sims */
2410 reg_file_set_group(read_group
);
2413 /* Read per-bit deskew can be done on a per shadow register basis */
2414 for (rank_bgn
= 0, sr
= 0; rank_bgn
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2415 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, ++sr
) {
2416 /* Determine if this set of ranks should be skipped entirely */
2417 if (!param
->skip_shadow_regs
[sr
]) {
2418 /* This is the last calibration round, update FOM here */
2419 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn
,
2430 if (grp_calibrated
== 0) {
2431 set_failing_group_stage(write_group
,
2432 CAL_STAGE_VFIFO_AFTER_WRITES
,
2433 CAL_SUBSTAGE_VFIFO_CENTER
);
2440 /* Calibrate LFIFO to find smallest read latency */
2441 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2445 debug("%s:%d\n", __func__
, __LINE__
);
2447 /* update info for sims */
2448 reg_file_set_stage(CAL_STAGE_LFIFO
);
2449 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY
);
2451 /* Load up the patterns used by read calibration for all ranks */
2452 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2456 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2457 debug_cond(DLEVEL
== 2, "%s:%d lfifo: read_lat=%u",
2458 __func__
, __LINE__
, gbl
->curr_read_lat
);
2460 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2468 /* reduce read latency and see if things are working */
2470 gbl
->curr_read_lat
--;
2471 } while (gbl
->curr_read_lat
> 0);
2473 /* reset the fifos to get pointers to known state */
2475 writel(0, &phy_mgr_cmd
->fifo_reset
);
2478 /* add a fudge factor to the read latency that was determined */
2479 gbl
->curr_read_lat
+= 2;
2480 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2481 debug_cond(DLEVEL
== 2, "%s:%d lfifo: success: using \
2482 read_lat=%u\n", __func__
, __LINE__
,
2483 gbl
->curr_read_lat
);
2486 set_failing_group_stage(0xff, CAL_STAGE_LFIFO
,
2487 CAL_SUBSTAGE_READ_LATENCY
);
2489 debug_cond(DLEVEL
== 2, "%s:%d lfifo: failed at initial \
2490 read_lat=%u\n", __func__
, __LINE__
,
2491 gbl
->curr_read_lat
);
2497 * issue write test command.
2498 * two variants are provided. one that just tests a write pattern and
2499 * another that tests datamask functionality.
2501 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group
,
2504 uint32_t mcc_instruction
;
2505 uint32_t quick_write_mode
= (((STATIC_CALIB_STEPS
) & CALIB_SKIP_WRITES
) &&
2506 ENABLE_SUPER_QUICK_CALIBRATION
);
2507 uint32_t rw_wl_nop_cycles
;
2511 * Set counter and jump addresses for the right
2512 * number of NOP cycles.
2513 * The number of supported NOP cycles can range from -1 to infinity
2514 * Three different cases are handled:
2516 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2517 * mechanism will be used to insert the right number of NOPs
2519 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2520 * issuing the write command will jump straight to the
2521 * micro-instruction that turns on DQS (for DDRx), or outputs write
2522 * data (for RLD), skipping
2523 * the NOP micro-instruction all together
2525 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2526 * turned on in the same micro-instruction that issues the write
2527 * command. Then we need
2528 * to directly jump to the micro-instruction that sends out the data
2530 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2531 * (2 and 3). One jump-counter (0) is used to perform multiple
2532 * write-read operations.
2533 * one counter left to issue this command in "multiple-group" mode
2536 rw_wl_nop_cycles
= gbl
->rw_wl_nop_cycles
;
2538 if (rw_wl_nop_cycles
== -1) {
2540 * CNTR 2 - We want to execute the special write operation that
2541 * turns on DQS right away and then skip directly to the
2542 * instruction that sends out the data. We set the counter to a
2543 * large number so that the jump is always taken.
2545 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
2547 /* CNTR 3 - Not used */
2549 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1
;
2550 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA
,
2551 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2552 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP
,
2553 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2555 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0_WL_1
;
2556 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA
,
2557 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2558 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP
,
2559 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2561 } else if (rw_wl_nop_cycles
== 0) {
2563 * CNTR 2 - We want to skip the NOP operation and go straight
2564 * to the DQS enable instruction. We set the counter to a large
2565 * number so that the jump is always taken.
2567 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
2569 /* CNTR 3 - Not used */
2571 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0
;
2572 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS
,
2573 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2575 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0
;
2576 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS
,
2577 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2581 * CNTR 2 - In this case we want to execute the next instruction
2582 * and NOT take the jump. So we set the counter to 0. The jump
2583 * address doesn't count.
2585 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr2
);
2586 writel(0x0, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2589 * CNTR 3 - Set the nop counter to the number of cycles we
2590 * need to loop for, minus 1.
2592 writel(rw_wl_nop_cycles
- 1, &sdr_rw_load_mgr_regs
->load_cntr3
);
2594 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0
;
2595 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP
,
2596 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2598 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0
;
2599 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP
,
2600 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2604 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
2605 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
2607 if (quick_write_mode
)
2608 writel(0x08, &sdr_rw_load_mgr_regs
->load_cntr0
);
2610 writel(0x40, &sdr_rw_load_mgr_regs
->load_cntr0
);
2612 writel(mcc_instruction
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
2615 * CNTR 1 - This is used to ensure enough time elapses
2616 * for read data to come back.
2618 writel(0x30, &sdr_rw_load_mgr_regs
->load_cntr1
);
2621 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT
,
2622 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
2624 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT
,
2625 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
2628 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
2629 writel(mcc_instruction
, addr
+ (group
<< 2));
2632 /* Test writes, can check for a single bit pass or multiple bit pass */
2633 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn
,
2634 uint32_t write_group
, uint32_t use_dm
, uint32_t all_correct
,
2635 uint32_t *bit_chk
, uint32_t all_ranks
)
2638 uint32_t correct_mask_vg
;
2639 uint32_t tmp_bit_chk
;
2641 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
2642 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
2643 uint32_t addr_rw_mgr
;
2644 uint32_t base_rw_mgr
;
2646 *bit_chk
= param
->write_correct_mask
;
2647 correct_mask_vg
= param
->write_correct_mask_vg
;
2649 for (r
= rank_bgn
; r
< rank_end
; r
++) {
2650 if (param
->skip_ranks
[r
]) {
2651 /* request to skip the rank */
2656 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
2659 addr_rw_mgr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
;
2660 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
-1; ; vg
--) {
2661 /* reset the fifos to get pointers to known state */
2662 writel(0, &phy_mgr_cmd
->fifo_reset
);
2664 tmp_bit_chk
= tmp_bit_chk
<<
2665 (RW_MGR_MEM_DQ_PER_WRITE_DQS
/
2666 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
);
2667 rw_mgr_mem_calibrate_write_test_issue(write_group
*
2668 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
+vg
,
2671 base_rw_mgr
= readl(addr_rw_mgr
);
2672 tmp_bit_chk
= tmp_bit_chk
| (correct_mask_vg
& ~(base_rw_mgr
));
2676 *bit_chk
&= tmp_bit_chk
;
2680 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
2681 debug_cond(DLEVEL
== 2, "write_test(%u,%u,ALL) : %u == \
2682 %u => %lu", write_group
, use_dm
,
2683 *bit_chk
, param
->write_correct_mask
,
2684 (long unsigned int)(*bit_chk
==
2685 param
->write_correct_mask
));
2686 return *bit_chk
== param
->write_correct_mask
;
2688 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
2689 debug_cond(DLEVEL
== 2, "write_test(%u,%u,ONE) : %u != ",
2690 write_group
, use_dm
, *bit_chk
);
2691 debug_cond(DLEVEL
== 2, "%lu" " => %lu", (long unsigned int)0,
2692 (long unsigned int)(*bit_chk
!= 0));
2693 return *bit_chk
!= 0x00;
2698 * center all windows. do per-bit-deskew to possibly increase size of
2701 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn
,
2702 uint32_t write_group
, uint32_t test_bgn
)
2704 uint32_t i
, p
, min_index
;
2707 * Store these as signed since there are comparisons with
2711 uint32_t sticky_bit_chk
;
2712 int32_t left_edge
[RW_MGR_MEM_DQ_PER_WRITE_DQS
];
2713 int32_t right_edge
[RW_MGR_MEM_DQ_PER_WRITE_DQS
];
2715 int32_t mid_min
, orig_mid_min
;
2716 int32_t new_dqs
, start_dqs
, shift_dq
;
2717 int32_t dq_margin
, dqs_margin
, dm_margin
;
2719 uint32_t temp_dq_out1_delay
;
2722 debug("%s:%d %u %u", __func__
, __LINE__
, write_group
, test_bgn
);
2726 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_OUT1_DELAY_OFFSET
;
2727 start_dqs
= readl(addr
+
2728 (RW_MGR_MEM_DQ_PER_WRITE_DQS
<< 2));
2730 /* per-bit deskew */
2733 * set the left and right edge of each bit to an illegal value
2734 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2737 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2738 left_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2739 right_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2742 /* Search for the left edge of the window for each bit */
2743 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
; d
++) {
2744 scc_mgr_apply_group_dq_out1_delay(write_group
, d
);
2746 writel(0, &sdr_scc_mgr
->update
);
2749 * Stop searching when the read test doesn't pass AND when
2750 * we've seen a passing read on every bit.
2752 stop
= !rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
2753 0, PASS_ONE_BIT
, &bit_chk
, 0);
2754 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
2755 stop
= stop
&& (sticky_bit_chk
== param
->write_correct_mask
);
2756 debug_cond(DLEVEL
== 2, "write_center(left): dtap=%d => %u \
2757 == %u && %u [bit_chk= %u ]\n",
2758 d
, sticky_bit_chk
, param
->write_correct_mask
,
2764 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2767 * Remember a passing test as the
2773 * If a left edge has not been seen
2774 * yet, then a future passing test will
2775 * mark this edge as the right edge.
2778 IO_IO_OUT1_DELAY_MAX
+ 1) {
2779 right_edge
[i
] = -(d
+ 1);
2782 debug_cond(DLEVEL
== 2, "write_center[l,d=%d):", d
);
2783 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d",
2784 (int)(bit_chk
& 1), i
, left_edge
[i
]);
2785 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2787 bit_chk
= bit_chk
>> 1;
2792 /* Reset DQ delay chains to 0 */
2793 scc_mgr_apply_group_dq_out1_delay(0);
2795 for (i
= RW_MGR_MEM_DQ_PER_WRITE_DQS
- 1;; i
--) {
2796 debug_cond(DLEVEL
== 2, "%s:%d write_center: left_edge[%u]: \
2797 %d right_edge[%u]: %d\n", __func__
, __LINE__
,
2798 i
, left_edge
[i
], i
, right_edge
[i
]);
2801 * Check for cases where we haven't found the left edge,
2802 * which makes our assignment of the the right edge invalid.
2803 * Reset it to the illegal value.
2805 if ((left_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1) &&
2806 (right_edge
[i
] != IO_IO_OUT1_DELAY_MAX
+ 1)) {
2807 right_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2808 debug_cond(DLEVEL
== 2, "%s:%d write_center: reset \
2809 right_edge[%u]: %d\n", __func__
, __LINE__
,
2814 * Reset sticky bit (except for bits where we have
2815 * seen the left edge).
2817 sticky_bit_chk
= sticky_bit_chk
<< 1;
2818 if ((left_edge
[i
] != IO_IO_OUT1_DELAY_MAX
+ 1))
2819 sticky_bit_chk
= sticky_bit_chk
| 1;
2825 /* Search for the right edge of the window for each bit */
2826 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
- start_dqs
; d
++) {
2827 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
2830 writel(0, &sdr_scc_mgr
->update
);
2833 * Stop searching when the read test doesn't pass AND when
2834 * we've seen a passing read on every bit.
2836 stop
= !rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
2837 0, PASS_ONE_BIT
, &bit_chk
, 0);
2839 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
2840 stop
= stop
&& (sticky_bit_chk
== param
->write_correct_mask
);
2842 debug_cond(DLEVEL
== 2, "write_center (right): dtap=%u => %u == \
2843 %u && %u\n", d
, sticky_bit_chk
,
2844 param
->write_correct_mask
, stop
);
2848 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
;
2850 /* d = 0 failed, but it passed when
2851 testing the left edge, so it must be
2852 marginal, set it to -1 */
2853 if (right_edge
[i
] ==
2854 IO_IO_OUT1_DELAY_MAX
+ 1 &&
2856 IO_IO_OUT1_DELAY_MAX
+ 1) {
2863 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2866 * Remember a passing test as
2873 * If a right edge has not
2874 * been seen yet, then a future
2875 * passing test will mark this
2876 * edge as the left edge.
2878 if (right_edge
[i
] ==
2879 IO_IO_OUT1_DELAY_MAX
+ 1)
2880 left_edge
[i
] = -(d
+ 1);
2883 * d = 0 failed, but it passed
2884 * when testing the left edge,
2885 * so it must be marginal, set
2888 if (right_edge
[i
] ==
2889 IO_IO_OUT1_DELAY_MAX
+ 1 &&
2891 IO_IO_OUT1_DELAY_MAX
+ 1)
2894 * If a right edge has not been
2895 * seen yet, then a future
2896 * passing test will mark this
2897 * edge as the left edge.
2899 else if (right_edge
[i
] ==
2900 IO_IO_OUT1_DELAY_MAX
+
2902 left_edge
[i
] = -(d
+ 1);
2905 debug_cond(DLEVEL
== 2, "write_center[r,d=%d):", d
);
2906 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d",
2907 (int)(bit_chk
& 1), i
, left_edge
[i
]);
2908 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2910 bit_chk
= bit_chk
>> 1;
2915 /* Check that all bits have a window */
2916 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2917 debug_cond(DLEVEL
== 2, "%s:%d write_center: left_edge[%u]: \
2918 %d right_edge[%u]: %d", __func__
, __LINE__
,
2919 i
, left_edge
[i
], i
, right_edge
[i
]);
2920 if ((left_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1) ||
2921 (right_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1)) {
2922 set_failing_group_stage(test_bgn
+ i
,
2924 CAL_SUBSTAGE_WRITES_CENTER
);
2929 /* Find middle of window for each DQ bit */
2930 mid_min
= left_edge
[0] - right_edge
[0];
2932 for (i
= 1; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2933 mid
= left_edge
[i
] - right_edge
[i
];
2934 if (mid
< mid_min
) {
2941 * -mid_min/2 represents the amount that we need to move DQS.
2942 * If mid_min is odd and positive we'll need to add one to
2943 * make sure the rounding in further calculations is correct
2944 * (always bias to the right), so just add 1 for all positive values.
2948 mid_min
= mid_min
/ 2;
2949 debug_cond(DLEVEL
== 1, "%s:%d write_center: mid_min=%d\n", __func__
,
2952 /* Determine the amount we can change DQS (which is -mid_min) */
2953 orig_mid_min
= mid_min
;
2954 new_dqs
= start_dqs
;
2956 debug_cond(DLEVEL
== 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2957 mid_min=%d\n", __func__
, __LINE__
, start_dqs
, new_dqs
, mid_min
);
2958 /* Initialize data for export structures */
2959 dqs_margin
= IO_IO_OUT1_DELAY_MAX
+ 1;
2960 dq_margin
= IO_IO_OUT1_DELAY_MAX
+ 1;
2962 /* add delay to bring centre of all DQ windows to the same "level" */
2963 for (i
= 0, p
= test_bgn
; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++, p
++) {
2964 /* Use values before divide by 2 to reduce round off error */
2965 shift_dq
= (left_edge
[i
] - right_edge
[i
] -
2966 (left_edge
[min_index
] - right_edge
[min_index
]))/2 +
2967 (orig_mid_min
- mid_min
);
2969 debug_cond(DLEVEL
== 2, "%s:%d write_center: before: shift_dq \
2970 [%u]=%d\n", __func__
, __LINE__
, i
, shift_dq
);
2972 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_OUT1_DELAY_OFFSET
;
2973 temp_dq_out1_delay
= readl(addr
+ (i
<< 2));
2974 if (shift_dq
+ (int32_t)temp_dq_out1_delay
>
2975 (int32_t)IO_IO_OUT1_DELAY_MAX
) {
2976 shift_dq
= (int32_t)IO_IO_OUT1_DELAY_MAX
- temp_dq_out1_delay
;
2977 } else if (shift_dq
+ (int32_t)temp_dq_out1_delay
< 0) {
2978 shift_dq
= -(int32_t)temp_dq_out1_delay
;
2980 debug_cond(DLEVEL
== 2, "write_center: after: shift_dq[%u]=%d\n",
2982 scc_mgr_set_dq_out1_delay(i
, temp_dq_out1_delay
+ shift_dq
);
2985 debug_cond(DLEVEL
== 2, "write_center: margin[%u]=[%d,%d]\n", i
,
2986 left_edge
[i
] - shift_dq
+ (-mid_min
),
2987 right_edge
[i
] + shift_dq
- (-mid_min
));
2988 /* To determine values for export structures */
2989 if (left_edge
[i
] - shift_dq
+ (-mid_min
) < dq_margin
)
2990 dq_margin
= left_edge
[i
] - shift_dq
+ (-mid_min
);
2992 if (right_edge
[i
] + shift_dq
- (-mid_min
) < dqs_margin
)
2993 dqs_margin
= right_edge
[i
] + shift_dq
- (-mid_min
);
2997 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
2998 writel(0, &sdr_scc_mgr
->update
);
3001 debug_cond(DLEVEL
== 2, "%s:%d write_center: DM\n", __func__
, __LINE__
);
3004 * set the left and right edge of each bit to an illegal value,
3005 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3007 left_edge
[0] = IO_IO_OUT1_DELAY_MAX
+ 1;
3008 right_edge
[0] = IO_IO_OUT1_DELAY_MAX
+ 1;
3009 int32_t bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3010 int32_t end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3011 int32_t bgn_best
= IO_IO_OUT1_DELAY_MAX
+ 1;
3012 int32_t end_best
= IO_IO_OUT1_DELAY_MAX
+ 1;
3013 int32_t win_best
= 0;
3015 /* Search for the/part of the window with DM shift */
3016 for (d
= IO_IO_OUT1_DELAY_MAX
; d
>= 0; d
-= DELTA_D
) {
3017 scc_mgr_apply_group_dm_out1_delay(d
);
3018 writel(0, &sdr_scc_mgr
->update
);
3020 if (rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 1,
3021 PASS_ALL_BITS
, &bit_chk
,
3023 /* USE Set current end of the window */
3026 * If a starting edge of our window has not been seen
3027 * this is our current start of the DM window.
3029 if (bgn_curr
== IO_IO_OUT1_DELAY_MAX
+ 1)
3033 * If current window is bigger than best seen.
3034 * Set best seen to be current window.
3036 if ((end_curr
-bgn_curr
+1) > win_best
) {
3037 win_best
= end_curr
-bgn_curr
+1;
3038 bgn_best
= bgn_curr
;
3039 end_best
= end_curr
;
3042 /* We just saw a failing test. Reset temp edge */
3043 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3044 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3049 /* Reset DM delay chains to 0 */
3050 scc_mgr_apply_group_dm_out1_delay(0);
3053 * Check to see if the current window nudges up aganist 0 delay.
3054 * If so we need to continue the search by shifting DQS otherwise DQS
3055 * search begins as a new search. */
3056 if (end_curr
!= 0) {
3057 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3058 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3061 /* Search for the/part of the window with DQS shifts */
3062 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
- new_dqs
; d
+= DELTA_D
) {
3064 * Note: This only shifts DQS, so are we limiting ourselve to
3065 * width of DQ unnecessarily.
3067 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
3070 writel(0, &sdr_scc_mgr
->update
);
3071 if (rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 1,
3072 PASS_ALL_BITS
, &bit_chk
,
3074 /* USE Set current end of the window */
3077 * If a beginning edge of our window has not been seen
3078 * this is our current begin of the DM window.
3080 if (bgn_curr
== IO_IO_OUT1_DELAY_MAX
+ 1)
3084 * If current window is bigger than best seen. Set best
3085 * seen to be current window.
3087 if ((end_curr
-bgn_curr
+1) > win_best
) {
3088 win_best
= end_curr
-bgn_curr
+1;
3089 bgn_best
= bgn_curr
;
3090 end_best
= end_curr
;
3093 /* We just saw a failing test. Reset temp edge */
3094 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3095 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3097 /* Early exit optimization: if ther remaining delay
3098 chain space is less than already seen largest window
3101 (IO_IO_OUT1_DELAY_MAX
- new_dqs
- d
)) {
3107 /* assign left and right edge for cal and reporting; */
3108 left_edge
[0] = -1*bgn_best
;
3109 right_edge
[0] = end_best
;
3111 debug_cond(DLEVEL
== 2, "%s:%d dm_calib: left=%d right=%d\n", __func__
,
3112 __LINE__
, left_edge
[0], right_edge
[0]);
3114 /* Move DQS (back to orig) */
3115 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
3119 /* Find middle of window for the DM bit */
3120 mid
= (left_edge
[0] - right_edge
[0]) / 2;
3122 /* only move right, since we are not moving DQS/DQ */
3126 /* dm_marign should fail if we never find a window */
3130 dm_margin
= left_edge
[0] - mid
;
3132 scc_mgr_apply_group_dm_out1_delay(mid
);
3133 writel(0, &sdr_scc_mgr
->update
);
3135 debug_cond(DLEVEL
== 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3136 dm_margin=%d\n", __func__
, __LINE__
, left_edge
[0],
3137 right_edge
[0], mid
, dm_margin
);
3139 gbl
->fom_out
+= dq_margin
+ dqs_margin
;
3141 debug_cond(DLEVEL
== 2, "%s:%d write_center: dq_margin=%d \
3142 dqs_margin=%d dm_margin=%d\n", __func__
, __LINE__
,
3143 dq_margin
, dqs_margin
, dm_margin
);
3146 * Do not remove this line as it makes sure all of our
3147 * decisions have been applied.
3149 writel(0, &sdr_scc_mgr
->update
);
3150 return (dq_margin
>= 0) && (dqs_margin
>= 0) && (dm_margin
>= 0);
3153 /* calibrate the write operations */
3154 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn
, uint32_t g
,
3157 /* update info for sims */
3158 debug("%s:%d %u %u\n", __func__
, __LINE__
, g
, test_bgn
);
3160 reg_file_set_stage(CAL_STAGE_WRITES
);
3161 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER
);
3163 reg_file_set_group(g
);
3165 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn
, g
, test_bgn
)) {
3166 set_failing_group_stage(g
, CAL_STAGE_WRITES
,
3167 CAL_SUBSTAGE_WRITES_CENTER
);
3175 * mem_precharge_and_activate() - Precharge all banks and activate
3177 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3179 static void mem_precharge_and_activate(void)
3183 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
; r
++) {
3184 /* Test if the rank should be skipped. */
3185 if (param
->skip_ranks
[r
])
3189 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
3191 /* Precharge all banks. */
3192 writel(RW_MGR_PRECHARGE_ALL
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3193 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3195 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr0
);
3196 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1
,
3197 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
3199 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr1
);
3200 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2
,
3201 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
3203 /* Activate rows. */
3204 writel(RW_MGR_ACTIVATE_0_AND_1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3205 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3210 * mem_init_latency() - Configure memory RLAT and WLAT settings
3212 * Configure memory RLAT and WLAT parameters.
3214 static void mem_init_latency(void)
3217 * For AV/CV, LFIFO is hardened and always runs at full rate
3218 * so max latency in AFI clocks, used here, is correspondingly
3221 const u32 max_latency
= (1 << MAX_LATENCY_COUNT_WIDTH
) - 1;
3224 debug("%s:%d\n", __func__
, __LINE__
);
3227 * Read in write latency.
3228 * WL for Hard PHY does not include additive latency.
3230 wlat
= readl(&data_mgr
->t_wl_add
);
3231 wlat
+= readl(&data_mgr
->mem_t_add
);
3233 gbl
->rw_wl_nop_cycles
= wlat
- 1;
3235 /* Read in readl latency. */
3236 rlat
= readl(&data_mgr
->t_rl_add
);
3238 /* Set a pretty high read latency initially. */
3239 gbl
->curr_read_lat
= rlat
+ 16;
3240 if (gbl
->curr_read_lat
> max_latency
)
3241 gbl
->curr_read_lat
= max_latency
;
3243 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3245 /* Advertise write latency. */
3246 writel(wlat
, &phy_mgr_cfg
->afi_wlat
);
3250 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3252 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3254 static void mem_skip_calibrate(void)
3256 uint32_t vfifo_offset
;
3259 debug("%s:%d\n", __func__
, __LINE__
);
3260 /* Need to update every shadow register set used by the interface */
3261 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
3262 r
+= NUM_RANKS_PER_SHADOW_REG
) {
3264 * Set output phase alignment settings appropriate for
3267 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3268 scc_mgr_set_dqs_en_phase(i
, 0);
3269 #if IO_DLL_CHAIN_LENGTH == 6
3270 scc_mgr_set_dqdqs_output_phase(i
, 6);
3272 scc_mgr_set_dqdqs_output_phase(i
, 7);
3277 * Write data arrives to the I/O two cycles before write
3278 * latency is reached (720 deg).
3279 * -> due to bit-slip in a/c bus
3280 * -> to allow board skew where dqs is longer than ck
3281 * -> how often can this happen!?
3282 * -> can claim back some ptaps for high freq
3283 * support if we can relax this, but i digress...
3285 * The write_clk leads mem_ck by 90 deg
3286 * The minimum ptap of the OPA is 180 deg
3287 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3288 * The write_clk is always delayed by 2 ptaps
3290 * Hence, to make DQS aligned to CK, we need to delay
3292 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3294 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3295 * gives us the number of ptaps, which simplies to:
3297 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3299 scc_mgr_set_dqdqs_output_phase(i
,
3300 1.25 * IO_DLL_CHAIN_LENGTH
- 2);
3302 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
3303 writel(0xff, &sdr_scc_mgr
->dqs_io_ena
);
3305 for (i
= 0; i
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; i
++) {
3306 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3307 SCC_MGR_GROUP_COUNTER_OFFSET
);
3309 writel(0xff, &sdr_scc_mgr
->dq_ena
);
3310 writel(0xff, &sdr_scc_mgr
->dm_ena
);
3311 writel(0, &sdr_scc_mgr
->update
);
3314 /* Compensate for simulation model behaviour */
3315 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3316 scc_mgr_set_dqs_bus_in_delay(i
, 10);
3317 scc_mgr_load_dqs(i
);
3319 writel(0, &sdr_scc_mgr
->update
);
3322 * ArriaV has hard FIFOs that can only be initialized by incrementing
3325 vfifo_offset
= CALIB_VFIFO_OFFSET
;
3326 for (j
= 0; j
< vfifo_offset
; j
++)
3327 writel(0xff, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
3328 writel(0, &phy_mgr_cmd
->fifo_reset
);
3331 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3332 * setting from generation-time constant.
3334 gbl
->curr_read_lat
= CALIB_LFIFO_OFFSET
;
3335 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3339 * mem_calibrate() - Memory calibration entry point.
3341 * Perform memory calibration.
3343 static uint32_t mem_calibrate(void)
3346 uint32_t rank_bgn
, sr
;
3347 uint32_t write_group
, write_test_bgn
;
3348 uint32_t read_group
, read_test_bgn
;
3349 uint32_t run_groups
, current_run
;
3350 uint32_t failing_groups
= 0;
3351 uint32_t group_failed
= 0;
3353 const u32 rwdqs_ratio
= RW_MGR_MEM_IF_READ_DQS_WIDTH
/
3354 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
;
3356 debug("%s:%d\n", __func__
, __LINE__
);
3358 /* Initialize the data settings */
3359 gbl
->error_substage
= CAL_SUBSTAGE_NIL
;
3360 gbl
->error_stage
= CAL_STAGE_NIL
;
3361 gbl
->error_group
= 0xff;
3365 /* Initialize WLAT and RLAT. */
3368 /* Initialize bit slips. */
3369 mem_precharge_and_activate();
3371 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3372 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3373 SCC_MGR_GROUP_COUNTER_OFFSET
);
3374 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3376 scc_mgr_set_hhp_extras();
3378 scc_set_bypass_mode(i
);
3381 /* Calibration is skipped. */
3382 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
) {
3384 * Set VFIFO and LFIFO to instant-on settings in skip
3387 mem_skip_calibrate();
3390 * Do not remove this line as it makes sure all of our
3391 * decisions have been applied.
3393 writel(0, &sdr_scc_mgr
->update
);
3397 /* Calibration is not skipped. */
3398 for (i
= 0; i
< NUM_CALIB_REPEAT
; i
++) {
3400 * Zero all delay chain/phase settings for all
3401 * groups and all shadow register sets.
3405 run_groups
= ~param
->skip_groups
;
3407 for (write_group
= 0, write_test_bgn
= 0; write_group
3408 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; write_group
++,
3409 write_test_bgn
+= RW_MGR_MEM_DQ_PER_WRITE_DQS
) {
3411 /* Initialize the group failure */
3414 current_run
= run_groups
& ((1 <<
3415 RW_MGR_NUM_DQS_PER_WRITE_GROUP
) - 1);
3416 run_groups
= run_groups
>>
3417 RW_MGR_NUM_DQS_PER_WRITE_GROUP
;
3419 if (current_run
== 0)
3422 writel(write_group
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3423 SCC_MGR_GROUP_COUNTER_OFFSET
);
3424 scc_mgr_zero_group(write_group
, 0);
3426 for (read_group
= write_group
* rwdqs_ratio
,
3428 read_group
< (write_group
+ 1) * rwdqs_ratio
;
3430 read_test_bgn
+= RW_MGR_MEM_DQ_PER_READ_DQS
) {
3431 if (STATIC_CALIB_STEPS
& CALIB_SKIP_VFIFO
)
3434 /* Calibrate the VFIFO */
3435 if (rw_mgr_mem_calibrate_vfifo(read_group
,
3439 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3442 /* The group failed, we're done. */
3446 /* Calibrate the output side */
3447 for (rank_bgn
= 0, sr
= 0;
3448 rank_bgn
< RW_MGR_MEM_NUMBER_OF_RANKS
;
3449 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, sr
++) {
3450 if (STATIC_CALIB_STEPS
& CALIB_SKIP_WRITES
)
3453 /* Not needed in quick mode! */
3454 if (STATIC_CALIB_STEPS
& CALIB_SKIP_DELAY_SWEEPS
)
3458 * Determine if this set of ranks
3459 * should be skipped entirely.
3461 if (param
->skip_shadow_regs
[sr
])
3464 /* Calibrate WRITEs */
3465 if (rw_mgr_mem_calibrate_writes(rank_bgn
,
3466 write_group
, write_test_bgn
))
3470 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3474 /* Some group failed, we're done. */
3478 for (read_group
= write_group
* rwdqs_ratio
,
3480 read_group
< (write_group
+ 1) * rwdqs_ratio
;
3482 read_test_bgn
+= RW_MGR_MEM_DQ_PER_READ_DQS
) {
3483 if (STATIC_CALIB_STEPS
& CALIB_SKIP_WRITES
)
3486 if (rw_mgr_mem_calibrate_vfifo_end(read_group
,
3490 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3493 /* The group failed, we're done. */
3497 /* No group failed, continue as usual. */
3500 grp_failed
: /* A group failed, increment the counter. */
3505 * USER If there are any failing groups then report
3508 if (failing_groups
!= 0)
3511 if (STATIC_CALIB_STEPS
& CALIB_SKIP_LFIFO
)
3515 * If we're skipping groups as part of debug,
3516 * don't calibrate LFIFO.
3518 if (param
->skip_groups
!= 0)
3521 /* Calibrate the LFIFO */
3522 if (!rw_mgr_mem_calibrate_lfifo())
3527 * Do not remove this line as it makes sure all of our decisions
3528 * have been applied.
3530 writel(0, &sdr_scc_mgr
->update
);
3535 * run_mem_calibrate() - Perform memory calibration
3537 * This function triggers the entire memory calibration procedure.
3539 static int run_mem_calibrate(void)
3543 debug("%s:%d\n", __func__
, __LINE__
);
3545 /* Reset pass/fail status shown on afi_cal_success/fail */
3546 writel(PHY_MGR_CAL_RESET
, &phy_mgr_cfg
->cal_status
);
3548 /* Stop tracking manager. */
3549 clrbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3551 phy_mgr_initialize();
3552 rw_mgr_mem_initialize();
3554 /* Perform the actual memory calibration. */
3555 pass
= mem_calibrate();
3557 mem_precharge_and_activate();
3558 writel(0, &phy_mgr_cmd
->fifo_reset
);
3561 rw_mgr_mem_handoff();
3563 * In Hard PHY this is a 2-bit control:
3565 * 1: DDIO Mux Select
3567 writel(0x2, &phy_mgr_cfg
->mux_sel
);
3569 /* Start tracking manager. */
3570 setbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3576 * debug_mem_calibrate() - Report result of memory calibration
3577 * @pass: Value indicating whether calibration passed or failed
3579 * This function reports the results of the memory calibration
3580 * and writes debug information into the register file.
3582 static void debug_mem_calibrate(int pass
)
3584 uint32_t debug_info
;
3587 printf("%s: CALIBRATION PASSED\n", __FILE__
);
3592 if (gbl
->fom_in
> 0xff)
3595 if (gbl
->fom_out
> 0xff)
3596 gbl
->fom_out
= 0xff;
3598 /* Update the FOM in the register file */
3599 debug_info
= gbl
->fom_in
;
3600 debug_info
|= gbl
->fom_out
<< 8;
3601 writel(debug_info
, &sdr_reg_file
->fom
);
3603 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3604 writel(PHY_MGR_CAL_SUCCESS
, &phy_mgr_cfg
->cal_status
);
3606 printf("%s: CALIBRATION FAILED\n", __FILE__
);
3608 debug_info
= gbl
->error_stage
;
3609 debug_info
|= gbl
->error_substage
<< 8;
3610 debug_info
|= gbl
->error_group
<< 16;
3612 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3613 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3614 writel(PHY_MGR_CAL_FAIL
, &phy_mgr_cfg
->cal_status
);
3616 /* Update the failing group/stage in the register file */
3617 debug_info
= gbl
->error_stage
;
3618 debug_info
|= gbl
->error_substage
<< 8;
3619 debug_info
|= gbl
->error_group
<< 16;
3620 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3623 printf("%s: Calibration complete\n", __FILE__
);
3627 * hc_initialize_rom_data() - Initialize ROM data
3629 * Initialize ROM data.
3631 static void hc_initialize_rom_data(void)
3635 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_INST_ROM_WRITE_OFFSET
;
3636 for (i
= 0; i
< ARRAY_SIZE(inst_rom_init
); i
++)
3637 writel(inst_rom_init
[i
], addr
+ (i
<< 2));
3639 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_AC_ROM_WRITE_OFFSET
;
3640 for (i
= 0; i
< ARRAY_SIZE(ac_rom_init
); i
++)
3641 writel(ac_rom_init
[i
], addr
+ (i
<< 2));
3645 * initialize_reg_file() - Initialize SDR register file
3647 * Initialize SDR register file.
3649 static void initialize_reg_file(void)
3651 /* Initialize the register file with the correct data */
3652 writel(REG_FILE_INIT_SEQ_SIGNATURE
, &sdr_reg_file
->signature
);
3653 writel(0, &sdr_reg_file
->debug_data_addr
);
3654 writel(0, &sdr_reg_file
->cur_stage
);
3655 writel(0, &sdr_reg_file
->fom
);
3656 writel(0, &sdr_reg_file
->failing_stage
);
3657 writel(0, &sdr_reg_file
->debug1
);
3658 writel(0, &sdr_reg_file
->debug2
);
3662 * initialize_hps_phy() - Initialize HPS PHY
3664 * Initialize HPS PHY.
3666 static void initialize_hps_phy(void)
3670 * Tracking also gets configured here because it's in the
3673 uint32_t trk_sample_count
= 7500;
3674 uint32_t trk_long_idle_sample_count
= (10 << 16) | 100;
3676 * Format is number of outer loops in the 16 MSB, sample
3681 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3682 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3683 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3684 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3685 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3686 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3688 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3689 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3691 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3692 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3694 writel(reg
, &sdr_ctrl
->phy_ctrl0
);
3697 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3699 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH
);
3700 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3701 trk_long_idle_sample_count
);
3702 writel(reg
, &sdr_ctrl
->phy_ctrl1
);
3705 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3706 trk_long_idle_sample_count
>>
3707 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH
);
3708 writel(reg
, &sdr_ctrl
->phy_ctrl2
);
3712 * initialize_tracking() - Initialize tracking
3714 * Initialize the register file with usable initial data.
3716 static void initialize_tracking(void)
3719 * Initialize the register file with the correct data.
3720 * Compute usable version of value in case we skip full
3721 * computation later.
3723 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP
, IO_DELAY_PER_DCHAIN_TAP
) - 1,
3724 &sdr_reg_file
->dtaps_per_ptap
);
3726 /* trk_sample_count */
3727 writel(7500, &sdr_reg_file
->trk_sample_count
);
3729 /* longidle outer loop [15:0] */
3730 writel((10 << 16) | (100 << 0), &sdr_reg_file
->trk_longidle
);
3733 * longidle sample count [31:24]
3734 * trfc, worst case of 933Mhz 4Gb [23:16]
3735 * trcd, worst case [15:8]
3738 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3739 &sdr_reg_file
->delays
);
3742 writel((RW_MGR_IDLE
<< 24) | (RW_MGR_ACTIVATE_1
<< 16) |
3743 (RW_MGR_SGLE_READ
<< 8) | (RW_MGR_PRECHARGE_ALL
<< 0),
3744 &sdr_reg_file
->trk_rw_mgr_addr
);
3746 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH
,
3747 &sdr_reg_file
->trk_read_dqs_width
);
3750 writel((RW_MGR_REFRESH_ALL
<< 24) | (1000 << 0),
3751 &sdr_reg_file
->trk_rfsh
);
3754 int sdram_calibration_full(void)
3756 struct param_type my_param
;
3757 struct gbl_type my_gbl
;
3760 memset(&my_param
, 0, sizeof(my_param
));
3761 memset(&my_gbl
, 0, sizeof(my_gbl
));
3766 /* Set the calibration enabled by default */
3767 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_ENABLE_CAL_RPT
;
3769 * Only sweep all groups (regardless of fail state) by default
3770 * Set enabled read test by default.
3772 #if DISABLE_GUARANTEED_READ
3773 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_DISABLE_GUARANTEED_READ
;
3775 /* Initialize the register file */
3776 initialize_reg_file();
3778 /* Initialize any PHY CSR */
3779 initialize_hps_phy();
3781 scc_mgr_initialize();
3783 initialize_tracking();
3785 printf("%s: Preparing to start memory calibration\n", __FILE__
);
3787 debug("%s:%d\n", __func__
, __LINE__
);
3788 debug_cond(DLEVEL
== 1,
3789 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3790 RW_MGR_MEM_NUMBER_OF_RANKS
, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
,
3791 RW_MGR_MEM_DQ_PER_READ_DQS
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
3792 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
,
3793 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
);
3794 debug_cond(DLEVEL
== 1,
3795 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3796 RW_MGR_MEM_IF_READ_DQS_WIDTH
, RW_MGR_MEM_IF_WRITE_DQS_WIDTH
,
3797 RW_MGR_MEM_DATA_WIDTH
, RW_MGR_MEM_DATA_MASK_WIDTH
,
3798 IO_DELAY_PER_OPA_TAP
, IO_DELAY_PER_DCHAIN_TAP
);
3799 debug_cond(DLEVEL
== 1, "dtap_dqsen_delay=%u, dll=%u",
3800 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
, IO_DLL_CHAIN_LENGTH
);
3801 debug_cond(DLEVEL
== 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3802 IO_DQS_EN_PHASE_MAX
, IO_DQDQS_OUT_PHASE_MAX
,
3803 IO_DQS_EN_DELAY_MAX
, IO_DQS_IN_DELAY_MAX
);
3804 debug_cond(DLEVEL
== 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3805 IO_IO_IN_DELAY_MAX
, IO_IO_OUT1_DELAY_MAX
,
3806 IO_IO_OUT2_DELAY_MAX
);
3807 debug_cond(DLEVEL
== 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3808 IO_DQS_IN_RESERVE
, IO_DQS_OUT_RESERVE
);
3810 hc_initialize_rom_data();
3812 /* update info for sims */
3813 reg_file_set_stage(CAL_STAGE_NIL
);
3814 reg_file_set_group(0);
3817 * Load global needed for those actions that require
3818 * some dynamic calibration support.
3820 dyn_calib_steps
= STATIC_CALIB_STEPS
;
3822 * Load global to allow dynamic selection of delay loop settings
3823 * based on calibration mode.
3825 if (!(dyn_calib_steps
& CALIB_SKIP_DELAY_LOOPS
))
3826 skip_delay_mask
= 0xff;
3828 skip_delay_mask
= 0x0;
3830 pass
= run_mem_calibrate();
3831 debug_mem_calibrate(pass
);