2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static struct socfpga_sdr_rw_load_manager
*sdr_rw_load_mgr_regs
=
17 (struct socfpga_sdr_rw_load_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0x800);
19 static struct socfpga_sdr_rw_load_jump_manager
*sdr_rw_load_jump_mgr_regs
=
20 (struct socfpga_sdr_rw_load_jump_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0xC00);
22 static struct socfpga_sdr_reg_file
*sdr_reg_file
=
23 (struct socfpga_sdr_reg_file
*)SDR_PHYGRP_REGFILEGRP_ADDRESS
;
25 static struct socfpga_sdr_scc_mgr
*sdr_scc_mgr
=
26 (struct socfpga_sdr_scc_mgr
*)(SDR_PHYGRP_SCCGRP_ADDRESS
| 0xe00);
28 static struct socfpga_phy_mgr_cmd
*phy_mgr_cmd
=
29 (struct socfpga_phy_mgr_cmd
*)SDR_PHYGRP_PHYMGRGRP_ADDRESS
;
31 static struct socfpga_phy_mgr_cfg
*phy_mgr_cfg
=
32 (struct socfpga_phy_mgr_cfg
*)(SDR_PHYGRP_PHYMGRGRP_ADDRESS
| 0x40);
34 static struct socfpga_data_mgr
*data_mgr
=
35 (struct socfpga_data_mgr
*)SDR_PHYGRP_DATAMGRGRP_ADDRESS
;
37 static struct socfpga_sdr_ctrl
*sdr_ctrl
=
38 (struct socfpga_sdr_ctrl
*)SDR_CTRLGRP_ADDRESS
;
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
55 #define STATIC_IN_RTL_SIM 0
56 #define STATIC_SKIP_DELAY_LOOPS 0
58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
61 /* calibration steps requested by the rtl */
62 uint16_t dyn_calib_steps
;
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
69 * The mask is set to include all bits when not-skipping, but is
73 uint16_t skip_delay_mask
; /* mask off bits when skipping/not-skipping */
75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
79 struct param_type
*param
;
80 uint32_t curr_shadow_reg
;
82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn
,
83 uint32_t write_group
, uint32_t use_dm
,
84 uint32_t all_correct
, uint32_t *bit_chk
, uint32_t all_ranks
);
86 static void set_failing_group_stage(uint32_t group
, uint32_t stage
,
90 * Only set the global stage if there was not been any other
93 if (gbl
->error_stage
== CAL_STAGE_NIL
) {
94 gbl
->error_substage
= substage
;
95 gbl
->error_stage
= stage
;
96 gbl
->error_group
= group
;
100 static void reg_file_set_group(u16 set_group
)
102 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff0000, set_group
<< 16);
105 static void reg_file_set_stage(u8 set_stage
)
107 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff, set_stage
& 0xff);
110 static void reg_file_set_sub_stage(u8 set_sub_stage
)
112 set_sub_stage
&= 0xff;
113 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xff00, set_sub_stage
<< 8);
117 * phy_mgr_initialize() - Initialize PHY Manager
119 * Initialize PHY Manager.
121 static void phy_mgr_initialize(void)
125 debug("%s:%d\n", __func__
, __LINE__
);
126 /* Calibration has control over path to memory */
128 * In Hard PHY this is a 2-bit control:
132 writel(0x3, &phy_mgr_cfg
->mux_sel
);
134 /* USER memory clock is not stable we begin initialization */
135 writel(0, &phy_mgr_cfg
->reset_mem_stbl
);
137 /* USER calibration status all set to zero */
138 writel(0, &phy_mgr_cfg
->cal_status
);
140 writel(0, &phy_mgr_cfg
->cal_debug_info
);
142 /* Init params only if we do NOT skip calibration. */
143 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
)
146 ratio
= RW_MGR_MEM_DQ_PER_READ_DQS
/
147 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
;
148 param
->read_correct_mask_vg
= (1 << ratio
) - 1;
149 param
->write_correct_mask_vg
= (1 << ratio
) - 1;
150 param
->read_correct_mask
= (1 << RW_MGR_MEM_DQ_PER_READ_DQS
) - 1;
151 param
->write_correct_mask
= (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS
) - 1;
152 ratio
= RW_MGR_MEM_DATA_WIDTH
/
153 RW_MGR_MEM_DATA_MASK_WIDTH
;
154 param
->dm_correct_mask
= (1 << ratio
) - 1;
158 * set_rank_and_odt_mask() - Set Rank and ODT mask
160 * @odt_mode: ODT mode, OFF or READ_WRITE
162 * Set Rank and ODT mask (On-Die Termination).
164 static void set_rank_and_odt_mask(const u32 rank
, const u32 odt_mode
)
170 if (odt_mode
== RW_MGR_ODT_MODE_OFF
) {
173 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
174 switch (RW_MGR_MEM_NUMBER_OF_RANKS
) {
176 /* Read: ODT = 0 ; Write: ODT = 1 */
180 case 2: /* 2 Ranks */
181 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
== 1) {
183 * - Dual-Slot , Single-Rank (1 CS per DIMM)
185 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
187 * Since MEM_NUMBER_OF_RANKS is 2, they
188 * are both single rank with 2 CS each
189 * (special for RDIMM).
191 * Read: Turn on ODT on the opposite rank
192 * Write: Turn on ODT on all ranks
194 odt_mask_0
= 0x3 & ~(1 << rank
);
198 * - Single-Slot , Dual-Rank (2 CS per DIMM)
200 * Read: Turn on ODT off on all ranks
201 * Write: Turn on ODT on active rank
204 odt_mask_1
= 0x3 & (1 << rank
);
207 case 4: /* 4 Ranks */
209 * ----------+-----------------------+
211 * Read From +-----------------------+
212 * Rank | 3 | 2 | 1 | 0 |
213 * ----------+-----+-----+-----+-----+
214 * 0 | 0 | 1 | 0 | 0 |
215 * 1 | 1 | 0 | 0 | 0 |
216 * 2 | 0 | 0 | 0 | 1 |
217 * 3 | 0 | 0 | 1 | 0 |
218 * ----------+-----+-----+-----+-----+
221 * ----------+-----------------------+
223 * Write To +-----------------------+
224 * Rank | 3 | 2 | 1 | 0 |
225 * ----------+-----+-----+-----+-----+
226 * 0 | 0 | 1 | 0 | 1 |
227 * 1 | 1 | 0 | 1 | 0 |
228 * 2 | 0 | 1 | 0 | 1 |
229 * 3 | 1 | 0 | 1 | 0 |
230 * ----------+-----+-----+-----+-----+
254 cs_and_odt_mask
= (0xFF & ~(1 << rank
)) |
255 ((0xFF & odt_mask_0
) << 8) |
256 ((0xFF & odt_mask_1
) << 16);
257 writel(cs_and_odt_mask
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
258 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
262 * scc_mgr_set() - Set SCC Manager register
263 * @off: Base offset in SCC Manager space
264 * @grp: Read/Write group
265 * @val: Value to be set
267 * This function sets the SCC Manager (Scan Chain Control Manager) register.
269 static void scc_mgr_set(u32 off
, u32 grp
, u32 val
)
271 writel(val
, SDR_PHYGRP_SCCGRP_ADDRESS
| off
| (grp
<< 2));
275 * scc_mgr_initialize() - Initialize SCC Manager registers
277 * Initialize SCC Manager registers.
279 static void scc_mgr_initialize(void)
282 * Clear register file for HPS. 16 (2^4) is the size of the
283 * full register file in the scc mgr:
284 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
285 * MEM_IF_READ_DQS_WIDTH - 1);
289 for (i
= 0; i
< 16; i
++) {
290 debug_cond(DLEVEL
== 1, "%s:%d: Clearing SCC RFILE index %u\n",
291 __func__
, __LINE__
, i
);
292 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET
, 0, i
);
296 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group
, uint32_t phase
)
298 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
, write_group
, phase
);
301 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group
, uint32_t delay
)
303 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET
, read_group
, delay
);
306 static void scc_mgr_set_dqs_en_phase(uint32_t read_group
, uint32_t phase
)
308 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET
, read_group
, phase
);
311 static void scc_mgr_set_dqs_en_delay(uint32_t read_group
, uint32_t delay
)
313 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET
, read_group
, delay
);
316 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay
)
318 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
322 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group
, uint32_t delay
)
324 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, dq_in_group
, delay
);
327 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group
, uint32_t delay
)
329 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, dq_in_group
, delay
);
332 static void scc_mgr_set_dqs_out1_delay(uint32_t delay
)
334 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
338 static void scc_mgr_set_dm_out1_delay(uint32_t dm
, uint32_t delay
)
340 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
,
341 RW_MGR_MEM_DQ_PER_WRITE_DQS
+ 1 + dm
,
345 /* load up dqs config settings */
346 static void scc_mgr_load_dqs(uint32_t dqs
)
348 writel(dqs
, &sdr_scc_mgr
->dqs_ena
);
351 /* load up dqs io config settings */
352 static void scc_mgr_load_dqs_io(void)
354 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
357 /* load up dq config settings */
358 static void scc_mgr_load_dq(uint32_t dq_in_group
)
360 writel(dq_in_group
, &sdr_scc_mgr
->dq_ena
);
363 /* load up dm config settings */
364 static void scc_mgr_load_dm(uint32_t dm
)
366 writel(dm
, &sdr_scc_mgr
->dm_ena
);
370 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
371 * @off: Base offset in SCC Manager space
372 * @grp: Read/Write group
373 * @val: Value to be set
374 * @update: If non-zero, trigger SCC Manager update for all ranks
376 * This function sets the SCC Manager (Scan Chain Control Manager) register
377 * and optionally triggers the SCC update for all ranks.
379 static void scc_mgr_set_all_ranks(const u32 off
, const u32 grp
, const u32 val
,
384 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
385 r
+= NUM_RANKS_PER_SHADOW_REG
) {
386 scc_mgr_set(off
, grp
, val
);
388 if (update
|| (r
== 0)) {
389 writel(grp
, &sdr_scc_mgr
->dqs_ena
);
390 writel(0, &sdr_scc_mgr
->update
);
395 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group
, u32 phase
)
398 * USER although the h/w doesn't support different phases per
399 * shadow register, for simplicity our scc manager modeling
400 * keeps different phase settings per shadow reg, and it's
401 * important for us to keep them in sync to match h/w.
402 * for efficiency, the scan chain update should occur only
405 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET
,
406 read_group
, phase
, 0);
409 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group
,
413 * USER although the h/w doesn't support different phases per
414 * shadow register, for simplicity our scc manager modeling
415 * keeps different phase settings per shadow reg, and it's
416 * important for us to keep them in sync to match h/w.
417 * for efficiency, the scan chain update should occur only
420 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
,
421 write_group
, phase
, 0);
424 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group
,
428 * In shadow register mode, the T11 settings are stored in
429 * registers in the core, which are updated by the DQS_ENA
430 * signals. Not issuing the SCC_MGR_UPD command allows us to
431 * save lots of rank switching overhead, by calling
432 * select_shadow_regs_for_update with update_scan_chains
435 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET
,
436 read_group
, delay
, 1);
437 writel(0, &sdr_scc_mgr
->update
);
441 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
442 * @write_group: Write group
443 * @delay: Delay value
445 * This function sets the OCT output delay in SCC manager.
447 static void scc_mgr_set_oct_out1_delay(const u32 write_group
, const u32 delay
)
449 const int ratio
= RW_MGR_MEM_IF_READ_DQS_WIDTH
/
450 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
;
451 const int base
= write_group
* ratio
;
454 * Load the setting in the SCC manager
455 * Although OCT affects only write data, the OCT delay is controlled
456 * by the DQS logic block which is instantiated once per read group.
457 * For protocols where a write group consists of multiple read groups,
458 * the setting must be set multiple times.
460 for (i
= 0; i
< ratio
; i
++)
461 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET
, base
+ i
, delay
);
465 * scc_mgr_set_hhp_extras() - Set HHP extras.
467 * Load the fixed setting in the SCC manager HHP extras.
469 static void scc_mgr_set_hhp_extras(void)
472 * Load the fixed setting in the SCC manager
473 * bits: 0:0 = 1'b1 - DQS bypass
474 * bits: 1:1 = 1'b1 - DQ bypass
475 * bits: 4:2 = 3'b001 - rfifo_mode
476 * bits: 6:5 = 2'b01 - rfifo clock_select
477 * bits: 7:7 = 1'b0 - separate gating from ungating setting
478 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
480 const u32 value
= (0 << 8) | (0 << 7) | (1 << 5) |
481 (1 << 2) | (1 << 1) | (1 << 0);
482 const u32 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
|
483 SCC_MGR_HHP_GLOBALS_OFFSET
|
484 SCC_MGR_HHP_EXTRAS_OFFSET
;
486 debug_cond(DLEVEL
== 1, "%s:%d Setting HHP Extras\n",
489 debug_cond(DLEVEL
== 1, "%s:%d Done Setting HHP Extras\n",
494 * scc_mgr_zero_all() - Zero all DQS config
496 * Zero all DQS config.
498 static void scc_mgr_zero_all(void)
503 * USER Zero all DQS config settings, across all groups and all
506 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
507 r
+= NUM_RANKS_PER_SHADOW_REG
) {
508 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
510 * The phases actually don't exist on a per-rank basis,
511 * but there's no harm updating them several times, so
512 * let's keep the code simple.
514 scc_mgr_set_dqs_bus_in_delay(i
, IO_DQS_IN_RESERVE
);
515 scc_mgr_set_dqs_en_phase(i
, 0);
516 scc_mgr_set_dqs_en_delay(i
, 0);
519 for (i
= 0; i
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; i
++) {
520 scc_mgr_set_dqdqs_output_phase(i
, 0);
521 /* Arria V/Cyclone V don't have out2. */
522 scc_mgr_set_oct_out1_delay(i
, IO_DQS_OUT_RESERVE
);
526 /* Multicast to all DQS group enables. */
527 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
528 writel(0, &sdr_scc_mgr
->update
);
532 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
533 * @write_group: Write group
535 * Set bypass mode and trigger SCC update.
537 static void scc_set_bypass_mode(const u32 write_group
)
539 /* Multicast to all DQ enables. */
540 writel(0xff, &sdr_scc_mgr
->dq_ena
);
541 writel(0xff, &sdr_scc_mgr
->dm_ena
);
543 /* Update current DQS IO enable. */
544 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
546 /* Update the DQS logic. */
547 writel(write_group
, &sdr_scc_mgr
->dqs_ena
);
550 writel(0, &sdr_scc_mgr
->update
);
554 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
555 * @write_group: Write group
557 * Load DQS settings for Write Group, do not trigger SCC update.
559 static void scc_mgr_load_dqs_for_write_group(const u32 write_group
)
561 const int ratio
= RW_MGR_MEM_IF_READ_DQS_WIDTH
/
562 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
;
563 const int base
= write_group
* ratio
;
566 * Load the setting in the SCC manager
567 * Although OCT affects only write data, the OCT delay is controlled
568 * by the DQS logic block which is instantiated once per read group.
569 * For protocols where a write group consists of multiple read groups,
570 * the setting must be set multiple times.
572 for (i
= 0; i
< ratio
; i
++)
573 writel(base
+ i
, &sdr_scc_mgr
->dqs_ena
);
577 * scc_mgr_zero_group() - Zero all configs for a group
579 * Zero DQ, DM, DQS and OCT configs for a group.
581 static void scc_mgr_zero_group(const u32 write_group
, const int out_only
)
585 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
586 r
+= NUM_RANKS_PER_SHADOW_REG
) {
587 /* Zero all DQ config settings. */
588 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
589 scc_mgr_set_dq_out1_delay(i
, 0);
591 scc_mgr_set_dq_in_delay(i
, 0);
594 /* Multicast to all DQ enables. */
595 writel(0xff, &sdr_scc_mgr
->dq_ena
);
597 /* Zero all DM config settings. */
598 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
599 scc_mgr_set_dm_out1_delay(i
, 0);
601 /* Multicast to all DM enables. */
602 writel(0xff, &sdr_scc_mgr
->dm_ena
);
604 /* Zero all DQS IO settings. */
606 scc_mgr_set_dqs_io_in_delay(0);
608 /* Arria V/Cyclone V don't have out2. */
609 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE
);
610 scc_mgr_set_oct_out1_delay(write_group
, IO_DQS_OUT_RESERVE
);
611 scc_mgr_load_dqs_for_write_group(write_group
);
613 /* Multicast to all DQS IO enables (only 1 in total). */
614 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
616 /* Hit update to zero everything. */
617 writel(0, &sdr_scc_mgr
->update
);
622 * apply and load a particular input delay for the DQ pins in a group
623 * group_bgn is the index of the first dq pin (in the write group)
625 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn
, uint32_t delay
)
629 for (i
= 0, p
= group_bgn
; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++, p
++) {
630 scc_mgr_set_dq_in_delay(p
, delay
);
636 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
637 * @delay: Delay value
639 * Apply and load a particular output delay for the DQ pins in a group.
641 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay
)
645 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
646 scc_mgr_set_dq_out1_delay(i
, delay
);
651 /* apply and load a particular output delay for the DM pins in a group */
652 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1
)
656 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++) {
657 scc_mgr_set_dm_out1_delay(i
, delay1
);
663 /* apply and load delay on both DQS and OCT out1 */
664 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group
,
667 scc_mgr_set_dqs_out1_delay(delay
);
668 scc_mgr_load_dqs_io();
670 scc_mgr_set_oct_out1_delay(write_group
, delay
);
671 scc_mgr_load_dqs_for_write_group(write_group
);
675 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
676 * @write_group: Write group
677 * @delay: Delay value
679 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
681 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group
,
687 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++)
691 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
695 new_delay
= READ_SCC_DQS_IO_OUT2_DELAY
+ delay
;
696 if (new_delay
> IO_IO_OUT2_DELAY_MAX
) {
697 debug_cond(DLEVEL
== 1,
698 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
699 __func__
, __LINE__
, write_group
, delay
, new_delay
,
700 IO_IO_OUT2_DELAY_MAX
,
701 new_delay
- IO_IO_OUT2_DELAY_MAX
);
702 new_delay
-= IO_IO_OUT2_DELAY_MAX
;
703 scc_mgr_set_dqs_out1_delay(new_delay
);
706 scc_mgr_load_dqs_io();
709 new_delay
= READ_SCC_OCT_OUT2_DELAY
+ delay
;
710 if (new_delay
> IO_IO_OUT2_DELAY_MAX
) {
711 debug_cond(DLEVEL
== 1,
712 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
713 __func__
, __LINE__
, write_group
, delay
,
714 new_delay
, IO_IO_OUT2_DELAY_MAX
,
715 new_delay
- IO_IO_OUT2_DELAY_MAX
);
716 new_delay
-= IO_IO_OUT2_DELAY_MAX
;
717 scc_mgr_set_oct_out1_delay(write_group
, new_delay
);
720 scc_mgr_load_dqs_for_write_group(write_group
);
724 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
725 * @write_group: Write group
726 * @delay: Delay value
728 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
731 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group
,
736 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
737 r
+= NUM_RANKS_PER_SHADOW_REG
) {
738 scc_mgr_apply_group_all_out_delay_add(write_group
, delay
);
739 writel(0, &sdr_scc_mgr
->update
);
744 * set_jump_as_return() - Return instruction optimization
746 * Optimization used to recover some slots in ddr3 inst_rom could be
747 * applied to other protocols if we wanted to
749 static void set_jump_as_return(void)
752 * To save space, we replace return with jump to special shared
753 * RETURN instruction so we set the counter to large value so that
756 writel(0xff, &sdr_rw_load_mgr_regs
->load_cntr0
);
757 writel(RW_MGR_RETURN
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
761 * should always use constants as argument to ensure all computations are
762 * performed at compile time
764 static void delay_for_n_mem_clocks(const uint32_t clocks
)
771 debug("%s:%d: clocks=%u ... start\n", __func__
, __LINE__
, clocks
);
774 afi_clocks
= (clocks
+ AFI_RATE_RATIO
-1) / AFI_RATE_RATIO
;
775 /* scale (rounding up) to get afi clocks */
778 * Note, we don't bother accounting for being off a little bit
779 * because of a few extra instructions in outer loops
780 * Note, the loops have a test at the end, and do the test before
781 * the decrement, and so always perform the loop
782 * 1 time more than the counter value
784 if (afi_clocks
== 0) {
786 } else if (afi_clocks
<= 0x100) {
787 inner
= afi_clocks
-1;
790 } else if (afi_clocks
<= 0x10000) {
792 outer
= (afi_clocks
-1) >> 8;
797 c_loop
= (afi_clocks
-1) >> 16;
801 * rom instructions are structured as follows:
803 * IDLE_LOOP2: jnz cntr0, TARGET_A
804 * IDLE_LOOP1: jnz cntr1, TARGET_B
807 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
808 * TARGET_B is set to IDLE_LOOP2 as well
810 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
811 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
813 * a little confusing, but it helps save precious space in the inst_rom
814 * and sequencer rom and keeps the delays more accurate and reduces
817 if (afi_clocks
<= 0x100) {
818 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
819 &sdr_rw_load_mgr_regs
->load_cntr1
);
821 writel(RW_MGR_IDLE_LOOP1
,
822 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
824 writel(RW_MGR_IDLE_LOOP1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
825 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
827 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
828 &sdr_rw_load_mgr_regs
->load_cntr0
);
830 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer
),
831 &sdr_rw_load_mgr_regs
->load_cntr1
);
833 writel(RW_MGR_IDLE_LOOP2
,
834 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
836 writel(RW_MGR_IDLE_LOOP2
,
837 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
839 /* hack to get around compiler not being smart enough */
840 if (afi_clocks
<= 0x10000) {
841 /* only need to run once */
842 writel(RW_MGR_IDLE_LOOP2
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
843 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
846 writel(RW_MGR_IDLE_LOOP2
,
847 SDR_PHYGRP_RWMGRGRP_ADDRESS
|
848 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
849 } while (c_loop
-- != 0);
852 debug("%s:%d clocks=%u ... end\n", __func__
, __LINE__
, clocks
);
856 * rw_mgr_mem_init_load_regs() - Load instruction registers
857 * @cntr0: Counter 0 value
858 * @cntr1: Counter 1 value
859 * @cntr2: Counter 2 value
860 * @jump: Jump instruction value
862 * Load instruction registers.
864 static void rw_mgr_mem_init_load_regs(u32 cntr0
, u32 cntr1
, u32 cntr2
, u32 jump
)
866 uint32_t grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
867 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
870 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0
),
871 &sdr_rw_load_mgr_regs
->load_cntr0
);
872 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1
),
873 &sdr_rw_load_mgr_regs
->load_cntr1
);
874 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2
),
875 &sdr_rw_load_mgr_regs
->load_cntr2
);
877 /* Load jump address */
878 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
879 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
880 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
882 /* Execute count instruction */
883 writel(jump
, grpaddr
);
887 * rw_mgr_mem_load_user() - Load user calibration values
888 * @fin1: Final instruction 1
889 * @fin2: Final instruction 2
890 * @precharge: If 1, precharge the banks at the end
892 * Load user calibration values and optionally precharge the banks.
894 static void rw_mgr_mem_load_user(const u32 fin1
, const u32 fin2
,
897 u32 grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
898 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
901 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
; r
++) {
902 if (param
->skip_ranks
[r
]) {
903 /* request to skip the rank */
908 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
910 /* precharge all banks ... */
912 writel(RW_MGR_PRECHARGE_ALL
, grpaddr
);
915 * USER Use Mirror-ed commands for odd ranks if address
918 if ((RW_MGR_MEM_ADDRESS_MIRRORING
>> r
) & 0x1) {
919 set_jump_as_return();
920 writel(RW_MGR_MRS2_MIRR
, grpaddr
);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS3_MIRR
, grpaddr
);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(RW_MGR_MRS1_MIRR
, grpaddr
);
927 delay_for_n_mem_clocks(4);
928 set_jump_as_return();
929 writel(fin1
, grpaddr
);
931 set_jump_as_return();
932 writel(RW_MGR_MRS2
, grpaddr
);
933 delay_for_n_mem_clocks(4);
934 set_jump_as_return();
935 writel(RW_MGR_MRS3
, grpaddr
);
936 delay_for_n_mem_clocks(4);
937 set_jump_as_return();
938 writel(RW_MGR_MRS1
, grpaddr
);
939 set_jump_as_return();
940 writel(fin2
, grpaddr
);
946 set_jump_as_return();
947 writel(RW_MGR_ZQCL
, grpaddr
);
949 /* tZQinit = tDLLK = 512 ck cycles */
950 delay_for_n_mem_clocks(512);
954 static void rw_mgr_mem_initialize(void)
956 debug("%s:%d\n", __func__
, __LINE__
);
958 /* The reset / cke part of initialization is broadcasted to all ranks */
959 writel(RW_MGR_RANK_ALL
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
960 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
963 * Here's how you load register for a loop
964 * Counters are located @ 0x800
965 * Jump address are located @ 0xC00
966 * For both, registers 0 to 3 are selected using bits 3 and 2, like
967 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
968 * I know this ain't pretty, but Avalon bus throws away the 2 least
972 /* start with memory RESET activated */
977 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
978 * If a and b are the number of iteration in 2 nested loops
979 * it takes the following number of cycles to complete the operation:
980 * number_of_cycles = ((2 + n) * a + 2) * b
981 * where n is the number of instruction in the inner loop
982 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
985 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL
, SEQ_TINIT_CNTR1_VAL
,
987 RW_MGR_INIT_RESET_0_CKE_0
);
989 /* indicate that memory is stable */
990 writel(1, &phy_mgr_cfg
->reset_mem_stbl
);
993 * transition the RESET to high
998 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
999 * If a and b are the number of iteration in 2 nested loops
1000 * it takes the following number of cycles to complete the operation
1001 * number_of_cycles = ((2 + n) * a + 2) * b
1002 * where n is the number of instruction in the inner loop
1003 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1006 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL
, SEQ_TRESET_CNTR1_VAL
,
1007 SEQ_TRESET_CNTR2_VAL
,
1008 RW_MGR_INIT_RESET_1_CKE_0
);
1010 /* bring up clock enable */
1012 /* tXRP < 250 ck cycles */
1013 delay_for_n_mem_clocks(250);
1015 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR
, RW_MGR_MRS0_DLL_RESET
,
1020 * At the end of calibration we have to program the user settings in, and
1021 * USER hand off the memory to the user.
1023 static void rw_mgr_mem_handoff(void)
1025 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR
, RW_MGR_MRS0_USER
, 1);
1027 * USER need to wait tMOD (12CK or 15ns) time before issuing
1028 * other commands, but we will have plenty of NIOS cycles before
1029 * actual handoff so its okay.
1034 * performs a guaranteed read on the patterns we are going to use during a
1035 * read test to ensure memory works
1037 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn
,
1038 uint32_t group
, uint32_t num_tries
, uint32_t *bit_chk
,
1042 uint32_t correct_mask_vg
;
1043 uint32_t tmp_bit_chk
;
1044 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
1045 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1047 uint32_t base_rw_mgr
;
1049 *bit_chk
= param
->read_correct_mask
;
1050 correct_mask_vg
= param
->read_correct_mask_vg
;
1052 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1053 if (param
->skip_ranks
[r
])
1054 /* request to skip the rank */
1058 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1060 /* Load up a constant bursts of read commands */
1061 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1062 writel(RW_MGR_GUARANTEED_READ
,
1063 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1065 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1066 writel(RW_MGR_GUARANTEED_READ_CONT
,
1067 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1070 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
-1; ; vg
--) {
1071 /* reset the fifos to get pointers to known state */
1073 writel(0, &phy_mgr_cmd
->fifo_reset
);
1074 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1075 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1077 tmp_bit_chk
= tmp_bit_chk
<< (RW_MGR_MEM_DQ_PER_READ_DQS
1078 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
);
1080 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1081 writel(RW_MGR_GUARANTEED_READ
, addr
+
1082 ((group
* RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
+
1085 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1086 tmp_bit_chk
= tmp_bit_chk
| (correct_mask_vg
& (~base_rw_mgr
));
1091 *bit_chk
&= tmp_bit_chk
;
1094 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1095 writel(RW_MGR_CLEAR_DQS_ENABLE
, addr
+ (group
<< 2));
1097 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1098 debug_cond(DLEVEL
== 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1099 %lu\n", __func__
, __LINE__
, group
, *bit_chk
, param
->read_correct_mask
,
1100 (long unsigned int)(*bit_chk
== param
->read_correct_mask
));
1101 return *bit_chk
== param
->read_correct_mask
;
1104 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1105 (uint32_t group
, uint32_t num_tries
, uint32_t *bit_chk
)
1107 return rw_mgr_mem_calibrate_read_test_patterns(0, group
,
1108 num_tries
, bit_chk
, 1);
1111 /* load up the patterns we are going to use during a read test */
1112 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn
,
1116 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
1117 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1119 debug("%s:%d\n", __func__
, __LINE__
);
1120 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1121 if (param
->skip_ranks
[r
])
1122 /* request to skip the rank */
1126 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1128 /* Load up a constant bursts */
1129 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1131 writel(RW_MGR_GUARANTEED_WRITE_WAIT0
,
1132 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1134 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1136 writel(RW_MGR_GUARANTEED_WRITE_WAIT1
,
1137 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1139 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr2
);
1141 writel(RW_MGR_GUARANTEED_WRITE_WAIT2
,
1142 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1144 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr3
);
1146 writel(RW_MGR_GUARANTEED_WRITE_WAIT3
,
1147 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1149 writel(RW_MGR_GUARANTEED_WRITE
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1150 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
1153 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1157 * try a read and see if it returns correct data back. has dummy reads
1158 * inserted into the mix used to align dqs enable. has more thorough checks
1159 * than the regular read test.
1161 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn
, uint32_t group
,
1162 uint32_t num_tries
, uint32_t all_correct
, uint32_t *bit_chk
,
1163 uint32_t all_groups
, uint32_t all_ranks
)
1166 uint32_t correct_mask_vg
;
1167 uint32_t tmp_bit_chk
;
1168 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
1169 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1171 uint32_t base_rw_mgr
;
1173 *bit_chk
= param
->read_correct_mask
;
1174 correct_mask_vg
= param
->read_correct_mask_vg
;
1176 uint32_t quick_read_mode
= (((STATIC_CALIB_STEPS
) &
1177 CALIB_SKIP_DELAY_SWEEPS
) && ENABLE_SUPER_QUICK_CALIBRATION
);
1179 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1180 if (param
->skip_ranks
[r
])
1181 /* request to skip the rank */
1185 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1187 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr1
);
1189 writel(RW_MGR_READ_B2B_WAIT1
,
1190 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1192 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr2
);
1193 writel(RW_MGR_READ_B2B_WAIT2
,
1194 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1196 if (quick_read_mode
)
1197 writel(0x1, &sdr_rw_load_mgr_regs
->load_cntr0
);
1198 /* need at least two (1+1) reads to capture failures */
1199 else if (all_groups
)
1200 writel(0x06, &sdr_rw_load_mgr_regs
->load_cntr0
);
1202 writel(0x32, &sdr_rw_load_mgr_regs
->load_cntr0
);
1204 writel(RW_MGR_READ_B2B
,
1205 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1207 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH
*
1208 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
- 1,
1209 &sdr_rw_load_mgr_regs
->load_cntr3
);
1211 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr3
);
1213 writel(RW_MGR_READ_B2B
,
1214 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1217 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
-1; ; vg
--) {
1218 /* reset the fifos to get pointers to known state */
1219 writel(0, &phy_mgr_cmd
->fifo_reset
);
1220 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1221 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1223 tmp_bit_chk
= tmp_bit_chk
<< (RW_MGR_MEM_DQ_PER_READ_DQS
1224 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
);
1227 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_ALL_GROUPS_OFFSET
;
1229 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1231 writel(RW_MGR_READ_B2B
, addr
+
1232 ((group
* RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
+
1235 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1236 tmp_bit_chk
= tmp_bit_chk
| (correct_mask_vg
& ~(base_rw_mgr
));
1241 *bit_chk
&= tmp_bit_chk
;
1244 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1245 writel(RW_MGR_CLEAR_DQS_ENABLE
, addr
+ (group
<< 2));
1248 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1249 debug_cond(DLEVEL
== 2, "%s:%d read_test(%u,ALL,%u) =>\
1250 (%u == %u) => %lu", __func__
, __LINE__
, group
,
1251 all_groups
, *bit_chk
, param
->read_correct_mask
,
1252 (long unsigned int)(*bit_chk
==
1253 param
->read_correct_mask
));
1254 return *bit_chk
== param
->read_correct_mask
;
1256 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1257 debug_cond(DLEVEL
== 2, "%s:%d read_test(%u,ONE,%u) =>\
1258 (%u != %lu) => %lu\n", __func__
, __LINE__
,
1259 group
, all_groups
, *bit_chk
, (long unsigned int)0,
1260 (long unsigned int)(*bit_chk
!= 0x00));
1261 return *bit_chk
!= 0x00;
1265 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group
,
1266 uint32_t num_tries
, uint32_t all_correct
, uint32_t *bit_chk
,
1267 uint32_t all_groups
)
1269 return rw_mgr_mem_calibrate_read_test(0, group
, num_tries
, all_correct
,
1270 bit_chk
, all_groups
, 1);
1273 static void rw_mgr_incr_vfifo(uint32_t grp
, uint32_t *v
)
1275 writel(grp
, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
1279 static void rw_mgr_decr_vfifo(uint32_t grp
, uint32_t *v
)
1283 for (i
= 0; i
< VFIFO_SIZE
-1; i
++)
1284 rw_mgr_incr_vfifo(grp
, v
);
1287 static int find_vfifo_read(uint32_t grp
, uint32_t *bit_chk
)
1290 uint32_t fail_cnt
= 0;
1291 uint32_t test_status
;
1293 for (v
= 0; v
< VFIFO_SIZE
; ) {
1294 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1295 __func__
, __LINE__
, v
);
1296 test_status
= rw_mgr_mem_calibrate_read_test_all_ranks
1297 (grp
, 1, PASS_ONE_BIT
, bit_chk
, 0);
1305 /* fiddle with FIFO */
1306 rw_mgr_incr_vfifo(grp
, &v
);
1309 if (v
>= VFIFO_SIZE
) {
1310 /* no failing read found!! Something must have gone wrong */
1311 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1312 __func__
, __LINE__
);
1319 static int find_working_phase(uint32_t *grp
, uint32_t *bit_chk
,
1320 uint32_t dtaps_per_ptap
, uint32_t *work_bgn
,
1321 uint32_t *v
, uint32_t *d
, uint32_t *p
,
1322 uint32_t *i
, uint32_t *max_working_cnt
)
1324 uint32_t found_begin
= 0;
1325 uint32_t tmp_delay
= 0;
1326 uint32_t test_status
;
1328 for (*d
= 0; *d
<= dtaps_per_ptap
; (*d
)++, tmp_delay
+=
1329 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
) {
1330 *work_bgn
= tmp_delay
;
1331 scc_mgr_set_dqs_en_delay_all_ranks(*grp
, *d
);
1333 for (*i
= 0; *i
< VFIFO_SIZE
; (*i
)++) {
1334 for (*p
= 0; *p
<= IO_DQS_EN_PHASE_MAX
; (*p
)++, *work_bgn
+=
1335 IO_DELAY_PER_OPA_TAP
) {
1336 scc_mgr_set_dqs_en_phase_all_ranks(*grp
, *p
);
1339 rw_mgr_mem_calibrate_read_test_all_ranks
1340 (*grp
, 1, PASS_ONE_BIT
, bit_chk
, 0);
1343 *max_working_cnt
= 1;
1352 if (*p
> IO_DQS_EN_PHASE_MAX
)
1353 /* fiddle with FIFO */
1354 rw_mgr_incr_vfifo(*grp
, v
);
1361 if (*i
>= VFIFO_SIZE
) {
1362 /* cannot find working solution */
1363 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: no vfifo/\
1364 ptap/dtap\n", __func__
, __LINE__
);
1371 static void sdr_backup_phase(uint32_t *grp
, uint32_t *bit_chk
,
1372 uint32_t *work_bgn
, uint32_t *v
, uint32_t *d
,
1373 uint32_t *p
, uint32_t *max_working_cnt
)
1375 uint32_t found_begin
= 0;
1378 /* Special case code for backing up a phase */
1380 *p
= IO_DQS_EN_PHASE_MAX
;
1381 rw_mgr_decr_vfifo(*grp
, v
);
1385 tmp_delay
= *work_bgn
- IO_DELAY_PER_OPA_TAP
;
1386 scc_mgr_set_dqs_en_phase_all_ranks(*grp
, *p
);
1388 for (*d
= 0; *d
<= IO_DQS_EN_DELAY_MAX
&& tmp_delay
< *work_bgn
;
1389 (*d
)++, tmp_delay
+= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
) {
1390 scc_mgr_set_dqs_en_delay_all_ranks(*grp
, *d
);
1392 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp
, 1,
1396 *work_bgn
= tmp_delay
;
1401 /* We have found a working dtap before the ptap found above */
1402 if (found_begin
== 1)
1403 (*max_working_cnt
)++;
1406 * Restore VFIFO to old state before we decremented it
1410 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1412 rw_mgr_incr_vfifo(*grp
, v
);
1415 scc_mgr_set_dqs_en_delay_all_ranks(*grp
, 0);
1418 static int sdr_nonworking_phase(uint32_t *grp
, uint32_t *bit_chk
,
1419 uint32_t *work_bgn
, uint32_t *v
, uint32_t *d
,
1420 uint32_t *p
, uint32_t *i
, uint32_t *max_working_cnt
,
1423 uint32_t found_end
= 0;
1426 *work_end
+= IO_DELAY_PER_OPA_TAP
;
1427 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1428 /* fiddle with FIFO */
1430 rw_mgr_incr_vfifo(*grp
, v
);
1433 for (; *i
< VFIFO_SIZE
+ 1; (*i
)++) {
1434 for (; *p
<= IO_DQS_EN_PHASE_MAX
; (*p
)++, *work_end
1435 += IO_DELAY_PER_OPA_TAP
) {
1436 scc_mgr_set_dqs_en_phase_all_ranks(*grp
, *p
);
1438 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1439 (*grp
, 1, PASS_ONE_BIT
, bit_chk
, 0)) {
1443 (*max_working_cnt
)++;
1450 if (*p
> IO_DQS_EN_PHASE_MAX
) {
1451 /* fiddle with FIFO */
1452 rw_mgr_incr_vfifo(*grp
, v
);
1457 if (*i
>= VFIFO_SIZE
+ 1) {
1458 /* cannot see edge of failing read */
1459 debug_cond(DLEVEL
== 2, "%s:%d sdr_nonworking_phase: end:\
1460 failed\n", __func__
, __LINE__
);
1467 static int sdr_find_window_centre(uint32_t *grp
, uint32_t *bit_chk
,
1468 uint32_t *work_bgn
, uint32_t *v
, uint32_t *d
,
1469 uint32_t *p
, uint32_t *work_mid
,
1475 *work_mid
= (*work_bgn
+ *work_end
) / 2;
1477 debug_cond(DLEVEL
== 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1478 *work_bgn
, *work_end
, *work_mid
);
1479 /* Get the middle delay to be less than a VFIFO delay */
1480 for (*p
= 0; *p
<= IO_DQS_EN_PHASE_MAX
;
1481 (*p
)++, tmp_delay
+= IO_DELAY_PER_OPA_TAP
)
1483 debug_cond(DLEVEL
== 2, "vfifo ptap delay %d\n", tmp_delay
);
1484 while (*work_mid
> tmp_delay
)
1485 *work_mid
-= tmp_delay
;
1486 debug_cond(DLEVEL
== 2, "new work_mid %d\n", *work_mid
);
1489 for (*p
= 0; *p
<= IO_DQS_EN_PHASE_MAX
&& tmp_delay
< *work_mid
;
1490 (*p
)++, tmp_delay
+= IO_DELAY_PER_OPA_TAP
)
1492 tmp_delay
-= IO_DELAY_PER_OPA_TAP
;
1493 debug_cond(DLEVEL
== 2, "new p %d, tmp_delay=%d\n", (*p
) - 1, tmp_delay
);
1494 for (*d
= 0; *d
<= IO_DQS_EN_DELAY_MAX
&& tmp_delay
< *work_mid
; (*d
)++,
1495 tmp_delay
+= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
)
1497 debug_cond(DLEVEL
== 2, "new d %d, tmp_delay=%d\n", *d
, tmp_delay
);
1499 scc_mgr_set_dqs_en_phase_all_ranks(*grp
, (*p
) - 1);
1500 scc_mgr_set_dqs_en_delay_all_ranks(*grp
, *d
);
1503 * push vfifo until we can successfully calibrate. We can do this
1504 * because the largest possible margin in 1 VFIFO cycle.
1506 for (i
= 0; i
< VFIFO_SIZE
; i
++) {
1507 debug_cond(DLEVEL
== 2, "find_dqs_en_phase: center: vfifo=%u\n",
1509 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp
, 1,
1515 /* fiddle with FIFO */
1516 rw_mgr_incr_vfifo(*grp
, v
);
1519 if (i
>= VFIFO_SIZE
) {
1520 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: center: \
1521 failed\n", __func__
, __LINE__
);
1528 /* find a good dqs enable to use */
1529 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp
)
1531 uint32_t v
, d
, p
, i
;
1532 uint32_t max_working_cnt
;
1534 uint32_t dtaps_per_ptap
;
1535 uint32_t work_bgn
, work_mid
, work_end
;
1536 uint32_t found_passing_read
, found_failing_read
, initial_failing_dtap
;
1538 debug("%s:%d %u\n", __func__
, __LINE__
, grp
);
1540 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
1542 scc_mgr_set_dqs_en_delay_all_ranks(grp
, 0);
1543 scc_mgr_set_dqs_en_phase_all_ranks(grp
, 0);
1545 /* ************************************************************** */
1546 /* * Step 0 : Determine number of delay taps for each phase tap * */
1547 dtaps_per_ptap
= IO_DELAY_PER_OPA_TAP
/IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1549 /* ********************************************************* */
1550 /* * Step 1 : First push vfifo until we get a failing read * */
1551 v
= find_vfifo_read(grp
, &bit_chk
);
1553 max_working_cnt
= 0;
1555 /* ******************************************************** */
1556 /* * step 2: find first working phase, increment in ptaps * */
1558 if (find_working_phase(&grp
, &bit_chk
, dtaps_per_ptap
, &work_bgn
, &v
, &d
,
1559 &p
, &i
, &max_working_cnt
) == 0)
1562 work_end
= work_bgn
;
1565 * If d is 0 then the working window covers a phase tap and
1566 * we can follow the old procedure otherwise, we've found the beginning,
1567 * and we need to increment the dtaps until we find the end.
1570 /* ********************************************************* */
1571 /* * step 3a: if we have room, back off by one and
1572 increment in dtaps * */
1574 sdr_backup_phase(&grp
, &bit_chk
, &work_bgn
, &v
, &d
, &p
,
1577 /* ********************************************************* */
1578 /* * step 4a: go forward from working phase to non working
1579 phase, increment in ptaps * */
1580 if (sdr_nonworking_phase(&grp
, &bit_chk
, &work_bgn
, &v
, &d
, &p
,
1581 &i
, &max_working_cnt
, &work_end
) == 0)
1584 /* ********************************************************* */
1585 /* * step 5a: back off one from last, increment in dtaps * */
1587 /* Special case code for backing up a phase */
1589 p
= IO_DQS_EN_PHASE_MAX
;
1590 rw_mgr_decr_vfifo(grp
, &v
);
1595 work_end
-= IO_DELAY_PER_OPA_TAP
;
1596 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1598 /* * The actual increment of dtaps is done outside of
1599 the if/else loop to share code */
1602 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: v/p: \
1603 vfifo=%u ptap=%u\n", __func__
, __LINE__
,
1606 /* ******************************************************* */
1607 /* * step 3-5b: Find the right edge of the window using
1609 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1610 ptap=%u dtap=%u bgn=%u\n", __func__
, __LINE__
,
1613 work_end
= work_bgn
;
1615 /* * The actual increment of dtaps is done outside of the
1616 if/else loop to share code */
1618 /* Only here to counterbalance a subtract later on which is
1619 not needed if this branch of the algorithm is taken */
1623 /* The dtap increment to find the failing edge is done here */
1624 for (; d
<= IO_DQS_EN_DELAY_MAX
; d
++, work_end
+=
1625 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
) {
1626 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: \
1627 end-2: dtap=%u\n", __func__
, __LINE__
, d
);
1628 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1630 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1637 /* Go back to working dtap */
1639 work_end
-= IO_DELAY_PER_DQS_EN_DCHAIN_TAP
;
1641 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1642 ptap=%u dtap=%u end=%u\n", __func__
, __LINE__
,
1643 v
, p
, d
-1, work_end
);
1645 if (work_end
< work_bgn
) {
1647 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: end-2: \
1648 failed\n", __func__
, __LINE__
);
1652 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1653 __func__
, __LINE__
, work_bgn
, work_end
);
1655 /* *************************************************************** */
1657 * * We need to calculate the number of dtaps that equal a ptap
1658 * * To do that we'll back up a ptap and re-find the edge of the
1659 * * window using dtaps
1662 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1663 for tracking\n", __func__
, __LINE__
);
1665 /* Special case code for backing up a phase */
1667 p
= IO_DQS_EN_PHASE_MAX
;
1668 rw_mgr_decr_vfifo(grp
, &v
);
1669 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: backedup \
1670 cycle/phase: v=%u p=%u\n", __func__
, __LINE__
,
1674 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: backedup \
1675 phase only: v=%u p=%u", __func__
, __LINE__
,
1679 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1682 * Increase dtap until we first see a passing read (in case the
1683 * window is smaller than a ptap),
1684 * and then a failing read to mark the edge of the window again
1687 /* Find a passing read */
1688 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: find passing read\n",
1689 __func__
, __LINE__
);
1690 found_passing_read
= 0;
1691 found_failing_read
= 0;
1692 initial_failing_dtap
= d
;
1693 for (; d
<= IO_DQS_EN_DELAY_MAX
; d
++) {
1694 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: testing \
1695 read d=%u\n", __func__
, __LINE__
, d
);
1696 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1698 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1701 found_passing_read
= 1;
1706 if (found_passing_read
) {
1707 /* Find a failing read */
1708 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: find failing \
1709 read\n", __func__
, __LINE__
);
1710 for (d
= d
+ 1; d
<= IO_DQS_EN_DELAY_MAX
; d
++) {
1711 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: \
1712 testing read d=%u\n", __func__
, __LINE__
, d
);
1713 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1715 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1716 (grp
, 1, PASS_ONE_BIT
, &bit_chk
, 0)) {
1717 found_failing_read
= 1;
1722 debug_cond(DLEVEL
== 1, "%s:%d find_dqs_en_phase: failed to \
1723 calculate dtaps", __func__
, __LINE__
);
1724 debug_cond(DLEVEL
== 1, "per ptap. Fall back on static value\n");
1728 * The dynamically calculated dtaps_per_ptap is only valid if we
1729 * found a passing/failing read. If we didn't, it means d hit the max
1730 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1731 * statically calculated value.
1733 if (found_passing_read
&& found_failing_read
)
1734 dtaps_per_ptap
= d
- initial_failing_dtap
;
1736 writel(dtaps_per_ptap
, &sdr_reg_file
->dtaps_per_ptap
);
1737 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1738 - %u = %u", __func__
, __LINE__
, d
,
1739 initial_failing_dtap
, dtaps_per_ptap
);
1741 /* ******************************************** */
1742 /* * step 6: Find the centre of the window * */
1743 if (sdr_find_window_centre(&grp
, &bit_chk
, &work_bgn
, &v
, &d
, &p
,
1744 &work_mid
, &work_end
) == 0)
1747 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: center found: \
1748 vfifo=%u ptap=%u dtap=%u\n", __func__
, __LINE__
,
1754 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1755 * dq_in_delay values
1758 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1759 (uint32_t write_group
, uint32_t read_group
, uint32_t test_bgn
)
1767 const uint32_t delay_step
= IO_IO_IN_DELAY_MAX
/
1768 (RW_MGR_MEM_DQ_PER_READ_DQS
-1);
1769 /* we start at zero, so have one less dq to devide among */
1771 debug("%s:%d (%u,%u,%u)", __func__
, __LINE__
, write_group
, read_group
,
1774 /* try different dq_in_delays since the dq path is shorter than dqs */
1776 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
1777 r
+= NUM_RANKS_PER_SHADOW_REG
) {
1778 for (i
= 0, p
= test_bgn
, d
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++, p
++, d
+= delay_step
) {
1779 debug_cond(DLEVEL
== 1, "%s:%d rw_mgr_mem_calibrate_\
1780 vfifo_find_dqs_", __func__
, __LINE__
);
1781 debug_cond(DLEVEL
== 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1782 write_group
, read_group
);
1783 debug_cond(DLEVEL
== 1, "r=%u, i=%u p=%u d=%u\n", r
, i
, p
, d
);
1784 scc_mgr_set_dq_in_delay(p
, d
);
1787 writel(0, &sdr_scc_mgr
->update
);
1790 found
= rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group
);
1792 debug_cond(DLEVEL
== 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1793 en_phase_sweep_dq", __func__
, __LINE__
);
1794 debug_cond(DLEVEL
== 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1795 chain to zero\n", write_group
, read_group
, found
);
1797 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
1798 r
+= NUM_RANKS_PER_SHADOW_REG
) {
1799 for (i
= 0, p
= test_bgn
; i
< RW_MGR_MEM_DQ_PER_READ_DQS
;
1801 scc_mgr_set_dq_in_delay(p
, 0);
1804 writel(0, &sdr_scc_mgr
->update
);
1810 /* per-bit deskew DQ and center */
1811 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn
,
1812 uint32_t write_group
, uint32_t read_group
, uint32_t test_bgn
,
1813 uint32_t use_read_test
, uint32_t update_fom
)
1815 uint32_t i
, p
, d
, min_index
;
1817 * Store these as signed since there are comparisons with
1821 uint32_t sticky_bit_chk
;
1822 int32_t left_edge
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1823 int32_t right_edge
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1824 int32_t final_dq
[RW_MGR_MEM_DQ_PER_READ_DQS
];
1826 int32_t orig_mid_min
, mid_min
;
1827 int32_t new_dqs
, start_dqs
, start_dqs_en
, shift_dq
, final_dqs
,
1829 int32_t dq_margin
, dqs_margin
;
1831 uint32_t temp_dq_in_delay1
, temp_dq_in_delay2
;
1834 debug("%s:%d: %u %u", __func__
, __LINE__
, read_group
, test_bgn
);
1836 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_DQS_IN_DELAY_OFFSET
;
1837 start_dqs
= readl(addr
+ (read_group
<< 2));
1838 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
)
1839 start_dqs_en
= readl(addr
+ ((read_group
<< 2)
1840 - IO_DQS_EN_DELAY_OFFSET
));
1842 /* set the left and right edge of each bit to an illegal value */
1843 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1845 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1846 left_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1847 right_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1850 /* Search for the left edge of the window for each bit */
1851 for (d
= 0; d
<= IO_IO_IN_DELAY_MAX
; d
++) {
1852 scc_mgr_apply_group_dq_in_delay(write_group
, test_bgn
, d
);
1854 writel(0, &sdr_scc_mgr
->update
);
1857 * Stop searching when the read test doesn't pass AND when
1858 * we've seen a passing read on every bit.
1860 if (use_read_test
) {
1861 stop
= !rw_mgr_mem_calibrate_read_test(rank_bgn
,
1862 read_group
, NUM_READ_PB_TESTS
, PASS_ONE_BIT
,
1865 rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
1868 bit_chk
= bit_chk
>> (RW_MGR_MEM_DQ_PER_READ_DQS
*
1869 (read_group
- (write_group
*
1870 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
1871 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
)));
1872 stop
= (bit_chk
== 0);
1874 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
1875 stop
= stop
&& (sticky_bit_chk
== param
->read_correct_mask
);
1876 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1877 && %u", __func__
, __LINE__
, d
,
1879 param
->read_correct_mask
, stop
);
1884 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1886 /* Remember a passing test as the
1890 /* If a left edge has not been seen yet,
1891 then a future passing test will mark
1892 this edge as the right edge */
1894 IO_IO_IN_DELAY_MAX
+ 1) {
1895 right_edge
[i
] = -(d
+ 1);
1898 bit_chk
= bit_chk
>> 1;
1903 /* Reset DQ delay chains to 0 */
1904 scc_mgr_apply_group_dq_in_delay(test_bgn
, 0);
1906 for (i
= RW_MGR_MEM_DQ_PER_READ_DQS
- 1;; i
--) {
1907 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: left_edge[%u]: \
1908 %d right_edge[%u]: %d\n", __func__
, __LINE__
,
1909 i
, left_edge
[i
], i
, right_edge
[i
]);
1912 * Check for cases where we haven't found the left edge,
1913 * which makes our assignment of the the right edge invalid.
1914 * Reset it to the illegal value.
1916 if ((left_edge
[i
] == IO_IO_IN_DELAY_MAX
+ 1) && (
1917 right_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1)) {
1918 right_edge
[i
] = IO_IO_IN_DELAY_MAX
+ 1;
1919 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: reset \
1920 right_edge[%u]: %d\n", __func__
, __LINE__
,
1925 * Reset sticky bit (except for bits where we have seen
1926 * both the left and right edge).
1928 sticky_bit_chk
= sticky_bit_chk
<< 1;
1929 if ((left_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1) &&
1930 (right_edge
[i
] != IO_IO_IN_DELAY_MAX
+ 1)) {
1931 sticky_bit_chk
= sticky_bit_chk
| 1;
1938 /* Search for the right edge of the window for each bit */
1939 for (d
= 0; d
<= IO_DQS_IN_DELAY_MAX
- start_dqs
; d
++) {
1940 scc_mgr_set_dqs_bus_in_delay(read_group
, d
+ start_dqs
);
1941 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
1942 uint32_t delay
= d
+ start_dqs_en
;
1943 if (delay
> IO_DQS_EN_DELAY_MAX
)
1944 delay
= IO_DQS_EN_DELAY_MAX
;
1945 scc_mgr_set_dqs_en_delay(read_group
, delay
);
1947 scc_mgr_load_dqs(read_group
);
1949 writel(0, &sdr_scc_mgr
->update
);
1952 * Stop searching when the read test doesn't pass AND when
1953 * we've seen a passing read on every bit.
1955 if (use_read_test
) {
1956 stop
= !rw_mgr_mem_calibrate_read_test(rank_bgn
,
1957 read_group
, NUM_READ_PB_TESTS
, PASS_ONE_BIT
,
1960 rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
1963 bit_chk
= bit_chk
>> (RW_MGR_MEM_DQ_PER_READ_DQS
*
1964 (read_group
- (write_group
*
1965 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
1966 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
)));
1967 stop
= (bit_chk
== 0);
1969 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
1970 stop
= stop
&& (sticky_bit_chk
== param
->read_correct_mask
);
1972 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1973 %u && %u", __func__
, __LINE__
, d
,
1974 sticky_bit_chk
, param
->read_correct_mask
, stop
);
1979 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
1981 /* Remember a passing test as
1986 /* If a right edge has not been
1987 seen yet, then a future passing
1988 test will mark this edge as the
1990 if (right_edge
[i
] ==
1991 IO_IO_IN_DELAY_MAX
+ 1) {
1992 left_edge
[i
] = -(d
+ 1);
1995 /* d = 0 failed, but it passed
1996 when testing the left edge,
1997 so it must be marginal,
1999 if (right_edge
[i
] ==
2000 IO_IO_IN_DELAY_MAX
+ 1 &&
2006 /* If a right edge has not been
2007 seen yet, then a future passing
2008 test will mark this edge as the
2010 else if (right_edge
[i
] ==
2011 IO_IO_IN_DELAY_MAX
+
2013 left_edge
[i
] = -(d
+ 1);
2018 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center[r,\
2019 d=%u]: ", __func__
, __LINE__
, d
);
2020 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d ",
2021 (int)(bit_chk
& 1), i
, left_edge
[i
]);
2022 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2024 bit_chk
= bit_chk
>> 1;
2029 /* Check that all bits have a window */
2030 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
2031 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: left_edge[%u]: \
2032 %d right_edge[%u]: %d", __func__
, __LINE__
,
2033 i
, left_edge
[i
], i
, right_edge
[i
]);
2034 if ((left_edge
[i
] == IO_IO_IN_DELAY_MAX
+ 1) || (right_edge
[i
]
2035 == IO_IO_IN_DELAY_MAX
+ 1)) {
2037 * Restore delay chain settings before letting the loop
2038 * in rw_mgr_mem_calibrate_vfifo to retry different
2039 * dqs/ck relationships.
2041 scc_mgr_set_dqs_bus_in_delay(read_group
, start_dqs
);
2042 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2043 scc_mgr_set_dqs_en_delay(read_group
,
2046 scc_mgr_load_dqs(read_group
);
2047 writel(0, &sdr_scc_mgr
->update
);
2049 debug_cond(DLEVEL
== 1, "%s:%d vfifo_center: failed to \
2050 find edge [%u]: %d %d", __func__
, __LINE__
,
2051 i
, left_edge
[i
], right_edge
[i
]);
2052 if (use_read_test
) {
2053 set_failing_group_stage(read_group
*
2054 RW_MGR_MEM_DQ_PER_READ_DQS
+ i
,
2056 CAL_SUBSTAGE_VFIFO_CENTER
);
2058 set_failing_group_stage(read_group
*
2059 RW_MGR_MEM_DQ_PER_READ_DQS
+ i
,
2060 CAL_STAGE_VFIFO_AFTER_WRITES
,
2061 CAL_SUBSTAGE_VFIFO_CENTER
);
2067 /* Find middle of window for each DQ bit */
2068 mid_min
= left_edge
[0] - right_edge
[0];
2070 for (i
= 1; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++) {
2071 mid
= left_edge
[i
] - right_edge
[i
];
2072 if (mid
< mid_min
) {
2079 * -mid_min/2 represents the amount that we need to move DQS.
2080 * If mid_min is odd and positive we'll need to add one to
2081 * make sure the rounding in further calculations is correct
2082 * (always bias to the right), so just add 1 for all positive values.
2087 mid_min
= mid_min
/ 2;
2089 debug_cond(DLEVEL
== 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2090 __func__
, __LINE__
, mid_min
, min_index
);
2092 /* Determine the amount we can change DQS (which is -mid_min) */
2093 orig_mid_min
= mid_min
;
2094 new_dqs
= start_dqs
- mid_min
;
2095 if (new_dqs
> IO_DQS_IN_DELAY_MAX
)
2096 new_dqs
= IO_DQS_IN_DELAY_MAX
;
2097 else if (new_dqs
< 0)
2100 mid_min
= start_dqs
- new_dqs
;
2101 debug_cond(DLEVEL
== 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2104 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2105 if (start_dqs_en
- mid_min
> IO_DQS_EN_DELAY_MAX
)
2106 mid_min
+= start_dqs_en
- mid_min
- IO_DQS_EN_DELAY_MAX
;
2107 else if (start_dqs_en
- mid_min
< 0)
2108 mid_min
+= start_dqs_en
- mid_min
;
2110 new_dqs
= start_dqs
- mid_min
;
2112 debug_cond(DLEVEL
== 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2113 new_dqs=%d mid_min=%d\n", start_dqs
,
2114 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
? start_dqs_en
: -1,
2117 /* Initialize data for export structures */
2118 dqs_margin
= IO_IO_IN_DELAY_MAX
+ 1;
2119 dq_margin
= IO_IO_IN_DELAY_MAX
+ 1;
2121 /* add delay to bring centre of all DQ windows to the same "level" */
2122 for (i
= 0, p
= test_bgn
; i
< RW_MGR_MEM_DQ_PER_READ_DQS
; i
++, p
++) {
2123 /* Use values before divide by 2 to reduce round off error */
2124 shift_dq
= (left_edge
[i
] - right_edge
[i
] -
2125 (left_edge
[min_index
] - right_edge
[min_index
]))/2 +
2126 (orig_mid_min
- mid_min
);
2128 debug_cond(DLEVEL
== 2, "vfifo_center: before: \
2129 shift_dq[%u]=%d\n", i
, shift_dq
);
2131 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_IN_DELAY_OFFSET
;
2132 temp_dq_in_delay1
= readl(addr
+ (p
<< 2));
2133 temp_dq_in_delay2
= readl(addr
+ (i
<< 2));
2135 if (shift_dq
+ (int32_t)temp_dq_in_delay1
>
2136 (int32_t)IO_IO_IN_DELAY_MAX
) {
2137 shift_dq
= (int32_t)IO_IO_IN_DELAY_MAX
- temp_dq_in_delay2
;
2138 } else if (shift_dq
+ (int32_t)temp_dq_in_delay1
< 0) {
2139 shift_dq
= -(int32_t)temp_dq_in_delay1
;
2141 debug_cond(DLEVEL
== 2, "vfifo_center: after: \
2142 shift_dq[%u]=%d\n", i
, shift_dq
);
2143 final_dq
[i
] = temp_dq_in_delay1
+ shift_dq
;
2144 scc_mgr_set_dq_in_delay(p
, final_dq
[i
]);
2147 debug_cond(DLEVEL
== 2, "vfifo_center: margin[%u]=[%d,%d]\n", i
,
2148 left_edge
[i
] - shift_dq
+ (-mid_min
),
2149 right_edge
[i
] + shift_dq
- (-mid_min
));
2150 /* To determine values for export structures */
2151 if (left_edge
[i
] - shift_dq
+ (-mid_min
) < dq_margin
)
2152 dq_margin
= left_edge
[i
] - shift_dq
+ (-mid_min
);
2154 if (right_edge
[i
] + shift_dq
- (-mid_min
) < dqs_margin
)
2155 dqs_margin
= right_edge
[i
] + shift_dq
- (-mid_min
);
2158 final_dqs
= new_dqs
;
2159 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
)
2160 final_dqs_en
= start_dqs_en
- mid_min
;
2163 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS
) {
2164 scc_mgr_set_dqs_en_delay(read_group
, final_dqs_en
);
2165 scc_mgr_load_dqs(read_group
);
2169 scc_mgr_set_dqs_bus_in_delay(read_group
, final_dqs
);
2170 scc_mgr_load_dqs(read_group
);
2171 debug_cond(DLEVEL
== 2, "%s:%d vfifo_center: dq_margin=%d \
2172 dqs_margin=%d", __func__
, __LINE__
,
2173 dq_margin
, dqs_margin
);
2176 * Do not remove this line as it makes sure all of our decisions
2177 * have been applied. Apply the update bit.
2179 writel(0, &sdr_scc_mgr
->update
);
2181 return (dq_margin
>= 0) && (dqs_margin
>= 0);
2185 * calibrate the read valid prediction FIFO.
2187 * - read valid prediction will consist of finding a good DQS enable phase,
2188 * DQS enable delay, DQS input phase, and DQS input delay.
2189 * - we also do a per-bit deskew on the DQ lines.
2191 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group
,
2194 uint32_t p
, d
, rank_bgn
, sr
;
2195 uint32_t dtaps_per_ptap
;
2197 uint32_t grp_calibrated
;
2198 uint32_t write_group
, write_test_bgn
;
2199 uint32_t failed_substage
;
2201 debug("%s:%d: %u %u\n", __func__
, __LINE__
, read_group
, test_bgn
);
2203 /* update info for sims */
2204 reg_file_set_stage(CAL_STAGE_VFIFO
);
2206 write_group
= read_group
;
2207 write_test_bgn
= test_bgn
;
2209 /* USER Determine number of delay taps for each phase tap */
2210 dtaps_per_ptap
= DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP
,
2211 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
) - 1;
2213 /* update info for sims */
2214 reg_file_set_group(read_group
);
2218 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ
);
2219 failed_substage
= CAL_SUBSTAGE_GUARANTEED_READ
;
2221 for (d
= 0; d
<= dtaps_per_ptap
&& grp_calibrated
== 0; d
+= 2) {
2223 * In RLDRAMX we may be messing the delay of pins in
2224 * the same write group but outside of the current read
2225 * the group, but that's ok because we haven't
2226 * calibrated output side yet.
2229 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2233 for (p
= 0; p
<= IO_DQDQS_OUT_PHASE_MAX
&& grp_calibrated
== 0;
2235 /* set a particular dqdqs phase */
2236 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group
, p
);
2238 debug_cond(DLEVEL
== 1, "%s:%d calibrate_vfifo: g=%u \
2239 p=%u d=%u\n", __func__
, __LINE__
,
2243 * Load up the patterns used by read calibration
2244 * using current DQDQS phase.
2246 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2247 if (!(gbl
->phy_debug_mode_flags
&
2248 PHY_DEBUG_DISABLE_GUARANTEED_READ
)) {
2249 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2250 (read_group
, 1, &bit_chk
)) {
2251 debug_cond(DLEVEL
== 1, "%s:%d Guaranteed read test failed:",
2252 __func__
, __LINE__
);
2253 debug_cond(DLEVEL
== 1, " g=%u p=%u d=%u\n",
2261 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2262 (write_group
, read_group
, test_bgn
)) {
2264 * USER Read per-bit deskew can be done on a
2265 * per shadow register basis.
2267 for (rank_bgn
= 0, sr
= 0;
2268 rank_bgn
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2269 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
,
2272 * Determine if this set of ranks
2273 * should be skipped entirely.
2275 if (!param
->skip_shadow_regs
[sr
]) {
2277 * If doing read after write
2278 * calibration, do not update
2279 * FOM, now - do it then.
2281 if (!rw_mgr_mem_calibrate_vfifo_center
2282 (rank_bgn
, write_group
,
2283 read_group
, test_bgn
, 1, 0)) {
2286 CAL_SUBSTAGE_VFIFO_CENTER
;
2292 failed_substage
= CAL_SUBSTAGE_DQS_EN_PHASE
;
2297 if (grp_calibrated
== 0) {
2298 set_failing_group_stage(write_group
, CAL_STAGE_VFIFO
,
2304 * Reset the delay chains back to zero if they have moved > 1
2305 * (check for > 1 because loop will increase d even when pass in
2309 scc_mgr_zero_group(write_group
, 1);
2314 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2315 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group
,
2318 uint32_t rank_bgn
, sr
;
2319 uint32_t grp_calibrated
;
2320 uint32_t write_group
;
2322 debug("%s:%d %u %u", __func__
, __LINE__
, read_group
, test_bgn
);
2324 /* update info for sims */
2326 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES
);
2327 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
2329 write_group
= read_group
;
2331 /* update info for sims */
2332 reg_file_set_group(read_group
);
2335 /* Read per-bit deskew can be done on a per shadow register basis */
2336 for (rank_bgn
= 0, sr
= 0; rank_bgn
< RW_MGR_MEM_NUMBER_OF_RANKS
;
2337 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, ++sr
) {
2338 /* Determine if this set of ranks should be skipped entirely */
2339 if (!param
->skip_shadow_regs
[sr
]) {
2340 /* This is the last calibration round, update FOM here */
2341 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn
,
2352 if (grp_calibrated
== 0) {
2353 set_failing_group_stage(write_group
,
2354 CAL_STAGE_VFIFO_AFTER_WRITES
,
2355 CAL_SUBSTAGE_VFIFO_CENTER
);
2362 /* Calibrate LFIFO to find smallest read latency */
2363 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2368 debug("%s:%d\n", __func__
, __LINE__
);
2370 /* update info for sims */
2371 reg_file_set_stage(CAL_STAGE_LFIFO
);
2372 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY
);
2374 /* Load up the patterns used by read calibration for all ranks */
2375 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2379 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2380 debug_cond(DLEVEL
== 2, "%s:%d lfifo: read_lat=%u",
2381 __func__
, __LINE__
, gbl
->curr_read_lat
);
2383 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2391 /* reduce read latency and see if things are working */
2393 gbl
->curr_read_lat
--;
2394 } while (gbl
->curr_read_lat
> 0);
2396 /* reset the fifos to get pointers to known state */
2398 writel(0, &phy_mgr_cmd
->fifo_reset
);
2401 /* add a fudge factor to the read latency that was determined */
2402 gbl
->curr_read_lat
+= 2;
2403 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2404 debug_cond(DLEVEL
== 2, "%s:%d lfifo: success: using \
2405 read_lat=%u\n", __func__
, __LINE__
,
2406 gbl
->curr_read_lat
);
2409 set_failing_group_stage(0xff, CAL_STAGE_LFIFO
,
2410 CAL_SUBSTAGE_READ_LATENCY
);
2412 debug_cond(DLEVEL
== 2, "%s:%d lfifo: failed at initial \
2413 read_lat=%u\n", __func__
, __LINE__
,
2414 gbl
->curr_read_lat
);
2420 * issue write test command.
2421 * two variants are provided. one that just tests a write pattern and
2422 * another that tests datamask functionality.
2424 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group
,
2427 uint32_t mcc_instruction
;
2428 uint32_t quick_write_mode
= (((STATIC_CALIB_STEPS
) & CALIB_SKIP_WRITES
) &&
2429 ENABLE_SUPER_QUICK_CALIBRATION
);
2430 uint32_t rw_wl_nop_cycles
;
2434 * Set counter and jump addresses for the right
2435 * number of NOP cycles.
2436 * The number of supported NOP cycles can range from -1 to infinity
2437 * Three different cases are handled:
2439 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2440 * mechanism will be used to insert the right number of NOPs
2442 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2443 * issuing the write command will jump straight to the
2444 * micro-instruction that turns on DQS (for DDRx), or outputs write
2445 * data (for RLD), skipping
2446 * the NOP micro-instruction all together
2448 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2449 * turned on in the same micro-instruction that issues the write
2450 * command. Then we need
2451 * to directly jump to the micro-instruction that sends out the data
2453 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2454 * (2 and 3). One jump-counter (0) is used to perform multiple
2455 * write-read operations.
2456 * one counter left to issue this command in "multiple-group" mode
2459 rw_wl_nop_cycles
= gbl
->rw_wl_nop_cycles
;
2461 if (rw_wl_nop_cycles
== -1) {
2463 * CNTR 2 - We want to execute the special write operation that
2464 * turns on DQS right away and then skip directly to the
2465 * instruction that sends out the data. We set the counter to a
2466 * large number so that the jump is always taken.
2468 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
2470 /* CNTR 3 - Not used */
2472 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1
;
2473 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA
,
2474 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2475 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP
,
2476 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2478 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0_WL_1
;
2479 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA
,
2480 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2481 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP
,
2482 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2484 } else if (rw_wl_nop_cycles
== 0) {
2486 * CNTR 2 - We want to skip the NOP operation and go straight
2487 * to the DQS enable instruction. We set the counter to a large
2488 * number so that the jump is always taken.
2490 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
2492 /* CNTR 3 - Not used */
2494 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0
;
2495 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS
,
2496 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2498 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0
;
2499 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS
,
2500 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2504 * CNTR 2 - In this case we want to execute the next instruction
2505 * and NOT take the jump. So we set the counter to 0. The jump
2506 * address doesn't count.
2508 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr2
);
2509 writel(0x0, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
2512 * CNTR 3 - Set the nop counter to the number of cycles we
2513 * need to loop for, minus 1.
2515 writel(rw_wl_nop_cycles
- 1, &sdr_rw_load_mgr_regs
->load_cntr3
);
2517 mcc_instruction
= RW_MGR_LFSR_WR_RD_DM_BANK_0
;
2518 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP
,
2519 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2521 mcc_instruction
= RW_MGR_LFSR_WR_RD_BANK_0
;
2522 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP
,
2523 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
2527 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
2528 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
2530 if (quick_write_mode
)
2531 writel(0x08, &sdr_rw_load_mgr_regs
->load_cntr0
);
2533 writel(0x40, &sdr_rw_load_mgr_regs
->load_cntr0
);
2535 writel(mcc_instruction
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
2538 * CNTR 1 - This is used to ensure enough time elapses
2539 * for read data to come back.
2541 writel(0x30, &sdr_rw_load_mgr_regs
->load_cntr1
);
2544 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT
,
2545 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
2547 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT
,
2548 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
2551 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
2552 writel(mcc_instruction
, addr
+ (group
<< 2));
2555 /* Test writes, can check for a single bit pass or multiple bit pass */
2556 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn
,
2557 uint32_t write_group
, uint32_t use_dm
, uint32_t all_correct
,
2558 uint32_t *bit_chk
, uint32_t all_ranks
)
2561 uint32_t correct_mask_vg
;
2562 uint32_t tmp_bit_chk
;
2564 uint32_t rank_end
= all_ranks
? RW_MGR_MEM_NUMBER_OF_RANKS
:
2565 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
2566 uint32_t addr_rw_mgr
;
2567 uint32_t base_rw_mgr
;
2569 *bit_chk
= param
->write_correct_mask
;
2570 correct_mask_vg
= param
->write_correct_mask_vg
;
2572 for (r
= rank_bgn
; r
< rank_end
; r
++) {
2573 if (param
->skip_ranks
[r
]) {
2574 /* request to skip the rank */
2579 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
2582 addr_rw_mgr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
;
2583 for (vg
= RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
-1; ; vg
--) {
2584 /* reset the fifos to get pointers to known state */
2585 writel(0, &phy_mgr_cmd
->fifo_reset
);
2587 tmp_bit_chk
= tmp_bit_chk
<<
2588 (RW_MGR_MEM_DQ_PER_WRITE_DQS
/
2589 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
);
2590 rw_mgr_mem_calibrate_write_test_issue(write_group
*
2591 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
+vg
,
2594 base_rw_mgr
= readl(addr_rw_mgr
);
2595 tmp_bit_chk
= tmp_bit_chk
| (correct_mask_vg
& ~(base_rw_mgr
));
2599 *bit_chk
&= tmp_bit_chk
;
2603 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
2604 debug_cond(DLEVEL
== 2, "write_test(%u,%u,ALL) : %u == \
2605 %u => %lu", write_group
, use_dm
,
2606 *bit_chk
, param
->write_correct_mask
,
2607 (long unsigned int)(*bit_chk
==
2608 param
->write_correct_mask
));
2609 return *bit_chk
== param
->write_correct_mask
;
2611 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
2612 debug_cond(DLEVEL
== 2, "write_test(%u,%u,ONE) : %u != ",
2613 write_group
, use_dm
, *bit_chk
);
2614 debug_cond(DLEVEL
== 2, "%lu" " => %lu", (long unsigned int)0,
2615 (long unsigned int)(*bit_chk
!= 0));
2616 return *bit_chk
!= 0x00;
2621 * center all windows. do per-bit-deskew to possibly increase size of
2624 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn
,
2625 uint32_t write_group
, uint32_t test_bgn
)
2627 uint32_t i
, p
, min_index
;
2630 * Store these as signed since there are comparisons with
2634 uint32_t sticky_bit_chk
;
2635 int32_t left_edge
[RW_MGR_MEM_DQ_PER_WRITE_DQS
];
2636 int32_t right_edge
[RW_MGR_MEM_DQ_PER_WRITE_DQS
];
2638 int32_t mid_min
, orig_mid_min
;
2639 int32_t new_dqs
, start_dqs
, shift_dq
;
2640 int32_t dq_margin
, dqs_margin
, dm_margin
;
2642 uint32_t temp_dq_out1_delay
;
2645 debug("%s:%d %u %u", __func__
, __LINE__
, write_group
, test_bgn
);
2649 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_OUT1_DELAY_OFFSET
;
2650 start_dqs
= readl(addr
+
2651 (RW_MGR_MEM_DQ_PER_WRITE_DQS
<< 2));
2653 /* per-bit deskew */
2656 * set the left and right edge of each bit to an illegal value
2657 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2660 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2661 left_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2662 right_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2665 /* Search for the left edge of the window for each bit */
2666 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
; d
++) {
2667 scc_mgr_apply_group_dq_out1_delay(write_group
, d
);
2669 writel(0, &sdr_scc_mgr
->update
);
2672 * Stop searching when the read test doesn't pass AND when
2673 * we've seen a passing read on every bit.
2675 stop
= !rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
2676 0, PASS_ONE_BIT
, &bit_chk
, 0);
2677 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
2678 stop
= stop
&& (sticky_bit_chk
== param
->write_correct_mask
);
2679 debug_cond(DLEVEL
== 2, "write_center(left): dtap=%d => %u \
2680 == %u && %u [bit_chk= %u ]\n",
2681 d
, sticky_bit_chk
, param
->write_correct_mask
,
2687 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2690 * Remember a passing test as the
2696 * If a left edge has not been seen
2697 * yet, then a future passing test will
2698 * mark this edge as the right edge.
2701 IO_IO_OUT1_DELAY_MAX
+ 1) {
2702 right_edge
[i
] = -(d
+ 1);
2705 debug_cond(DLEVEL
== 2, "write_center[l,d=%d):", d
);
2706 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d",
2707 (int)(bit_chk
& 1), i
, left_edge
[i
]);
2708 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2710 bit_chk
= bit_chk
>> 1;
2715 /* Reset DQ delay chains to 0 */
2716 scc_mgr_apply_group_dq_out1_delay(0);
2718 for (i
= RW_MGR_MEM_DQ_PER_WRITE_DQS
- 1;; i
--) {
2719 debug_cond(DLEVEL
== 2, "%s:%d write_center: left_edge[%u]: \
2720 %d right_edge[%u]: %d\n", __func__
, __LINE__
,
2721 i
, left_edge
[i
], i
, right_edge
[i
]);
2724 * Check for cases where we haven't found the left edge,
2725 * which makes our assignment of the the right edge invalid.
2726 * Reset it to the illegal value.
2728 if ((left_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1) &&
2729 (right_edge
[i
] != IO_IO_OUT1_DELAY_MAX
+ 1)) {
2730 right_edge
[i
] = IO_IO_OUT1_DELAY_MAX
+ 1;
2731 debug_cond(DLEVEL
== 2, "%s:%d write_center: reset \
2732 right_edge[%u]: %d\n", __func__
, __LINE__
,
2737 * Reset sticky bit (except for bits where we have
2738 * seen the left edge).
2740 sticky_bit_chk
= sticky_bit_chk
<< 1;
2741 if ((left_edge
[i
] != IO_IO_OUT1_DELAY_MAX
+ 1))
2742 sticky_bit_chk
= sticky_bit_chk
| 1;
2748 /* Search for the right edge of the window for each bit */
2749 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
- start_dqs
; d
++) {
2750 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
2753 writel(0, &sdr_scc_mgr
->update
);
2756 * Stop searching when the read test doesn't pass AND when
2757 * we've seen a passing read on every bit.
2759 stop
= !rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
2760 0, PASS_ONE_BIT
, &bit_chk
, 0);
2762 sticky_bit_chk
= sticky_bit_chk
| bit_chk
;
2763 stop
= stop
&& (sticky_bit_chk
== param
->write_correct_mask
);
2765 debug_cond(DLEVEL
== 2, "write_center (right): dtap=%u => %u == \
2766 %u && %u\n", d
, sticky_bit_chk
,
2767 param
->write_correct_mask
, stop
);
2771 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
;
2773 /* d = 0 failed, but it passed when
2774 testing the left edge, so it must be
2775 marginal, set it to -1 */
2776 if (right_edge
[i
] ==
2777 IO_IO_OUT1_DELAY_MAX
+ 1 &&
2779 IO_IO_OUT1_DELAY_MAX
+ 1) {
2786 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2789 * Remember a passing test as
2796 * If a right edge has not
2797 * been seen yet, then a future
2798 * passing test will mark this
2799 * edge as the left edge.
2801 if (right_edge
[i
] ==
2802 IO_IO_OUT1_DELAY_MAX
+ 1)
2803 left_edge
[i
] = -(d
+ 1);
2806 * d = 0 failed, but it passed
2807 * when testing the left edge,
2808 * so it must be marginal, set
2811 if (right_edge
[i
] ==
2812 IO_IO_OUT1_DELAY_MAX
+ 1 &&
2814 IO_IO_OUT1_DELAY_MAX
+ 1)
2817 * If a right edge has not been
2818 * seen yet, then a future
2819 * passing test will mark this
2820 * edge as the left edge.
2822 else if (right_edge
[i
] ==
2823 IO_IO_OUT1_DELAY_MAX
+
2825 left_edge
[i
] = -(d
+ 1);
2828 debug_cond(DLEVEL
== 2, "write_center[r,d=%d):", d
);
2829 debug_cond(DLEVEL
== 2, "bit_chk_test=%d left_edge[%u]: %d",
2830 (int)(bit_chk
& 1), i
, left_edge
[i
]);
2831 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2833 bit_chk
= bit_chk
>> 1;
2838 /* Check that all bits have a window */
2839 for (i
= 0; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2840 debug_cond(DLEVEL
== 2, "%s:%d write_center: left_edge[%u]: \
2841 %d right_edge[%u]: %d", __func__
, __LINE__
,
2842 i
, left_edge
[i
], i
, right_edge
[i
]);
2843 if ((left_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1) ||
2844 (right_edge
[i
] == IO_IO_OUT1_DELAY_MAX
+ 1)) {
2845 set_failing_group_stage(test_bgn
+ i
,
2847 CAL_SUBSTAGE_WRITES_CENTER
);
2852 /* Find middle of window for each DQ bit */
2853 mid_min
= left_edge
[0] - right_edge
[0];
2855 for (i
= 1; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++) {
2856 mid
= left_edge
[i
] - right_edge
[i
];
2857 if (mid
< mid_min
) {
2864 * -mid_min/2 represents the amount that we need to move DQS.
2865 * If mid_min is odd and positive we'll need to add one to
2866 * make sure the rounding in further calculations is correct
2867 * (always bias to the right), so just add 1 for all positive values.
2871 mid_min
= mid_min
/ 2;
2872 debug_cond(DLEVEL
== 1, "%s:%d write_center: mid_min=%d\n", __func__
,
2875 /* Determine the amount we can change DQS (which is -mid_min) */
2876 orig_mid_min
= mid_min
;
2877 new_dqs
= start_dqs
;
2879 debug_cond(DLEVEL
== 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2880 mid_min=%d\n", __func__
, __LINE__
, start_dqs
, new_dqs
, mid_min
);
2881 /* Initialize data for export structures */
2882 dqs_margin
= IO_IO_OUT1_DELAY_MAX
+ 1;
2883 dq_margin
= IO_IO_OUT1_DELAY_MAX
+ 1;
2885 /* add delay to bring centre of all DQ windows to the same "level" */
2886 for (i
= 0, p
= test_bgn
; i
< RW_MGR_MEM_DQ_PER_WRITE_DQS
; i
++, p
++) {
2887 /* Use values before divide by 2 to reduce round off error */
2888 shift_dq
= (left_edge
[i
] - right_edge
[i
] -
2889 (left_edge
[min_index
] - right_edge
[min_index
]))/2 +
2890 (orig_mid_min
- mid_min
);
2892 debug_cond(DLEVEL
== 2, "%s:%d write_center: before: shift_dq \
2893 [%u]=%d\n", __func__
, __LINE__
, i
, shift_dq
);
2895 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| SCC_MGR_IO_OUT1_DELAY_OFFSET
;
2896 temp_dq_out1_delay
= readl(addr
+ (i
<< 2));
2897 if (shift_dq
+ (int32_t)temp_dq_out1_delay
>
2898 (int32_t)IO_IO_OUT1_DELAY_MAX
) {
2899 shift_dq
= (int32_t)IO_IO_OUT1_DELAY_MAX
- temp_dq_out1_delay
;
2900 } else if (shift_dq
+ (int32_t)temp_dq_out1_delay
< 0) {
2901 shift_dq
= -(int32_t)temp_dq_out1_delay
;
2903 debug_cond(DLEVEL
== 2, "write_center: after: shift_dq[%u]=%d\n",
2905 scc_mgr_set_dq_out1_delay(i
, temp_dq_out1_delay
+ shift_dq
);
2908 debug_cond(DLEVEL
== 2, "write_center: margin[%u]=[%d,%d]\n", i
,
2909 left_edge
[i
] - shift_dq
+ (-mid_min
),
2910 right_edge
[i
] + shift_dq
- (-mid_min
));
2911 /* To determine values for export structures */
2912 if (left_edge
[i
] - shift_dq
+ (-mid_min
) < dq_margin
)
2913 dq_margin
= left_edge
[i
] - shift_dq
+ (-mid_min
);
2915 if (right_edge
[i
] + shift_dq
- (-mid_min
) < dqs_margin
)
2916 dqs_margin
= right_edge
[i
] + shift_dq
- (-mid_min
);
2920 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
2921 writel(0, &sdr_scc_mgr
->update
);
2924 debug_cond(DLEVEL
== 2, "%s:%d write_center: DM\n", __func__
, __LINE__
);
2927 * set the left and right edge of each bit to an illegal value,
2928 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2930 left_edge
[0] = IO_IO_OUT1_DELAY_MAX
+ 1;
2931 right_edge
[0] = IO_IO_OUT1_DELAY_MAX
+ 1;
2932 int32_t bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2933 int32_t end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2934 int32_t bgn_best
= IO_IO_OUT1_DELAY_MAX
+ 1;
2935 int32_t end_best
= IO_IO_OUT1_DELAY_MAX
+ 1;
2936 int32_t win_best
= 0;
2938 /* Search for the/part of the window with DM shift */
2939 for (d
= IO_IO_OUT1_DELAY_MAX
; d
>= 0; d
-= DELTA_D
) {
2940 scc_mgr_apply_group_dm_out1_delay(d
);
2941 writel(0, &sdr_scc_mgr
->update
);
2943 if (rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 1,
2944 PASS_ALL_BITS
, &bit_chk
,
2946 /* USE Set current end of the window */
2949 * If a starting edge of our window has not been seen
2950 * this is our current start of the DM window.
2952 if (bgn_curr
== IO_IO_OUT1_DELAY_MAX
+ 1)
2956 * If current window is bigger than best seen.
2957 * Set best seen to be current window.
2959 if ((end_curr
-bgn_curr
+1) > win_best
) {
2960 win_best
= end_curr
-bgn_curr
+1;
2961 bgn_best
= bgn_curr
;
2962 end_best
= end_curr
;
2965 /* We just saw a failing test. Reset temp edge */
2966 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2967 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2972 /* Reset DM delay chains to 0 */
2973 scc_mgr_apply_group_dm_out1_delay(0);
2976 * Check to see if the current window nudges up aganist 0 delay.
2977 * If so we need to continue the search by shifting DQS otherwise DQS
2978 * search begins as a new search. */
2979 if (end_curr
!= 0) {
2980 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2981 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
2984 /* Search for the/part of the window with DQS shifts */
2985 for (d
= 0; d
<= IO_IO_OUT1_DELAY_MAX
- new_dqs
; d
+= DELTA_D
) {
2987 * Note: This only shifts DQS, so are we limiting ourselve to
2988 * width of DQ unnecessarily.
2990 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
2993 writel(0, &sdr_scc_mgr
->update
);
2994 if (rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 1,
2995 PASS_ALL_BITS
, &bit_chk
,
2997 /* USE Set current end of the window */
3000 * If a beginning edge of our window has not been seen
3001 * this is our current begin of the DM window.
3003 if (bgn_curr
== IO_IO_OUT1_DELAY_MAX
+ 1)
3007 * If current window is bigger than best seen. Set best
3008 * seen to be current window.
3010 if ((end_curr
-bgn_curr
+1) > win_best
) {
3011 win_best
= end_curr
-bgn_curr
+1;
3012 bgn_best
= bgn_curr
;
3013 end_best
= end_curr
;
3016 /* We just saw a failing test. Reset temp edge */
3017 bgn_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3018 end_curr
= IO_IO_OUT1_DELAY_MAX
+ 1;
3020 /* Early exit optimization: if ther remaining delay
3021 chain space is less than already seen largest window
3024 (IO_IO_OUT1_DELAY_MAX
- new_dqs
- d
)) {
3030 /* assign left and right edge for cal and reporting; */
3031 left_edge
[0] = -1*bgn_best
;
3032 right_edge
[0] = end_best
;
3034 debug_cond(DLEVEL
== 2, "%s:%d dm_calib: left=%d right=%d\n", __func__
,
3035 __LINE__
, left_edge
[0], right_edge
[0]);
3037 /* Move DQS (back to orig) */
3038 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
3042 /* Find middle of window for the DM bit */
3043 mid
= (left_edge
[0] - right_edge
[0]) / 2;
3045 /* only move right, since we are not moving DQS/DQ */
3049 /* dm_marign should fail if we never find a window */
3053 dm_margin
= left_edge
[0] - mid
;
3055 scc_mgr_apply_group_dm_out1_delay(mid
);
3056 writel(0, &sdr_scc_mgr
->update
);
3058 debug_cond(DLEVEL
== 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3059 dm_margin=%d\n", __func__
, __LINE__
, left_edge
[0],
3060 right_edge
[0], mid
, dm_margin
);
3062 gbl
->fom_out
+= dq_margin
+ dqs_margin
;
3064 debug_cond(DLEVEL
== 2, "%s:%d write_center: dq_margin=%d \
3065 dqs_margin=%d dm_margin=%d\n", __func__
, __LINE__
,
3066 dq_margin
, dqs_margin
, dm_margin
);
3069 * Do not remove this line as it makes sure all of our
3070 * decisions have been applied.
3072 writel(0, &sdr_scc_mgr
->update
);
3073 return (dq_margin
>= 0) && (dqs_margin
>= 0) && (dm_margin
>= 0);
3076 /* calibrate the write operations */
3077 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn
, uint32_t g
,
3080 /* update info for sims */
3081 debug("%s:%d %u %u\n", __func__
, __LINE__
, g
, test_bgn
);
3083 reg_file_set_stage(CAL_STAGE_WRITES
);
3084 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER
);
3086 reg_file_set_group(g
);
3088 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn
, g
, test_bgn
)) {
3089 set_failing_group_stage(g
, CAL_STAGE_WRITES
,
3090 CAL_SUBSTAGE_WRITES_CENTER
);
3098 * mem_precharge_and_activate() - Precharge all banks and activate
3100 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3102 static void mem_precharge_and_activate(void)
3106 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
; r
++) {
3107 /* Test if the rank should be skipped. */
3108 if (param
->skip_ranks
[r
])
3112 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
3114 /* Precharge all banks. */
3115 writel(RW_MGR_PRECHARGE_ALL
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3116 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3118 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr0
);
3119 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1
,
3120 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
3122 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr1
);
3123 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2
,
3124 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
3126 /* Activate rows. */
3127 writel(RW_MGR_ACTIVATE_0_AND_1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3128 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3133 * mem_init_latency() - Configure memory RLAT and WLAT settings
3135 * Configure memory RLAT and WLAT parameters.
3137 static void mem_init_latency(void)
3140 * For AV/CV, LFIFO is hardened and always runs at full rate
3141 * so max latency in AFI clocks, used here, is correspondingly
3144 const u32 max_latency
= (1 << MAX_LATENCY_COUNT_WIDTH
) - 1;
3147 debug("%s:%d\n", __func__
, __LINE__
);
3150 * Read in write latency.
3151 * WL for Hard PHY does not include additive latency.
3153 wlat
= readl(&data_mgr
->t_wl_add
);
3154 wlat
+= readl(&data_mgr
->mem_t_add
);
3156 gbl
->rw_wl_nop_cycles
= wlat
- 1;
3158 /* Read in readl latency. */
3159 rlat
= readl(&data_mgr
->t_rl_add
);
3161 /* Set a pretty high read latency initially. */
3162 gbl
->curr_read_lat
= rlat
+ 16;
3163 if (gbl
->curr_read_lat
> max_latency
)
3164 gbl
->curr_read_lat
= max_latency
;
3166 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3168 /* Advertise write latency. */
3169 writel(wlat
, &phy_mgr_cfg
->afi_wlat
);
3172 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3173 static void mem_skip_calibrate(void)
3175 uint32_t vfifo_offset
;
3178 debug("%s:%d\n", __func__
, __LINE__
);
3179 /* Need to update every shadow register set used by the interface */
3180 for (r
= 0; r
< RW_MGR_MEM_NUMBER_OF_RANKS
;
3181 r
+= NUM_RANKS_PER_SHADOW_REG
) {
3183 * Set output phase alignment settings appropriate for
3186 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3187 scc_mgr_set_dqs_en_phase(i
, 0);
3188 #if IO_DLL_CHAIN_LENGTH == 6
3189 scc_mgr_set_dqdqs_output_phase(i
, 6);
3191 scc_mgr_set_dqdqs_output_phase(i
, 7);
3196 * Write data arrives to the I/O two cycles before write
3197 * latency is reached (720 deg).
3198 * -> due to bit-slip in a/c bus
3199 * -> to allow board skew where dqs is longer than ck
3200 * -> how often can this happen!?
3201 * -> can claim back some ptaps for high freq
3202 * support if we can relax this, but i digress...
3204 * The write_clk leads mem_ck by 90 deg
3205 * The minimum ptap of the OPA is 180 deg
3206 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3207 * The write_clk is always delayed by 2 ptaps
3209 * Hence, to make DQS aligned to CK, we need to delay
3211 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3213 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3214 * gives us the number of ptaps, which simplies to:
3216 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3218 scc_mgr_set_dqdqs_output_phase(i
, (1.25 *
3219 IO_DLL_CHAIN_LENGTH
- 2));
3221 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
3222 writel(0xff, &sdr_scc_mgr
->dqs_io_ena
);
3224 for (i
= 0; i
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; i
++) {
3225 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3226 SCC_MGR_GROUP_COUNTER_OFFSET
);
3228 writel(0xff, &sdr_scc_mgr
->dq_ena
);
3229 writel(0xff, &sdr_scc_mgr
->dm_ena
);
3230 writel(0, &sdr_scc_mgr
->update
);
3233 /* Compensate for simulation model behaviour */
3234 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3235 scc_mgr_set_dqs_bus_in_delay(i
, 10);
3236 scc_mgr_load_dqs(i
);
3238 writel(0, &sdr_scc_mgr
->update
);
3241 * ArriaV has hard FIFOs that can only be initialized by incrementing
3244 vfifo_offset
= CALIB_VFIFO_OFFSET
;
3245 for (j
= 0; j
< vfifo_offset
; j
++) {
3246 writel(0xff, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
3248 writel(0, &phy_mgr_cmd
->fifo_reset
);
3251 * For ACV with hard lfifo, we get the skip-cal setting from
3252 * generation-time constant.
3254 gbl
->curr_read_lat
= CALIB_LFIFO_OFFSET
;
3255 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3258 /* Memory calibration entry point */
3259 static uint32_t mem_calibrate(void)
3262 uint32_t rank_bgn
, sr
;
3263 uint32_t write_group
, write_test_bgn
;
3264 uint32_t read_group
, read_test_bgn
;
3265 uint32_t run_groups
, current_run
;
3266 uint32_t failing_groups
= 0;
3267 uint32_t group_failed
= 0;
3268 uint32_t sr_failed
= 0;
3270 debug("%s:%d\n", __func__
, __LINE__
);
3272 /* Initialize the data settings */
3273 gbl
->error_substage
= CAL_SUBSTAGE_NIL
;
3274 gbl
->error_stage
= CAL_STAGE_NIL
;
3275 gbl
->error_group
= 0xff;
3279 /* Initialize WLAT and RLAT. */
3282 /* Initialize bit slips. */
3283 mem_precharge_and_activate();
3285 for (i
= 0; i
< RW_MGR_MEM_IF_READ_DQS_WIDTH
; i
++) {
3286 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3287 SCC_MGR_GROUP_COUNTER_OFFSET
);
3288 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3290 scc_mgr_set_hhp_extras();
3292 scc_set_bypass_mode(i
);
3295 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
) {
3297 * Set VFIFO and LFIFO to instant-on settings in skip
3300 mem_skip_calibrate();
3302 for (i
= 0; i
< NUM_CALIB_REPEAT
; i
++) {
3304 * Zero all delay chain/phase settings for all
3305 * groups and all shadow register sets.
3309 run_groups
= ~param
->skip_groups
;
3311 for (write_group
= 0, write_test_bgn
= 0; write_group
3312 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH
; write_group
++,
3313 write_test_bgn
+= RW_MGR_MEM_DQ_PER_WRITE_DQS
) {
3314 /* Initialized the group failure */
3317 current_run
= run_groups
& ((1 <<
3318 RW_MGR_NUM_DQS_PER_WRITE_GROUP
) - 1);
3319 run_groups
= run_groups
>>
3320 RW_MGR_NUM_DQS_PER_WRITE_GROUP
;
3322 if (current_run
== 0)
3325 writel(write_group
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3326 SCC_MGR_GROUP_COUNTER_OFFSET
);
3327 scc_mgr_zero_group(write_group
, 0);
3329 for (read_group
= write_group
*
3330 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
3331 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
,
3333 read_group
< (write_group
+ 1) *
3334 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
3335 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
&&
3337 read_group
++, read_test_bgn
+=
3338 RW_MGR_MEM_DQ_PER_READ_DQS
) {
3339 /* Calibrate the VFIFO */
3340 if (!((STATIC_CALIB_STEPS
) &
3341 CALIB_SKIP_VFIFO
)) {
3342 if (!rw_mgr_mem_calibrate_vfifo
3348 phy_debug_mode_flags
&
3349 PHY_DEBUG_SWEEP_ALL_GROUPS
)) {
3356 /* Calibrate the output side */
3357 if (group_failed
== 0) {
3358 for (rank_bgn
= 0, sr
= 0; rank_bgn
3359 < RW_MGR_MEM_NUMBER_OF_RANKS
;
3361 NUM_RANKS_PER_SHADOW_REG
,
3364 if (!((STATIC_CALIB_STEPS
) &
3365 CALIB_SKIP_WRITES
)) {
3366 if ((STATIC_CALIB_STEPS
)
3367 & CALIB_SKIP_DELAY_SWEEPS
) {
3368 /* not needed in quick mode! */
3371 * Determine if this set of
3372 * ranks should be skipped
3375 if (!param
->skip_shadow_regs
[sr
]) {
3376 if (!rw_mgr_mem_calibrate_writes
3377 (rank_bgn
, write_group
,
3381 phy_debug_mode_flags
&
3382 PHY_DEBUG_SWEEP_ALL_GROUPS
)) {
3394 if (group_failed
== 0) {
3395 for (read_group
= write_group
*
3396 RW_MGR_MEM_IF_READ_DQS_WIDTH
/
3397 RW_MGR_MEM_IF_WRITE_DQS_WIDTH
,
3399 read_group
< (write_group
+ 1)
3400 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3401 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH
&&
3403 read_group
++, read_test_bgn
+=
3404 RW_MGR_MEM_DQ_PER_READ_DQS
) {
3405 if (!((STATIC_CALIB_STEPS
) &
3406 CALIB_SKIP_WRITES
)) {
3407 if (!rw_mgr_mem_calibrate_vfifo_end
3408 (read_group
, read_test_bgn
)) {
3411 if (!(gbl
->phy_debug_mode_flags
3412 & PHY_DEBUG_SWEEP_ALL_GROUPS
)) {
3420 if (group_failed
!= 0)
3425 * USER If there are any failing groups then report
3428 if (failing_groups
!= 0)
3431 /* Calibrate the LFIFO */
3432 if (!((STATIC_CALIB_STEPS
) & CALIB_SKIP_LFIFO
)) {
3434 * If we're skipping groups as part of debug,
3435 * don't calibrate LFIFO.
3437 if (param
->skip_groups
== 0) {
3438 if (!rw_mgr_mem_calibrate_lfifo())
3446 * Do not remove this line as it makes sure all of our decisions
3447 * have been applied.
3449 writel(0, &sdr_scc_mgr
->update
);
3454 * run_mem_calibrate() - Perform memory calibration
3456 * This function triggers the entire memory calibration procedure.
3458 static int run_mem_calibrate(void)
3462 debug("%s:%d\n", __func__
, __LINE__
);
3464 /* Reset pass/fail status shown on afi_cal_success/fail */
3465 writel(PHY_MGR_CAL_RESET
, &phy_mgr_cfg
->cal_status
);
3467 /* Stop tracking manager. */
3468 clrbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3470 phy_mgr_initialize();
3471 rw_mgr_mem_initialize();
3473 /* Perform the actual memory calibration. */
3474 pass
= mem_calibrate();
3476 mem_precharge_and_activate();
3477 writel(0, &phy_mgr_cmd
->fifo_reset
);
3480 rw_mgr_mem_handoff();
3482 * In Hard PHY this is a 2-bit control:
3484 * 1: DDIO Mux Select
3486 writel(0x2, &phy_mgr_cfg
->mux_sel
);
3488 /* Start tracking manager. */
3489 setbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3495 * debug_mem_calibrate() - Report result of memory calibration
3496 * @pass: Value indicating whether calibration passed or failed
3498 * This function reports the results of the memory calibration
3499 * and writes debug information into the register file.
3501 static void debug_mem_calibrate(int pass
)
3503 uint32_t debug_info
;
3506 printf("%s: CALIBRATION PASSED\n", __FILE__
);
3511 if (gbl
->fom_in
> 0xff)
3514 if (gbl
->fom_out
> 0xff)
3515 gbl
->fom_out
= 0xff;
3517 /* Update the FOM in the register file */
3518 debug_info
= gbl
->fom_in
;
3519 debug_info
|= gbl
->fom_out
<< 8;
3520 writel(debug_info
, &sdr_reg_file
->fom
);
3522 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3523 writel(PHY_MGR_CAL_SUCCESS
, &phy_mgr_cfg
->cal_status
);
3525 printf("%s: CALIBRATION FAILED\n", __FILE__
);
3527 debug_info
= gbl
->error_stage
;
3528 debug_info
|= gbl
->error_substage
<< 8;
3529 debug_info
|= gbl
->error_group
<< 16;
3531 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3532 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3533 writel(PHY_MGR_CAL_FAIL
, &phy_mgr_cfg
->cal_status
);
3535 /* Update the failing group/stage in the register file */
3536 debug_info
= gbl
->error_stage
;
3537 debug_info
|= gbl
->error_substage
<< 8;
3538 debug_info
|= gbl
->error_group
<< 16;
3539 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3542 printf("%s: Calibration complete\n", __FILE__
);
3546 * hc_initialize_rom_data() - Initialize ROM data
3548 * Initialize ROM data.
3550 static void hc_initialize_rom_data(void)
3554 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_INST_ROM_WRITE_OFFSET
;
3555 for (i
= 0; i
< ARRAY_SIZE(inst_rom_init
); i
++)
3556 writel(inst_rom_init
[i
], addr
+ (i
<< 2));
3558 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_AC_ROM_WRITE_OFFSET
;
3559 for (i
= 0; i
< ARRAY_SIZE(ac_rom_init
); i
++)
3560 writel(ac_rom_init
[i
], addr
+ (i
<< 2));
3564 * initialize_reg_file() - Initialize SDR register file
3566 * Initialize SDR register file.
3568 static void initialize_reg_file(void)
3570 /* Initialize the register file with the correct data */
3571 writel(REG_FILE_INIT_SEQ_SIGNATURE
, &sdr_reg_file
->signature
);
3572 writel(0, &sdr_reg_file
->debug_data_addr
);
3573 writel(0, &sdr_reg_file
->cur_stage
);
3574 writel(0, &sdr_reg_file
->fom
);
3575 writel(0, &sdr_reg_file
->failing_stage
);
3576 writel(0, &sdr_reg_file
->debug1
);
3577 writel(0, &sdr_reg_file
->debug2
);
3581 * initialize_hps_phy() - Initialize HPS PHY
3583 * Initialize HPS PHY.
3585 static void initialize_hps_phy(void)
3589 * Tracking also gets configured here because it's in the
3592 uint32_t trk_sample_count
= 7500;
3593 uint32_t trk_long_idle_sample_count
= (10 << 16) | 100;
3595 * Format is number of outer loops in the 16 MSB, sample
3600 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3601 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3602 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3603 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3604 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3605 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3607 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3608 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3610 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3611 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3613 writel(reg
, &sdr_ctrl
->phy_ctrl0
);
3616 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3618 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH
);
3619 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3620 trk_long_idle_sample_count
);
3621 writel(reg
, &sdr_ctrl
->phy_ctrl1
);
3624 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3625 trk_long_idle_sample_count
>>
3626 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH
);
3627 writel(reg
, &sdr_ctrl
->phy_ctrl2
);
3631 * initialize_tracking() - Initialize tracking
3633 * Initialize the register file with usable initial data.
3635 static void initialize_tracking(void)
3638 * Initialize the register file with the correct data.
3639 * Compute usable version of value in case we skip full
3640 * computation later.
3642 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP
, IO_DELAY_PER_DCHAIN_TAP
) - 1,
3643 &sdr_reg_file
->dtaps_per_ptap
);
3645 /* trk_sample_count */
3646 writel(7500, &sdr_reg_file
->trk_sample_count
);
3648 /* longidle outer loop [15:0] */
3649 writel((10 << 16) | (100 << 0), &sdr_reg_file
->trk_longidle
);
3652 * longidle sample count [31:24]
3653 * trfc, worst case of 933Mhz 4Gb [23:16]
3654 * trcd, worst case [15:8]
3657 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3658 &sdr_reg_file
->delays
);
3661 writel((RW_MGR_IDLE
<< 24) | (RW_MGR_ACTIVATE_1
<< 16) |
3662 (RW_MGR_SGLE_READ
<< 8) | (RW_MGR_PRECHARGE_ALL
<< 0),
3663 &sdr_reg_file
->trk_rw_mgr_addr
);
3665 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH
,
3666 &sdr_reg_file
->trk_read_dqs_width
);
3669 writel((RW_MGR_REFRESH_ALL
<< 24) | (1000 << 0),
3670 &sdr_reg_file
->trk_rfsh
);
3673 int sdram_calibration_full(void)
3675 struct param_type my_param
;
3676 struct gbl_type my_gbl
;
3679 memset(&my_param
, 0, sizeof(my_param
));
3680 memset(&my_gbl
, 0, sizeof(my_gbl
));
3685 /* Set the calibration enabled by default */
3686 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_ENABLE_CAL_RPT
;
3688 * Only sweep all groups (regardless of fail state) by default
3689 * Set enabled read test by default.
3691 #if DISABLE_GUARANTEED_READ
3692 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_DISABLE_GUARANTEED_READ
;
3694 /* Initialize the register file */
3695 initialize_reg_file();
3697 /* Initialize any PHY CSR */
3698 initialize_hps_phy();
3700 scc_mgr_initialize();
3702 initialize_tracking();
3704 printf("%s: Preparing to start memory calibration\n", __FILE__
);
3706 debug("%s:%d\n", __func__
, __LINE__
);
3707 debug_cond(DLEVEL
== 1,
3708 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3709 RW_MGR_MEM_NUMBER_OF_RANKS
, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM
,
3710 RW_MGR_MEM_DQ_PER_READ_DQS
, RW_MGR_MEM_DQ_PER_WRITE_DQS
,
3711 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS
,
3712 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS
);
3713 debug_cond(DLEVEL
== 1,
3714 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3715 RW_MGR_MEM_IF_READ_DQS_WIDTH
, RW_MGR_MEM_IF_WRITE_DQS_WIDTH
,
3716 RW_MGR_MEM_DATA_WIDTH
, RW_MGR_MEM_DATA_MASK_WIDTH
,
3717 IO_DELAY_PER_OPA_TAP
, IO_DELAY_PER_DCHAIN_TAP
);
3718 debug_cond(DLEVEL
== 1, "dtap_dqsen_delay=%u, dll=%u",
3719 IO_DELAY_PER_DQS_EN_DCHAIN_TAP
, IO_DLL_CHAIN_LENGTH
);
3720 debug_cond(DLEVEL
== 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3721 IO_DQS_EN_PHASE_MAX
, IO_DQDQS_OUT_PHASE_MAX
,
3722 IO_DQS_EN_DELAY_MAX
, IO_DQS_IN_DELAY_MAX
);
3723 debug_cond(DLEVEL
== 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3724 IO_IO_IN_DELAY_MAX
, IO_IO_OUT1_DELAY_MAX
,
3725 IO_IO_OUT2_DELAY_MAX
);
3726 debug_cond(DLEVEL
== 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3727 IO_DQS_IN_RESERVE
, IO_DQS_OUT_RESERVE
);
3729 hc_initialize_rom_data();
3731 /* update info for sims */
3732 reg_file_set_stage(CAL_STAGE_NIL
);
3733 reg_file_set_group(0);
3736 * Load global needed for those actions that require
3737 * some dynamic calibration support.
3739 dyn_calib_steps
= STATIC_CALIB_STEPS
;
3741 * Load global to allow dynamic selection of delay loop settings
3742 * based on calibration mode.
3744 if (!(dyn_calib_steps
& CALIB_SKIP_DELAY_LOOPS
))
3745 skip_delay_mask
= 0xff;
3747 skip_delay_mask
= 0x0;
3749 pass
= run_mem_calibrate();
3750 debug_mem_calibrate(pass
);