2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
11 #include <fsl_ddr_sdram.h>
12 #include <asm/processor.h>
13 #include <fsl_immap.h>
15 #include <asm/arch/clock.h>
17 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
18 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
23 * regs has the to-be-set values for DDR controller registers
24 * ctrl_num is the DDR controller number
25 * step: 0 goes through the initialization in one pass
26 * 1 sets registers and returns before enabling controller
27 * 2 resumes from step 1 and continues to initialize
28 * Dividing the initialization to two steps to deassert DDR reset signal
29 * to comply with JEDEC specs for RDIMMs.
31 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs
,
32 unsigned int ctrl_num
, int step
)
34 unsigned int i
, bus_width
;
35 struct ccsr_ddr __iomem
*ddr
;
37 u32 total_gb_size_per_controller
;
42 ddr
= (void *)CONFIG_SYS_FSL_DDR_ADDR
;
44 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
46 ddr
= (void *)CONFIG_SYS_FSL_DDR2_ADDR
;
49 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
51 ddr
= (void *)CONFIG_SYS_FSL_DDR3_ADDR
;
54 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
56 ddr
= (void *)CONFIG_SYS_FSL_DDR4_ADDR
;
60 printf("%s unexpected ctrl_num = %u\n", __func__
, ctrl_num
);
68 ddr_out32(&ddr
->eor
, regs
->ddr_eor
);
69 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
71 ddr_out32(&ddr
->cs0_bnds
, regs
->cs
[i
].bnds
);
72 ddr_out32(&ddr
->cs0_config
, regs
->cs
[i
].config
);
73 ddr_out32(&ddr
->cs0_config_2
, regs
->cs
[i
].config_2
);
76 ddr_out32(&ddr
->cs1_bnds
, regs
->cs
[i
].bnds
);
77 ddr_out32(&ddr
->cs1_config
, regs
->cs
[i
].config
);
78 ddr_out32(&ddr
->cs1_config_2
, regs
->cs
[i
].config_2
);
81 ddr_out32(&ddr
->cs2_bnds
, regs
->cs
[i
].bnds
);
82 ddr_out32(&ddr
->cs2_config
, regs
->cs
[i
].config
);
83 ddr_out32(&ddr
->cs2_config_2
, regs
->cs
[i
].config_2
);
86 ddr_out32(&ddr
->cs3_bnds
, regs
->cs
[i
].bnds
);
87 ddr_out32(&ddr
->cs3_config
, regs
->cs
[i
].config
);
88 ddr_out32(&ddr
->cs3_config_2
, regs
->cs
[i
].config_2
);
92 ddr_out32(&ddr
->timing_cfg_3
, regs
->timing_cfg_3
);
93 ddr_out32(&ddr
->timing_cfg_0
, regs
->timing_cfg_0
);
94 ddr_out32(&ddr
->timing_cfg_1
, regs
->timing_cfg_1
);
95 ddr_out32(&ddr
->timing_cfg_2
, regs
->timing_cfg_2
);
96 ddr_out32(&ddr
->sdram_mode
, regs
->ddr_sdram_mode
);
97 ddr_out32(&ddr
->sdram_mode_2
, regs
->ddr_sdram_mode_2
);
98 ddr_out32(&ddr
->sdram_mode_3
, regs
->ddr_sdram_mode_3
);
99 ddr_out32(&ddr
->sdram_mode_4
, regs
->ddr_sdram_mode_4
);
100 ddr_out32(&ddr
->sdram_mode_5
, regs
->ddr_sdram_mode_5
);
101 ddr_out32(&ddr
->sdram_mode_6
, regs
->ddr_sdram_mode_6
);
102 ddr_out32(&ddr
->sdram_mode_7
, regs
->ddr_sdram_mode_7
);
103 ddr_out32(&ddr
->sdram_mode_8
, regs
->ddr_sdram_mode_8
);
104 ddr_out32(&ddr
->sdram_md_cntl
, regs
->ddr_sdram_md_cntl
);
105 ddr_out32(&ddr
->sdram_interval
, regs
->ddr_sdram_interval
);
106 ddr_out32(&ddr
->sdram_data_init
, regs
->ddr_data_init
);
107 ddr_out32(&ddr
->sdram_clk_cntl
, regs
->ddr_sdram_clk_cntl
);
108 ddr_out32(&ddr
->timing_cfg_4
, regs
->timing_cfg_4
);
109 ddr_out32(&ddr
->timing_cfg_5
, regs
->timing_cfg_5
);
110 ddr_out32(&ddr
->ddr_zq_cntl
, regs
->ddr_zq_cntl
);
111 ddr_out32(&ddr
->ddr_wrlvl_cntl
, regs
->ddr_wrlvl_cntl
);
112 #ifndef CONFIG_SYS_FSL_DDR_EMU
114 * Skip these two registers if running on emulator
115 * because emulator doesn't have skew between bytes.
118 if (regs
->ddr_wrlvl_cntl_2
)
119 ddr_out32(&ddr
->ddr_wrlvl_cntl_2
, regs
->ddr_wrlvl_cntl_2
);
120 if (regs
->ddr_wrlvl_cntl_3
)
121 ddr_out32(&ddr
->ddr_wrlvl_cntl_3
, regs
->ddr_wrlvl_cntl_3
);
124 ddr_out32(&ddr
->ddr_sr_cntr
, regs
->ddr_sr_cntr
);
125 ddr_out32(&ddr
->ddr_sdram_rcw_1
, regs
->ddr_sdram_rcw_1
);
126 ddr_out32(&ddr
->ddr_sdram_rcw_2
, regs
->ddr_sdram_rcw_2
);
127 ddr_out32(&ddr
->ddr_cdr1
, regs
->ddr_cdr1
);
128 #ifdef CONFIG_DEEP_SLEEP
129 if (is_warm_boot()) {
130 ddr_out32(&ddr
->sdram_cfg_2
,
131 regs
->ddr_sdram_cfg_2
& ~SDRAM_CFG2_D_INIT
);
132 ddr_out32(&ddr
->init_addr
, CONFIG_SYS_SDRAM_BASE
);
133 ddr_out32(&ddr
->init_ext_addr
, DDR_INIT_ADDR_EXT_UIA
);
135 /* DRAM VRef will not be trained */
136 ddr_out32(&ddr
->ddr_cdr2
,
137 regs
->ddr_cdr2
& ~DDR_CDR2_VREF_TRAIN_EN
);
141 ddr_out32(&ddr
->sdram_cfg_2
, regs
->ddr_sdram_cfg_2
);
142 ddr_out32(&ddr
->init_addr
, regs
->ddr_init_addr
);
143 ddr_out32(&ddr
->init_ext_addr
, regs
->ddr_init_ext_addr
);
144 ddr_out32(&ddr
->ddr_cdr2
, regs
->ddr_cdr2
);
146 ddr_out32(&ddr
->err_disable
, regs
->err_disable
);
147 ddr_out32(&ddr
->err_int_en
, regs
->err_int_en
);
148 for (i
= 0; i
< 32; i
++) {
149 if (regs
->debug
[i
]) {
150 debug("Write to debug_%d as %08x\n", i
+ 1,
152 ddr_out32(&ddr
->debug
[i
], regs
->debug
[i
]);
157 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
158 * deasserted. Clocks start when any chip select is enabled and clock
159 * control register is set. Because all DDR components are connected to
160 * one reset signal, this needs to be done in two steps. Step 1 is to
161 * get the clocks started. Step 2 resumes after reset signal is
170 /* Set, but do not enable the memory */
171 temp_sdram_cfg
= regs
->ddr_sdram_cfg
;
172 temp_sdram_cfg
&= ~(SDRAM_CFG_MEM_EN
);
173 ddr_out32(&ddr
->sdram_cfg
, temp_sdram_cfg
);
176 * 500 painful micro-seconds must elapse between
177 * the DDR clock setup and the DDR config enable.
178 * DDR2 need 200 us, and DDR3 need 500 us from spec,
179 * we choose the max, that is 500 us for all of case.
182 asm volatile("dsb sy;isb");
184 #ifdef CONFIG_DEEP_SLEEP
185 if (is_warm_boot()) {
186 /* enter self-refresh */
187 temp_sdram_cfg
= ddr_in32(&ddr
->sdram_cfg_2
);
188 temp_sdram_cfg
|= SDRAM_CFG2_FRC_SR
;
189 ddr_out32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);
190 /* do board specific memory setup */
191 board_mem_sleep_setup();
193 temp_sdram_cfg
= (ddr_in32(&ddr
->sdram_cfg
) | SDRAM_CFG_BI
);
196 temp_sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
) & ~SDRAM_CFG_BI
;
197 /* Let the controller go */
198 ddr_out32(&ddr
->sdram_cfg
, temp_sdram_cfg
| SDRAM_CFG_MEM_EN
);
199 asm volatile("dsb sy;isb");
201 total_gb_size_per_controller
= 0;
202 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
203 if (!(regs
->cs
[i
].config
& 0x80000000))
205 total_gb_size_per_controller
+= 1 << (
206 ((regs
->cs
[i
].config
>> 14) & 0x3) + 2 +
207 ((regs
->cs
[i
].config
>> 8) & 0x7) + 12 +
208 ((regs
->cs
[i
].config
>> 0) & 0x7) + 8 +
209 3 - ((regs
->ddr_sdram_cfg
>> 19) & 0x3) -
210 26); /* minus 26 (count of 64M) */
212 if (regs
->cs
[0].config
& 0x20000000) {
213 /* 2-way interleaving */
214 total_gb_size_per_controller
<<= 1;
217 * total memory / bus width = transactions needed
218 * transactions needed / data rate = seconds
219 * to add plenty of buffer, double the time
220 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
221 * Let's wait for 800ms
223 bus_width
= 3 - ((ddr_in32(&ddr
->sdram_cfg
) & SDRAM_CFG_DBW_MASK
)
224 >> SDRAM_CFG_DBW_SHIFT
);
225 timeout
= ((total_gb_size_per_controller
<< (6 - bus_width
)) * 100 /
226 (get_ddr_freq(ctrl_num
) >> 20)) << 1;
227 total_gb_size_per_controller
>>= 4; /* shift down to gb size */
228 debug("total %d GB\n", total_gb_size_per_controller
);
229 debug("Need to wait up to %d * 10ms\n", timeout
);
231 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
232 while ((ddr_in32(&ddr
->sdram_cfg_2
) & SDRAM_CFG2_D_INIT
) &&
234 udelay(10000); /* throttle polling rate */
239 printf("Waiting for D_INIT timeout. Memory may not work.\n");
240 #ifdef CONFIG_DEEP_SLEEP
241 if (is_warm_boot()) {
242 /* exit self-refresh */
243 temp_sdram_cfg
= ddr_in32(&ddr
->sdram_cfg_2
);
244 temp_sdram_cfg
&= ~SDRAM_CFG2_FRC_SR
;
245 ddr_out32(&ddr
->sdram_cfg_2
, temp_sdram_cfg
);