2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
15 #include <fsl_ddr_sdram.h>
19 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
20 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
21 * all Power SoCs. But it could be different for ARM SoCs. For example,
22 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
23 * 0x00_8000_0000 ~ 0x00_ffff_ffff
24 * 0x80_8000_0000 ~ 0xff_ffff_ffff
26 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
31 #include <asm/fsl_law.h>
33 void fsl_ddr_set_lawbar(
34 const common_timing_params_t
*memctl_common_params
,
35 unsigned int memctl_interleaved
,
36 unsigned int ctrl_num
);
39 void fsl_ddr_set_intl3r(const unsigned int granule_size
);
40 #if defined(SPD_EEPROM_ADDRESS) || \
41 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
42 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
43 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
44 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
45 [0][0] = SPD_EEPROM_ADDRESS
,
47 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
48 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
49 [0][0] = SPD_EEPROM_ADDRESS1
, /* controller 1 */
50 [0][1] = SPD_EEPROM_ADDRESS2
, /* controller 1 */
52 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
53 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
54 [0][0] = SPD_EEPROM_ADDRESS1
, /* controller 1 */
55 [1][0] = SPD_EEPROM_ADDRESS2
, /* controller 2 */
57 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
58 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
59 [0][0] = SPD_EEPROM_ADDRESS1
, /* controller 1 */
60 [0][1] = SPD_EEPROM_ADDRESS2
, /* controller 1 */
61 [1][0] = SPD_EEPROM_ADDRESS3
, /* controller 2 */
62 [1][1] = SPD_EEPROM_ADDRESS4
, /* controller 2 */
64 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
65 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
66 [0][0] = SPD_EEPROM_ADDRESS1
, /* controller 1 */
67 [1][0] = SPD_EEPROM_ADDRESS2
, /* controller 2 */
68 [2][0] = SPD_EEPROM_ADDRESS3
, /* controller 3 */
70 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
71 u8 spd_i2c_addr
[CONFIG_SYS_NUM_DDR_CTLRS
][CONFIG_DIMM_SLOTS_PER_CTLR
] = {
72 [0][0] = SPD_EEPROM_ADDRESS1
, /* controller 1 */
73 [0][1] = SPD_EEPROM_ADDRESS2
, /* controller 1 */
74 [1][0] = SPD_EEPROM_ADDRESS3
, /* controller 2 */
75 [1][1] = SPD_EEPROM_ADDRESS4
, /* controller 2 */
76 [2][0] = SPD_EEPROM_ADDRESS5
, /* controller 3 */
77 [2][1] = SPD_EEPROM_ADDRESS6
, /* controller 3 */
82 #define SPD_SPA0_ADDRESS 0x36
83 #define SPD_SPA1_ADDRESS 0x37
85 static void __get_spd(generic_spd_eeprom_t
*spd
, u8 i2c_address
)
88 #ifdef CONFIG_SYS_FSL_DDR4
92 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM
);
94 #ifdef CONFIG_SYS_FSL_DDR4
96 * DDR4 SPD has 384 to 512 bytes
97 * To access the lower 256 bytes, we need to set EE page address to 0
98 * To access the upper 256 bytes, we need to set EE page address to 1
99 * See Jedec standar No. 21-C for detail
101 i2c_write(SPD_SPA0_ADDRESS
, 0, 1, &dummy
, 1);
102 ret
= i2c_read(i2c_address
, 0, 1, (uchar
*)spd
, 256);
104 i2c_write(SPD_SPA1_ADDRESS
, 0, 1, &dummy
, 1);
105 ret
= i2c_read(i2c_address
, 0, 1,
106 (uchar
*)((ulong
)spd
+ 256),
108 (int)sizeof(generic_spd_eeprom_t
) - 256));
111 ret
= i2c_read(i2c_address
, 0, 1, (uchar
*)spd
,
112 sizeof(generic_spd_eeprom_t
));
117 #ifdef SPD_EEPROM_ADDRESS
119 #elif defined(SPD_EEPROM_ADDRESS1)
123 printf("DDR: failed to read SPD from address %u\n",
126 debug("DDR: failed to read SPD from address %u\n",
129 memset(spd
, 0, sizeof(generic_spd_eeprom_t
));
133 __attribute__((weak
, alias("__get_spd")))
134 void get_spd(generic_spd_eeprom_t
*spd
, u8 i2c_address
);
136 /* This function allows boards to update SPD address */
137 __weak
void update_spd_address(unsigned int ctrl_num
,
143 void fsl_ddr_get_spd(generic_spd_eeprom_t
*ctrl_dimms_spd
,
144 unsigned int ctrl_num
, unsigned int dimm_slots_per_ctrl
)
147 unsigned int i2c_address
= 0;
149 if (ctrl_num
>= CONFIG_SYS_NUM_DDR_CTLRS
) {
150 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__
, ctrl_num
);
154 for (i
= 0; i
< dimm_slots_per_ctrl
; i
++) {
155 i2c_address
= spd_i2c_addr
[ctrl_num
][i
];
156 update_spd_address(ctrl_num
, i
, &i2c_address
);
157 get_spd(&(ctrl_dimms_spd
[i
]), i2c_address
);
161 void fsl_ddr_get_spd(generic_spd_eeprom_t
*ctrl_dimms_spd
,
162 unsigned int ctrl_num
, unsigned int dimm_slots_per_ctrl
)
165 #endif /* SPD_EEPROM_ADDRESSx */
169 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
170 * - Same memory data bus width on all controllers
174 * The memory controller and associated documentation use confusing
175 * terminology when referring to the orgranization of DRAM.
177 * Here is a terminology translation table:
179 * memory controller/documention |industry |this code |signals
180 * -------------------------------|-----------|-----------|-----------------
181 * physical bank/bank |rank |rank |chip select (CS)
182 * logical bank/sub-bank |bank |bank |bank address (BA)
183 * page/row |row |page |row address
184 * ??? |column |column |column address
186 * The naming confusion is further exacerbated by the descriptions of the
187 * memory controller interleaving feature, where accesses are interleaved
188 * _BETWEEN_ two seperate memory controllers. This is configured only in
189 * CS0_CONFIG[INTLV_CTL] of each memory controller.
191 * memory controller documentation | number of chip selects
192 * | per memory controller supported
193 * --------------------------------|-----------------------------------------
194 * cache line interleaving | 1 (CS0 only)
195 * page interleaving | 1 (CS0 only)
196 * bank interleaving | 1 (CS0 only)
197 * superbank interleraving | depends on bank (chip select)
198 * | interleraving [rank interleaving]
199 * | mode used on every memory controller
201 * Even further confusing is the existence of the interleaving feature
202 * _WITHIN_ each memory controller. The feature is referred to in
203 * documentation as chip select interleaving or bank interleaving,
204 * although it is configured in the DDR_SDRAM_CFG field.
206 * Name of field | documentation name | this code
207 * -----------------------------|-----------------------|------------------
208 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
212 const char *step_string_tbl
[] = {
214 "STEP_COMPUTE_DIMM_PARMS",
215 "STEP_COMPUTE_COMMON_PARMS",
217 "STEP_ASSIGN_ADDRESSES",
223 const char * step_to_string(unsigned int step
) {
225 unsigned int s
= __ilog2(step
);
227 if ((1 << s
) != step
)
228 return step_string_tbl
[7];
230 if (s
>= ARRAY_SIZE(step_string_tbl
)) {
231 printf("Error for the step in %s\n", __func__
);
235 return step_string_tbl
[s
];
238 static unsigned long long __step_assign_addresses(fsl_ddr_info_t
*pinfo
,
239 unsigned int dbw_cap_adj
[])
242 unsigned long long total_mem
, current_mem_base
, total_ctlr_mem
;
243 unsigned long long rank_density
, ctlr_density
= 0;
244 unsigned int first_ctrl
= pinfo
->first_ctrl
;
245 unsigned int last_ctrl
= first_ctrl
+ pinfo
->num_ctrls
- 1;
248 * If a reduced data width is requested, but the SPD
249 * specifies a physically wider device, adjust the
250 * computed dimm capacities accordingly before
251 * assigning addresses.
253 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
254 unsigned int found
= 0;
256 switch (pinfo
->memctl_opts
[i
].data_bus_width
) {
259 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
261 if (!pinfo
->dimm_params
[i
][j
].n_ranks
)
263 dw
= pinfo
->dimm_params
[i
][j
].primary_sdram_width
;
264 if ((dw
== 72 || dw
== 64)) {
267 } else if ((dw
== 40 || dw
== 32)) {
276 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
278 dw
= pinfo
->dimm_params
[i
][j
].data_width
;
279 if (pinfo
->dimm_params
[i
][j
].n_ranks
280 && (dw
== 72 || dw
== 64)) {
282 * FIXME: can't really do it
283 * like this because this just
284 * further reduces the memory
300 printf("unexpected data bus width "
301 "specified controller %u\n", i
);
304 debug("dbw_cap_adj[%d]=%d\n", i
, dbw_cap_adj
[i
]);
307 current_mem_base
= pinfo
->mem_base
;
309 if (pinfo
->memctl_opts
[first_ctrl
].memctl_interleaving
) {
310 rank_density
= pinfo
->dimm_params
[first_ctrl
][0].rank_density
>>
311 dbw_cap_adj
[first_ctrl
];
312 switch (pinfo
->memctl_opts
[first_ctrl
].ba_intlv_ctl
&
313 FSL_DDR_CS0_CS1_CS2_CS3
) {
314 case FSL_DDR_CS0_CS1_CS2_CS3
:
315 ctlr_density
= 4 * rank_density
;
317 case FSL_DDR_CS0_CS1
:
318 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
319 ctlr_density
= 2 * rank_density
;
321 case FSL_DDR_CS2_CS3
:
323 ctlr_density
= rank_density
;
326 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
327 rank_density
, ctlr_density
);
328 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
329 if (pinfo
->memctl_opts
[i
].memctl_interleaving
) {
330 switch (pinfo
->memctl_opts
[i
].memctl_interleaving_mode
) {
331 case FSL_DDR_256B_INTERLEAVING
:
332 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
333 case FSL_DDR_PAGE_INTERLEAVING
:
334 case FSL_DDR_BANK_INTERLEAVING
:
335 case FSL_DDR_SUPERBANK_INTERLEAVING
:
336 total_ctlr_mem
= 2 * ctlr_density
;
338 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
339 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
340 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
341 total_ctlr_mem
= 3 * ctlr_density
;
343 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
344 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
345 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
346 total_ctlr_mem
= 4 * ctlr_density
;
349 panic("Unknown interleaving mode");
351 pinfo
->common_timing_params
[i
].base_address
=
353 pinfo
->common_timing_params
[i
].total_mem
=
355 total_mem
= current_mem_base
+ total_ctlr_mem
;
356 debug("ctrl %d base 0x%llx\n", i
, current_mem_base
);
357 debug("ctrl %d total 0x%llx\n", i
, total_ctlr_mem
);
359 /* when 3rd controller not interleaved */
360 current_mem_base
= total_mem
;
362 pinfo
->common_timing_params
[i
].base_address
=
364 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
365 unsigned long long cap
=
366 pinfo
->dimm_params
[i
][j
].capacity
>> dbw_cap_adj
[i
];
367 pinfo
->dimm_params
[i
][j
].base_address
=
369 debug("ctrl %d dimm %d base 0x%llx\n", i
, j
, current_mem_base
);
370 current_mem_base
+= cap
;
371 total_ctlr_mem
+= cap
;
373 debug("ctrl %d total 0x%llx\n", i
, total_ctlr_mem
);
374 pinfo
->common_timing_params
[i
].total_mem
=
376 total_mem
+= total_ctlr_mem
;
381 * Simple linear assignment if memory
382 * controllers are not interleaved.
384 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
386 pinfo
->common_timing_params
[i
].base_address
=
388 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
389 /* Compute DIMM base addresses. */
390 unsigned long long cap
=
391 pinfo
->dimm_params
[i
][j
].capacity
>> dbw_cap_adj
[i
];
392 pinfo
->dimm_params
[i
][j
].base_address
=
394 debug("ctrl %d dimm %d base 0x%llx\n", i
, j
, current_mem_base
);
395 current_mem_base
+= cap
;
396 total_ctlr_mem
+= cap
;
398 debug("ctrl %d total 0x%llx\n", i
, total_ctlr_mem
);
399 pinfo
->common_timing_params
[i
].total_mem
=
401 total_mem
+= total_ctlr_mem
;
404 debug("Total mem by %s is 0x%llx\n", __func__
, total_mem
);
409 /* Use weak function to allow board file to override the address assignment */
410 __attribute__((weak
, alias("__step_assign_addresses")))
411 unsigned long long step_assign_addresses(fsl_ddr_info_t
*pinfo
,
412 unsigned int dbw_cap_adj
[]);
415 fsl_ddr_compute(fsl_ddr_info_t
*pinfo
, unsigned int start_step
,
416 unsigned int size_only
)
419 unsigned long long total_mem
= 0;
420 int assert_reset
= 0;
421 unsigned int first_ctrl
= pinfo
->first_ctrl
;
422 unsigned int last_ctrl
= first_ctrl
+ pinfo
->num_ctrls
- 1;
423 __maybe_unused
int retval
;
424 __maybe_unused
bool goodspd
= false;
425 __maybe_unused
int dimm_slots_per_ctrl
= pinfo
->dimm_slots_per_ctrl
;
427 fsl_ddr_cfg_regs_t
*ddr_reg
= pinfo
->fsl_ddr_config_reg
;
428 common_timing_params_t
*timing_params
= pinfo
->common_timing_params
;
429 if (pinfo
->board_need_mem_reset
)
430 assert_reset
= pinfo
->board_need_mem_reset();
432 /* data bus width capacity adjust shift amount */
433 unsigned int dbw_capacity_adjust
[CONFIG_SYS_NUM_DDR_CTLRS
];
435 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
436 dbw_capacity_adjust
[i
] = 0;
438 debug("starting at step %u (%s)\n",
439 start_step
, step_to_string(start_step
));
441 switch (start_step
) {
443 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
444 /* STEP 1: Gather all DIMM SPD data */
445 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
446 fsl_ddr_get_spd(pinfo
->spd_installed_dimms
[i
], i
,
447 dimm_slots_per_ctrl
);
450 case STEP_COMPUTE_DIMM_PARMS
:
451 /* STEP 2: Compute DIMM parameters from SPD data */
453 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
454 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
455 generic_spd_eeprom_t
*spd
=
456 &(pinfo
->spd_installed_dimms
[i
][j
]);
457 dimm_params_t
*pdimm
=
458 &(pinfo
->dimm_params
[i
][j
]);
459 retval
= compute_dimm_parameters(
461 #ifdef CONFIG_SYS_DDR_RAW_TIMING
463 printf("SPD error on controller %d! "
464 "Trying fallback to raw timing "
466 retval
= fsl_ddr_get_dimm_params(pdimm
,
471 printf("Error: compute_dimm_parameters"
472 " non-zero returned FATAL value "
473 "for memctl=%u dimm=%u\n", i
, j
);
478 debug("Warning: compute_dimm_parameters"
479 " non-zero return value for memctl=%u "
489 * Throw an error if this is for main memory, i.e.
490 * first_ctrl == 0. Otherwise, siliently return 0
491 * as the memory size.
494 printf("Error: No valid SPD detected.\n");
498 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
499 case STEP_COMPUTE_DIMM_PARMS
:
500 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
501 for (j
= 0; j
< CONFIG_DIMM_SLOTS_PER_CTLR
; j
++) {
502 dimm_params_t
*pdimm
=
503 &(pinfo
->dimm_params
[i
][j
]);
504 fsl_ddr_get_dimm_params(pdimm
, i
, j
);
507 debug("Filling dimm parameters from board specific file\n");
509 case STEP_COMPUTE_COMMON_PARMS
:
511 * STEP 3: Compute a common set of timing parameters
512 * suitable for all of the DIMMs on each memory controller
514 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
515 debug("Computing lowest common DIMM"
516 " parameters for memctl=%u\n", i
);
517 compute_lowest_common_dimm_parameters
519 pinfo
->dimm_params
[i
],
521 CONFIG_DIMM_SLOTS_PER_CTLR
);
524 case STEP_GATHER_OPTS
:
525 /* STEP 4: Gather configuration requirements from user */
526 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
527 debug("Reloading memory controller "
528 "configuration options for memctl=%u\n", i
);
530 * This "reloads" the memory controller options
531 * to defaults. If the user "edits" an option,
532 * next_step points to the step after this,
533 * which is currently STEP_ASSIGN_ADDRESSES.
535 populate_memctl_options(
537 &pinfo
->memctl_opts
[i
],
538 pinfo
->dimm_params
[i
], i
);
540 * For RDIMMs, JEDEC spec requires clocks to be stable
541 * before reset signal is deasserted. For the boards
542 * using fixed parameters, this function should be
543 * be called from board init file.
545 if (timing_params
[i
].all_dimms_registered
)
548 if (assert_reset
&& !size_only
) {
549 if (pinfo
->board_mem_reset
) {
550 debug("Asserting mem reset\n");
551 pinfo
->board_mem_reset();
553 debug("Asserting mem reset missing\n");
557 case STEP_ASSIGN_ADDRESSES
:
558 /* STEP 5: Assign addresses to chip selects */
559 check_interleaving_options(pinfo
);
560 total_mem
= step_assign_addresses(pinfo
, dbw_capacity_adjust
);
561 debug("Total mem %llu assigned\n", total_mem
);
563 case STEP_COMPUTE_REGS
:
564 /* STEP 6: compute controller register values */
565 debug("FSL Memory ctrl register computation\n");
566 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
567 if (timing_params
[i
].ndimms_present
== 0) {
568 memset(&ddr_reg
[i
], 0,
569 sizeof(fsl_ddr_cfg_regs_t
));
573 compute_fsl_memctl_config_regs
575 &pinfo
->memctl_opts
[i
],
576 &ddr_reg
[i
], &timing_params
[i
],
577 pinfo
->dimm_params
[i
],
578 dbw_capacity_adjust
[i
],
588 * Compute the amount of memory available just by
589 * looking for the highest valid CSn_BNDS value.
590 * This allows us to also experiment with using
591 * only CS0 when using dual-rank DIMMs.
593 unsigned int max_end
= 0;
595 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
596 for (j
= 0; j
< CONFIG_CHIP_SELECTS_PER_CTRL
; j
++) {
597 fsl_ddr_cfg_regs_t
*reg
= &ddr_reg
[i
];
598 if (reg
->cs
[j
].config
& 0x80000000) {
601 * 0xfffffff is a special value we put
604 if (reg
->cs
[j
].bnds
== 0xffffffff)
606 end
= reg
->cs
[j
].bnds
& 0xffff;
614 total_mem
= 1 + (((unsigned long long)max_end
<< 24ULL) |
615 0xFFFFFFULL
) - pinfo
->mem_base
;
621 phys_size_t
__fsl_ddr_sdram(fsl_ddr_info_t
*pinfo
)
623 unsigned int i
, first_ctrl
, last_ctrl
;
625 unsigned int law_memctl
= LAW_TRGT_IF_DDR_1
;
627 unsigned long long total_memory
;
628 int deassert_reset
= 0;
630 first_ctrl
= pinfo
->first_ctrl
;
631 last_ctrl
= first_ctrl
+ pinfo
->num_ctrls
- 1;
633 /* Compute it once normally. */
634 #ifdef CONFIG_FSL_DDR_INTERACTIVE
635 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
636 total_memory
= fsl_ddr_interactive(pinfo
, 0);
637 } else if (fsl_ddr_interactive_env_var_exists()) {
638 total_memory
= fsl_ddr_interactive(pinfo
, 1);
641 total_memory
= fsl_ddr_compute(pinfo
, STEP_GET_SPD
, 0);
643 /* setup 3-way interleaving before enabling DDRC */
644 switch (pinfo
->memctl_opts
[first_ctrl
].memctl_interleaving_mode
) {
645 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
646 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
647 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
649 pinfo
->memctl_opts
[first_ctrl
].
650 memctl_interleaving_mode
);
657 * Program configuration registers.
658 * JEDEC specs requires clocks to be stable before deasserting reset
659 * for RDIMMs. Clocks start after chip select is enabled and clock
660 * control register is set. During step 1, all controllers have their
661 * registers set but not enabled. Step 2 proceeds after deasserting
662 * reset through board FPGA or GPIO.
663 * For non-registered DIMMs, initialization can go through but it is
664 * also OK to follow the same flow.
666 if (pinfo
->board_need_mem_reset
)
667 deassert_reset
= pinfo
->board_need_mem_reset();
668 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
669 if (pinfo
->common_timing_params
[i
].all_dimms_registered
)
672 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
673 debug("Programming controller %u\n", i
);
674 if (pinfo
->common_timing_params
[i
].ndimms_present
== 0) {
675 debug("No dimms present on controller %u; "
676 "skipping programming\n", i
);
680 * The following call with step = 1 returns before enabling
681 * the controller. It has to finish with step = 2 later.
683 fsl_ddr_set_memctl_regs(&(pinfo
->fsl_ddr_config_reg
[i
]), i
,
684 deassert_reset
? 1 : 0);
686 if (deassert_reset
) {
687 /* Use board FPGA or GPIO to deassert reset signal */
688 if (pinfo
->board_mem_de_reset
) {
689 debug("Deasserting mem reset\n");
690 pinfo
->board_mem_de_reset();
692 debug("Deasserting mem reset missing\n");
694 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
695 /* Call with step = 2 to continue initialization */
696 fsl_ddr_set_memctl_regs(&(pinfo
->fsl_ddr_config_reg
[i
]),
701 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
702 fsl_ddr_sync_memctl_refresh(first_ctrl
, last_ctrl
);
707 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
708 if (pinfo
->memctl_opts
[i
].memctl_interleaving
) {
709 switch (pinfo
->memctl_opts
[i
].
710 memctl_interleaving_mode
) {
711 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
712 case FSL_DDR_PAGE_INTERLEAVING
:
713 case FSL_DDR_BANK_INTERLEAVING
:
714 case FSL_DDR_SUPERBANK_INTERLEAVING
:
718 law_memctl
= LAW_TRGT_IF_DDR_INTRLV
;
720 &pinfo
->common_timing_params
[i
],
723 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
725 law_memctl
= LAW_TRGT_IF_DDR_INTLV_34
;
727 &pinfo
->common_timing_params
[i
],
732 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
733 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
734 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
735 law_memctl
= LAW_TRGT_IF_DDR_INTLV_123
;
738 &pinfo
->common_timing_params
[i
],
742 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
743 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
744 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
745 law_memctl
= LAW_TRGT_IF_DDR_INTLV_1234
;
748 &pinfo
->common_timing_params
[i
],
750 /* place holder for future 4-way interleaving */
758 law_memctl
= LAW_TRGT_IF_DDR_1
;
761 law_memctl
= LAW_TRGT_IF_DDR_2
;
764 law_memctl
= LAW_TRGT_IF_DDR_3
;
767 law_memctl
= LAW_TRGT_IF_DDR_4
;
772 fsl_ddr_set_lawbar(&pinfo
->common_timing_params
[i
],
778 debug("total_memory by %s = %llu\n", __func__
, total_memory
);
780 #if !defined(CONFIG_PHYS_64BIT)
781 /* Check for 4G or more. Bad. */
782 if ((first_ctrl
== 0) && (total_memory
>= (1ull << 32))) {
784 print_size(total_memory
, " of memory\n");
785 printf(" This U-Boot only supports < 4G of DDR\n");
786 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
787 printf(" "); /* re-align to match init_func_ram print */
788 total_memory
= CONFIG_MAX_MEM_MAPPED
;
796 * fsl_ddr_sdram(void) -- this is the main function to be
797 * called by initdram() in the board file.
799 * It returns amount of memory configured in bytes.
801 phys_size_t
fsl_ddr_sdram(void)
805 /* Reset info structure. */
806 memset(&info
, 0, sizeof(fsl_ddr_info_t
));
807 info
.mem_base
= CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
;
809 info
.num_ctrls
= CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
;
810 info
.dimm_slots_per_ctrl
= CONFIG_DIMM_SLOTS_PER_CTLR
;
811 info
.board_need_mem_reset
= board_need_mem_reset
;
812 info
.board_mem_reset
= board_assert_mem_reset
;
813 info
.board_mem_de_reset
= board_deassert_mem_reset
;
814 remove_unused_controllers(&info
);
816 return __fsl_ddr_sdram(&info
);
819 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
820 phys_size_t
fsl_other_ddr_sdram(unsigned long long base
,
821 unsigned int first_ctrl
,
822 unsigned int num_ctrls
,
823 unsigned int dimm_slots_per_ctrl
,
824 int (*board_need_reset
)(void),
825 void (*board_reset
)(void),
826 void (*board_de_reset
)(void))
830 /* Reset info structure. */
831 memset(&info
, 0, sizeof(fsl_ddr_info_t
));
832 info
.mem_base
= base
;
833 info
.first_ctrl
= first_ctrl
;
834 info
.num_ctrls
= num_ctrls
;
835 info
.dimm_slots_per_ctrl
= dimm_slots_per_ctrl
;
836 info
.board_need_mem_reset
= board_need_reset
;
837 info
.board_mem_reset
= board_reset
;
838 info
.board_mem_de_reset
= board_de_reset
;
840 return __fsl_ddr_sdram(&info
);
845 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
846 * size of the total memory without setting ddr control registers.
849 fsl_ddr_sdram_size(void)
852 unsigned long long total_memory
= 0;
854 memset(&info
, 0 , sizeof(fsl_ddr_info_t
));
855 info
.mem_base
= CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
;
857 info
.num_ctrls
= CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
;
858 info
.dimm_slots_per_ctrl
= CONFIG_DIMM_SLOTS_PER_CTLR
;
859 info
.board_need_mem_reset
= NULL
;
860 remove_unused_controllers(&info
);
862 /* Compute it once normally. */
863 total_memory
= fsl_ddr_compute(&info
, STEP_GET_SPD
, 1);