]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/ddr/fsl/main.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[people/ms/u-boot.git] / drivers / ddr / fsl / main.c
1 /*
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9 /*
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
13 */
14
15 #include <common.h>
16 #include <i2c.h>
17 #include <fsl_ddr_sdram.h>
18 #include <fsl_ddr.h>
19
20 /*
21 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
22 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
23 * all Power SoCs. But it could be different for ARM SoCs. For example,
24 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
25 * 0x00_8000_0000 ~ 0x00_ffff_ffff
26 * 0x80_8000_0000 ~ 0xff_ffff_ffff
27 */
28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
30 #endif
31
32 #ifdef CONFIG_PPC
33 #include <asm/fsl_law.h>
34
35 void fsl_ddr_set_lawbar(
36 const common_timing_params_t *memctl_common_params,
37 unsigned int memctl_interleaved,
38 unsigned int ctrl_num);
39 #endif
40
41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
42 #if defined(SPD_EEPROM_ADDRESS) || \
43 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
44 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
47 [0][0] = SPD_EEPROM_ADDRESS,
48 };
49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
53 };
54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
56 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
57 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
58 };
59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
61 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
62 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
63 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
64 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
65 };
66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
68 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
69 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
70 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
71 };
72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
74 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
75 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
76 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
77 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
78 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
79 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
80 };
81
82 #endif
83
84 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
85 {
86 int ret;
87
88 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
89
90 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
91 sizeof(generic_spd_eeprom_t));
92
93 if (ret) {
94 if (i2c_address ==
95 #ifdef SPD_EEPROM_ADDRESS
96 SPD_EEPROM_ADDRESS
97 #elif defined(SPD_EEPROM_ADDRESS1)
98 SPD_EEPROM_ADDRESS1
99 #endif
100 ) {
101 printf("DDR: failed to read SPD from address %u\n",
102 i2c_address);
103 } else {
104 debug("DDR: failed to read SPD from address %u\n",
105 i2c_address);
106 }
107 memset(spd, 0, sizeof(generic_spd_eeprom_t));
108 }
109 }
110
111 __attribute__((weak, alias("__get_spd")))
112 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
113
114 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
115 unsigned int ctrl_num)
116 {
117 unsigned int i;
118 unsigned int i2c_address = 0;
119
120 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
121 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
122 return;
123 }
124
125 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
126 i2c_address = spd_i2c_addr[ctrl_num][i];
127 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
128 }
129 }
130 #else
131 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
132 unsigned int ctrl_num)
133 {
134 }
135 #endif /* SPD_EEPROM_ADDRESSx */
136
137 /*
138 * ASSUMPTIONS:
139 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
140 * - Same memory data bus width on all controllers
141 *
142 * NOTES:
143 *
144 * The memory controller and associated documentation use confusing
145 * terminology when referring to the orgranization of DRAM.
146 *
147 * Here is a terminology translation table:
148 *
149 * memory controller/documention |industry |this code |signals
150 * -------------------------------|-----------|-----------|-----------------
151 * physical bank/bank |rank |rank |chip select (CS)
152 * logical bank/sub-bank |bank |bank |bank address (BA)
153 * page/row |row |page |row address
154 * ??? |column |column |column address
155 *
156 * The naming confusion is further exacerbated by the descriptions of the
157 * memory controller interleaving feature, where accesses are interleaved
158 * _BETWEEN_ two seperate memory controllers. This is configured only in
159 * CS0_CONFIG[INTLV_CTL] of each memory controller.
160 *
161 * memory controller documentation | number of chip selects
162 * | per memory controller supported
163 * --------------------------------|-----------------------------------------
164 * cache line interleaving | 1 (CS0 only)
165 * page interleaving | 1 (CS0 only)
166 * bank interleaving | 1 (CS0 only)
167 * superbank interleraving | depends on bank (chip select)
168 * | interleraving [rank interleaving]
169 * | mode used on every memory controller
170 *
171 * Even further confusing is the existence of the interleaving feature
172 * _WITHIN_ each memory controller. The feature is referred to in
173 * documentation as chip select interleaving or bank interleaving,
174 * although it is configured in the DDR_SDRAM_CFG field.
175 *
176 * Name of field | documentation name | this code
177 * -----------------------------|-----------------------|------------------
178 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
179 * | interleaving
180 */
181
182 const char *step_string_tbl[] = {
183 "STEP_GET_SPD",
184 "STEP_COMPUTE_DIMM_PARMS",
185 "STEP_COMPUTE_COMMON_PARMS",
186 "STEP_GATHER_OPTS",
187 "STEP_ASSIGN_ADDRESSES",
188 "STEP_COMPUTE_REGS",
189 "STEP_PROGRAM_REGS",
190 "STEP_ALL"
191 };
192
193 const char * step_to_string(unsigned int step) {
194
195 unsigned int s = __ilog2(step);
196
197 if ((1 << s) != step)
198 return step_string_tbl[7];
199
200 return step_string_tbl[s];
201 }
202
203 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
204 unsigned int dbw_cap_adj[])
205 {
206 int i, j;
207 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
208 unsigned long long rank_density, ctlr_density = 0;
209
210 /*
211 * If a reduced data width is requested, but the SPD
212 * specifies a physically wider device, adjust the
213 * computed dimm capacities accordingly before
214 * assigning addresses.
215 */
216 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
217 unsigned int found = 0;
218
219 switch (pinfo->memctl_opts[i].data_bus_width) {
220 case 2:
221 /* 16-bit */
222 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
223 unsigned int dw;
224 if (!pinfo->dimm_params[i][j].n_ranks)
225 continue;
226 dw = pinfo->dimm_params[i][j].primary_sdram_width;
227 if ((dw == 72 || dw == 64)) {
228 dbw_cap_adj[i] = 2;
229 break;
230 } else if ((dw == 40 || dw == 32)) {
231 dbw_cap_adj[i] = 1;
232 break;
233 }
234 }
235 break;
236
237 case 1:
238 /* 32-bit */
239 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
240 unsigned int dw;
241 dw = pinfo->dimm_params[i][j].data_width;
242 if (pinfo->dimm_params[i][j].n_ranks
243 && (dw == 72 || dw == 64)) {
244 /*
245 * FIXME: can't really do it
246 * like this because this just
247 * further reduces the memory
248 */
249 found = 1;
250 break;
251 }
252 }
253 if (found) {
254 dbw_cap_adj[i] = 1;
255 }
256 break;
257
258 case 0:
259 /* 64-bit */
260 break;
261
262 default:
263 printf("unexpected data bus width "
264 "specified controller %u\n", i);
265 return 1;
266 }
267 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
268 }
269
270 current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
271 total_mem = 0;
272 if (pinfo->memctl_opts[0].memctl_interleaving) {
273 rank_density = pinfo->dimm_params[0][0].rank_density >>
274 dbw_cap_adj[0];
275 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
276 FSL_DDR_CS0_CS1_CS2_CS3) {
277 case FSL_DDR_CS0_CS1_CS2_CS3:
278 ctlr_density = 4 * rank_density;
279 break;
280 case FSL_DDR_CS0_CS1:
281 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
282 ctlr_density = 2 * rank_density;
283 break;
284 case FSL_DDR_CS2_CS3:
285 default:
286 ctlr_density = rank_density;
287 break;
288 }
289 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
290 rank_density, ctlr_density);
291 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
292 if (pinfo->memctl_opts[i].memctl_interleaving) {
293 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
294 case FSL_DDR_256B_INTERLEAVING:
295 case FSL_DDR_CACHE_LINE_INTERLEAVING:
296 case FSL_DDR_PAGE_INTERLEAVING:
297 case FSL_DDR_BANK_INTERLEAVING:
298 case FSL_DDR_SUPERBANK_INTERLEAVING:
299 total_ctlr_mem = 2 * ctlr_density;
300 break;
301 case FSL_DDR_3WAY_1KB_INTERLEAVING:
302 case FSL_DDR_3WAY_4KB_INTERLEAVING:
303 case FSL_DDR_3WAY_8KB_INTERLEAVING:
304 total_ctlr_mem = 3 * ctlr_density;
305 break;
306 case FSL_DDR_4WAY_1KB_INTERLEAVING:
307 case FSL_DDR_4WAY_4KB_INTERLEAVING:
308 case FSL_DDR_4WAY_8KB_INTERLEAVING:
309 total_ctlr_mem = 4 * ctlr_density;
310 break;
311 default:
312 panic("Unknown interleaving mode");
313 }
314 pinfo->common_timing_params[i].base_address =
315 current_mem_base;
316 pinfo->common_timing_params[i].total_mem =
317 total_ctlr_mem;
318 total_mem = current_mem_base + total_ctlr_mem;
319 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
320 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
321 } else {
322 /* when 3rd controller not interleaved */
323 current_mem_base = total_mem;
324 total_ctlr_mem = 0;
325 pinfo->common_timing_params[i].base_address =
326 current_mem_base;
327 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
328 unsigned long long cap =
329 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
330 pinfo->dimm_params[i][j].base_address =
331 current_mem_base;
332 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
333 current_mem_base += cap;
334 total_ctlr_mem += cap;
335 }
336 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
337 pinfo->common_timing_params[i].total_mem =
338 total_ctlr_mem;
339 total_mem += total_ctlr_mem;
340 }
341 }
342 } else {
343 /*
344 * Simple linear assignment if memory
345 * controllers are not interleaved.
346 */
347 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
348 total_ctlr_mem = 0;
349 pinfo->common_timing_params[i].base_address =
350 current_mem_base;
351 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
352 /* Compute DIMM base addresses. */
353 unsigned long long cap =
354 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
355 pinfo->dimm_params[i][j].base_address =
356 current_mem_base;
357 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
358 current_mem_base += cap;
359 total_ctlr_mem += cap;
360 }
361 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
362 pinfo->common_timing_params[i].total_mem =
363 total_ctlr_mem;
364 total_mem += total_ctlr_mem;
365 }
366 }
367 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
368
369 return total_mem;
370 }
371
372 /* Use weak function to allow board file to override the address assignment */
373 __attribute__((weak, alias("__step_assign_addresses")))
374 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
375 unsigned int dbw_cap_adj[]);
376
377 unsigned long long
378 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
379 unsigned int size_only)
380 {
381 unsigned int i, j;
382 unsigned long long total_mem = 0;
383 int assert_reset;
384
385 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
386 common_timing_params_t *timing_params = pinfo->common_timing_params;
387 assert_reset = board_need_mem_reset();
388
389 /* data bus width capacity adjust shift amount */
390 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
391
392 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
393 dbw_capacity_adjust[i] = 0;
394 }
395
396 debug("starting at step %u (%s)\n",
397 start_step, step_to_string(start_step));
398
399 switch (start_step) {
400 case STEP_GET_SPD:
401 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
402 /* STEP 1: Gather all DIMM SPD data */
403 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
404 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
405 }
406
407 case STEP_COMPUTE_DIMM_PARMS:
408 /* STEP 2: Compute DIMM parameters from SPD data */
409
410 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
411 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
412 unsigned int retval;
413 generic_spd_eeprom_t *spd =
414 &(pinfo->spd_installed_dimms[i][j]);
415 dimm_params_t *pdimm =
416 &(pinfo->dimm_params[i][j]);
417
418 retval = compute_dimm_parameters(spd, pdimm, i);
419 #ifdef CONFIG_SYS_DDR_RAW_TIMING
420 if (!i && !j && retval) {
421 printf("SPD error on controller %d! "
422 "Trying fallback to raw timing "
423 "calculation\n", i);
424 fsl_ddr_get_dimm_params(pdimm, i, j);
425 }
426 #else
427 if (retval == 2) {
428 printf("Error: compute_dimm_parameters"
429 " non-zero returned FATAL value "
430 "for memctl=%u dimm=%u\n", i, j);
431 return 0;
432 }
433 #endif
434 if (retval) {
435 debug("Warning: compute_dimm_parameters"
436 " non-zero return value for memctl=%u "
437 "dimm=%u\n", i, j);
438 }
439 }
440 }
441
442 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
443 case STEP_COMPUTE_DIMM_PARMS:
444 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
445 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
446 dimm_params_t *pdimm =
447 &(pinfo->dimm_params[i][j]);
448 fsl_ddr_get_dimm_params(pdimm, i, j);
449 }
450 }
451 debug("Filling dimm parameters from board specific file\n");
452 #endif
453 case STEP_COMPUTE_COMMON_PARMS:
454 /*
455 * STEP 3: Compute a common set of timing parameters
456 * suitable for all of the DIMMs on each memory controller
457 */
458 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
459 debug("Computing lowest common DIMM"
460 " parameters for memctl=%u\n", i);
461 compute_lowest_common_dimm_parameters(
462 pinfo->dimm_params[i],
463 &timing_params[i],
464 CONFIG_DIMM_SLOTS_PER_CTLR);
465 }
466
467 case STEP_GATHER_OPTS:
468 /* STEP 4: Gather configuration requirements from user */
469 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
470 debug("Reloading memory controller "
471 "configuration options for memctl=%u\n", i);
472 /*
473 * This "reloads" the memory controller options
474 * to defaults. If the user "edits" an option,
475 * next_step points to the step after this,
476 * which is currently STEP_ASSIGN_ADDRESSES.
477 */
478 populate_memctl_options(
479 timing_params[i].all_dimms_registered,
480 &pinfo->memctl_opts[i],
481 pinfo->dimm_params[i], i);
482 /*
483 * For RDIMMs, JEDEC spec requires clocks to be stable
484 * before reset signal is deasserted. For the boards
485 * using fixed parameters, this function should be
486 * be called from board init file.
487 */
488 if (timing_params[i].all_dimms_registered)
489 assert_reset = 1;
490 }
491 if (assert_reset) {
492 debug("Asserting mem reset\n");
493 board_assert_mem_reset();
494 }
495
496 case STEP_ASSIGN_ADDRESSES:
497 /* STEP 5: Assign addresses to chip selects */
498 check_interleaving_options(pinfo);
499 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
500
501 case STEP_COMPUTE_REGS:
502 /* STEP 6: compute controller register values */
503 debug("FSL Memory ctrl register computation\n");
504 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
505 if (timing_params[i].ndimms_present == 0) {
506 memset(&ddr_reg[i], 0,
507 sizeof(fsl_ddr_cfg_regs_t));
508 continue;
509 }
510
511 compute_fsl_memctl_config_regs(
512 &pinfo->memctl_opts[i],
513 &ddr_reg[i], &timing_params[i],
514 pinfo->dimm_params[i],
515 dbw_capacity_adjust[i],
516 size_only);
517 }
518
519 default:
520 break;
521 }
522
523 {
524 /*
525 * Compute the amount of memory available just by
526 * looking for the highest valid CSn_BNDS value.
527 * This allows us to also experiment with using
528 * only CS0 when using dual-rank DIMMs.
529 */
530 unsigned int max_end = 0;
531
532 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
533 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
534 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
535 if (reg->cs[j].config & 0x80000000) {
536 unsigned int end;
537 /*
538 * 0xfffffff is a special value we put
539 * for unused bnds
540 */
541 if (reg->cs[j].bnds == 0xffffffff)
542 continue;
543 end = reg->cs[j].bnds & 0xffff;
544 if (end > max_end) {
545 max_end = end;
546 }
547 }
548 }
549 }
550
551 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
552 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
553 }
554
555 return total_mem;
556 }
557
558 /*
559 * fsl_ddr_sdram() -- this is the main function to be called by
560 * initdram() in the board file.
561 *
562 * It returns amount of memory configured in bytes.
563 */
564 phys_size_t fsl_ddr_sdram(void)
565 {
566 unsigned int i;
567 #ifdef CONFIG_PPC
568 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
569 #endif
570 unsigned long long total_memory;
571 fsl_ddr_info_t info;
572 int deassert_reset;
573
574 /* Reset info structure. */
575 memset(&info, 0, sizeof(fsl_ddr_info_t));
576
577 /* Compute it once normally. */
578 #ifdef CONFIG_FSL_DDR_INTERACTIVE
579 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
580 total_memory = fsl_ddr_interactive(&info, 0);
581 } else if (fsl_ddr_interactive_env_var_exists()) {
582 total_memory = fsl_ddr_interactive(&info, 1);
583 } else
584 #endif
585 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
586
587 /* setup 3-way interleaving before enabling DDRC */
588 if (info.memctl_opts[0].memctl_interleaving) {
589 switch (info.memctl_opts[0].memctl_interleaving_mode) {
590 case FSL_DDR_3WAY_1KB_INTERLEAVING:
591 case FSL_DDR_3WAY_4KB_INTERLEAVING:
592 case FSL_DDR_3WAY_8KB_INTERLEAVING:
593 fsl_ddr_set_intl3r(
594 info.memctl_opts[0].memctl_interleaving_mode);
595 break;
596 default:
597 break;
598 }
599 }
600
601 /*
602 * Program configuration registers.
603 * JEDEC specs requires clocks to be stable before deasserting reset
604 * for RDIMMs. Clocks start after chip select is enabled and clock
605 * control register is set. During step 1, all controllers have their
606 * registers set but not enabled. Step 2 proceeds after deasserting
607 * reset through board FPGA or GPIO.
608 * For non-registered DIMMs, initialization can go through but it is
609 * also OK to follow the same flow.
610 */
611 deassert_reset = board_need_mem_reset();
612 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
613 if (info.common_timing_params[i].all_dimms_registered)
614 deassert_reset = 1;
615 }
616 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
617 debug("Programming controller %u\n", i);
618 if (info.common_timing_params[i].ndimms_present == 0) {
619 debug("No dimms present on controller %u; "
620 "skipping programming\n", i);
621 continue;
622 }
623 /*
624 * The following call with step = 1 returns before enabling
625 * the controller. It has to finish with step = 2 later.
626 */
627 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
628 deassert_reset ? 1 : 0);
629 }
630 if (deassert_reset) {
631 /* Use board FPGA or GPIO to deassert reset signal */
632 debug("Deasserting mem reset\n");
633 board_deassert_mem_reset();
634 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
635 /* Call with step = 2 to continue initialization */
636 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
637 i, 2);
638 }
639 }
640
641 #ifdef CONFIG_PPC
642 /* program LAWs */
643 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
644 if (info.memctl_opts[i].memctl_interleaving) {
645 switch (info.memctl_opts[i].memctl_interleaving_mode) {
646 case FSL_DDR_CACHE_LINE_INTERLEAVING:
647 case FSL_DDR_PAGE_INTERLEAVING:
648 case FSL_DDR_BANK_INTERLEAVING:
649 case FSL_DDR_SUPERBANK_INTERLEAVING:
650 if (i == 0) {
651 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
652 fsl_ddr_set_lawbar(&info.common_timing_params[i],
653 law_memctl, i);
654 } else if (i == 2) {
655 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
656 fsl_ddr_set_lawbar(&info.common_timing_params[i],
657 law_memctl, i);
658 }
659 break;
660 case FSL_DDR_3WAY_1KB_INTERLEAVING:
661 case FSL_DDR_3WAY_4KB_INTERLEAVING:
662 case FSL_DDR_3WAY_8KB_INTERLEAVING:
663 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
664 if (i == 0) {
665 fsl_ddr_set_lawbar(&info.common_timing_params[i],
666 law_memctl, i);
667 }
668 break;
669 case FSL_DDR_4WAY_1KB_INTERLEAVING:
670 case FSL_DDR_4WAY_4KB_INTERLEAVING:
671 case FSL_DDR_4WAY_8KB_INTERLEAVING:
672 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
673 if (i == 0)
674 fsl_ddr_set_lawbar(&info.common_timing_params[i],
675 law_memctl, i);
676 /* place holder for future 4-way interleaving */
677 break;
678 default:
679 break;
680 }
681 } else {
682 switch (i) {
683 case 0:
684 law_memctl = LAW_TRGT_IF_DDR_1;
685 break;
686 case 1:
687 law_memctl = LAW_TRGT_IF_DDR_2;
688 break;
689 case 2:
690 law_memctl = LAW_TRGT_IF_DDR_3;
691 break;
692 case 3:
693 law_memctl = LAW_TRGT_IF_DDR_4;
694 break;
695 default:
696 break;
697 }
698 fsl_ddr_set_lawbar(&info.common_timing_params[i],
699 law_memctl, i);
700 }
701 }
702 #endif
703
704 debug("total_memory by %s = %llu\n", __func__, total_memory);
705
706 #if !defined(CONFIG_PHYS_64BIT)
707 /* Check for 4G or more. Bad. */
708 if (total_memory >= (1ull << 32)) {
709 puts("Detected ");
710 print_size(total_memory, " of memory\n");
711 printf(" This U-Boot only supports < 4G of DDR\n");
712 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
713 printf(" "); /* re-align to match init_func_ram print */
714 total_memory = CONFIG_MAX_MEM_MAPPED;
715 }
716 #endif
717
718 return total_memory;
719 }
720
721 /*
722 * fsl_ddr_sdram_size() - This function only returns the size of the total
723 * memory without setting ddr control registers.
724 */
725 phys_size_t
726 fsl_ddr_sdram_size(void)
727 {
728 fsl_ddr_info_t info;
729 unsigned long long total_memory = 0;
730
731 memset(&info, 0 , sizeof(fsl_ddr_info_t));
732
733 /* Compute it once normally. */
734 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
735
736 return total_memory;
737 }
"Das U-Boot" Source Tree