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[people/ms/u-boot.git] / drivers / ddr / fsl / main.c
1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9 /*
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
13 */
14
15 #include <common.h>
16 #include <i2c.h>
17 #include <fsl_ddr_sdram.h>
18 #include <fsl_ddr.h>
19
20 /*
21 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
22 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
23 * all Power SoCs. But it could be different for ARM SoCs. For example,
24 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
25 * 0x00_8000_0000 ~ 0x00_ffff_ffff
26 * 0x80_8000_0000 ~ 0xff_ffff_ffff
27 */
28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
30 #endif
31
32 #ifdef CONFIG_PPC
33 #include <asm/fsl_law.h>
34
35 void fsl_ddr_set_lawbar(
36 const common_timing_params_t *memctl_common_params,
37 unsigned int memctl_interleaved,
38 unsigned int ctrl_num);
39 #endif
40
41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
42 #if defined(SPD_EEPROM_ADDRESS) || \
43 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
44 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
47 [0][0] = SPD_EEPROM_ADDRESS,
48 };
49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
51 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
52 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
53 };
54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
56 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
57 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
58 };
59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
61 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
62 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
63 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
64 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
65 };
66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
68 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
69 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
70 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
71 };
72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
74 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
75 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
76 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
77 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
78 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
79 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
80 };
81
82 #endif
83
84 #define SPD_SPA0_ADDRESS 0x36
85 #define SPD_SPA1_ADDRESS 0x37
86
87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
88 {
89 int ret;
90 #ifdef CONFIG_SYS_FSL_DDR4
91 uint8_t dummy = 0;
92 #endif
93
94 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
95
96 #ifdef CONFIG_SYS_FSL_DDR4
97 /*
98 * DDR4 SPD has 384 to 512 bytes
99 * To access the lower 256 bytes, we need to set EE page address to 0
100 * To access the upper 256 bytes, we need to set EE page address to 1
101 * See Jedec standar No. 21-C for detail
102 */
103 i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
104 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
105 if (!ret) {
106 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
107 ret = i2c_read(i2c_address, 0, 1,
108 (uchar *)((ulong)spd + 256),
109 min(256,
110 (int)sizeof(generic_spd_eeprom_t) - 256));
111 }
112 #else
113 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
114 sizeof(generic_spd_eeprom_t));
115 #endif
116
117 if (ret) {
118 if (i2c_address ==
119 #ifdef SPD_EEPROM_ADDRESS
120 SPD_EEPROM_ADDRESS
121 #elif defined(SPD_EEPROM_ADDRESS1)
122 SPD_EEPROM_ADDRESS1
123 #endif
124 ) {
125 printf("DDR: failed to read SPD from address %u\n",
126 i2c_address);
127 } else {
128 debug("DDR: failed to read SPD from address %u\n",
129 i2c_address);
130 }
131 memset(spd, 0, sizeof(generic_spd_eeprom_t));
132 }
133 }
134
135 __attribute__((weak, alias("__get_spd")))
136 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
137
138 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
139 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
140 {
141 unsigned int i;
142 unsigned int i2c_address = 0;
143
144 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
145 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
146 return;
147 }
148
149 for (i = 0; i < dimm_slots_per_ctrl; i++) {
150 i2c_address = spd_i2c_addr[ctrl_num][i];
151 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
152 }
153 }
154 #else
155 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
156 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
157 {
158 }
159 #endif /* SPD_EEPROM_ADDRESSx */
160
161 /*
162 * ASSUMPTIONS:
163 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
164 * - Same memory data bus width on all controllers
165 *
166 * NOTES:
167 *
168 * The memory controller and associated documentation use confusing
169 * terminology when referring to the orgranization of DRAM.
170 *
171 * Here is a terminology translation table:
172 *
173 * memory controller/documention |industry |this code |signals
174 * -------------------------------|-----------|-----------|-----------------
175 * physical bank/bank |rank |rank |chip select (CS)
176 * logical bank/sub-bank |bank |bank |bank address (BA)
177 * page/row |row |page |row address
178 * ??? |column |column |column address
179 *
180 * The naming confusion is further exacerbated by the descriptions of the
181 * memory controller interleaving feature, where accesses are interleaved
182 * _BETWEEN_ two seperate memory controllers. This is configured only in
183 * CS0_CONFIG[INTLV_CTL] of each memory controller.
184 *
185 * memory controller documentation | number of chip selects
186 * | per memory controller supported
187 * --------------------------------|-----------------------------------------
188 * cache line interleaving | 1 (CS0 only)
189 * page interleaving | 1 (CS0 only)
190 * bank interleaving | 1 (CS0 only)
191 * superbank interleraving | depends on bank (chip select)
192 * | interleraving [rank interleaving]
193 * | mode used on every memory controller
194 *
195 * Even further confusing is the existence of the interleaving feature
196 * _WITHIN_ each memory controller. The feature is referred to in
197 * documentation as chip select interleaving or bank interleaving,
198 * although it is configured in the DDR_SDRAM_CFG field.
199 *
200 * Name of field | documentation name | this code
201 * -----------------------------|-----------------------|------------------
202 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
203 * | interleaving
204 */
205
206 const char *step_string_tbl[] = {
207 "STEP_GET_SPD",
208 "STEP_COMPUTE_DIMM_PARMS",
209 "STEP_COMPUTE_COMMON_PARMS",
210 "STEP_GATHER_OPTS",
211 "STEP_ASSIGN_ADDRESSES",
212 "STEP_COMPUTE_REGS",
213 "STEP_PROGRAM_REGS",
214 "STEP_ALL"
215 };
216
217 const char * step_to_string(unsigned int step) {
218
219 unsigned int s = __ilog2(step);
220
221 if ((1 << s) != step)
222 return step_string_tbl[7];
223
224 if (s >= ARRAY_SIZE(step_string_tbl)) {
225 printf("Error for the step in %s\n", __func__);
226 s = 0;
227 }
228
229 return step_string_tbl[s];
230 }
231
232 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
233 unsigned int dbw_cap_adj[])
234 {
235 unsigned int i, j;
236 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
237 unsigned long long rank_density, ctlr_density = 0;
238 unsigned int first_ctrl = pinfo->first_ctrl;
239 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
240
241 /*
242 * If a reduced data width is requested, but the SPD
243 * specifies a physically wider device, adjust the
244 * computed dimm capacities accordingly before
245 * assigning addresses.
246 */
247 for (i = first_ctrl; i <= last_ctrl; i++) {
248 unsigned int found = 0;
249
250 switch (pinfo->memctl_opts[i].data_bus_width) {
251 case 2:
252 /* 16-bit */
253 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
254 unsigned int dw;
255 if (!pinfo->dimm_params[i][j].n_ranks)
256 continue;
257 dw = pinfo->dimm_params[i][j].primary_sdram_width;
258 if ((dw == 72 || dw == 64)) {
259 dbw_cap_adj[i] = 2;
260 break;
261 } else if ((dw == 40 || dw == 32)) {
262 dbw_cap_adj[i] = 1;
263 break;
264 }
265 }
266 break;
267
268 case 1:
269 /* 32-bit */
270 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
271 unsigned int dw;
272 dw = pinfo->dimm_params[i][j].data_width;
273 if (pinfo->dimm_params[i][j].n_ranks
274 && (dw == 72 || dw == 64)) {
275 /*
276 * FIXME: can't really do it
277 * like this because this just
278 * further reduces the memory
279 */
280 found = 1;
281 break;
282 }
283 }
284 if (found) {
285 dbw_cap_adj[i] = 1;
286 }
287 break;
288
289 case 0:
290 /* 64-bit */
291 break;
292
293 default:
294 printf("unexpected data bus width "
295 "specified controller %u\n", i);
296 return 1;
297 }
298 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
299 }
300
301 current_mem_base = pinfo->mem_base;
302 total_mem = 0;
303 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
304 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
305 dbw_cap_adj[first_ctrl];
306 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
307 FSL_DDR_CS0_CS1_CS2_CS3) {
308 case FSL_DDR_CS0_CS1_CS2_CS3:
309 ctlr_density = 4 * rank_density;
310 break;
311 case FSL_DDR_CS0_CS1:
312 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
313 ctlr_density = 2 * rank_density;
314 break;
315 case FSL_DDR_CS2_CS3:
316 default:
317 ctlr_density = rank_density;
318 break;
319 }
320 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
321 rank_density, ctlr_density);
322 for (i = first_ctrl; i <= last_ctrl; i++) {
323 if (pinfo->memctl_opts[i].memctl_interleaving) {
324 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
325 case FSL_DDR_256B_INTERLEAVING:
326 case FSL_DDR_CACHE_LINE_INTERLEAVING:
327 case FSL_DDR_PAGE_INTERLEAVING:
328 case FSL_DDR_BANK_INTERLEAVING:
329 case FSL_DDR_SUPERBANK_INTERLEAVING:
330 total_ctlr_mem = 2 * ctlr_density;
331 break;
332 case FSL_DDR_3WAY_1KB_INTERLEAVING:
333 case FSL_DDR_3WAY_4KB_INTERLEAVING:
334 case FSL_DDR_3WAY_8KB_INTERLEAVING:
335 total_ctlr_mem = 3 * ctlr_density;
336 break;
337 case FSL_DDR_4WAY_1KB_INTERLEAVING:
338 case FSL_DDR_4WAY_4KB_INTERLEAVING:
339 case FSL_DDR_4WAY_8KB_INTERLEAVING:
340 total_ctlr_mem = 4 * ctlr_density;
341 break;
342 default:
343 panic("Unknown interleaving mode");
344 }
345 pinfo->common_timing_params[i].base_address =
346 current_mem_base;
347 pinfo->common_timing_params[i].total_mem =
348 total_ctlr_mem;
349 total_mem = current_mem_base + total_ctlr_mem;
350 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
351 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
352 } else {
353 /* when 3rd controller not interleaved */
354 current_mem_base = total_mem;
355 total_ctlr_mem = 0;
356 pinfo->common_timing_params[i].base_address =
357 current_mem_base;
358 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
359 unsigned long long cap =
360 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
361 pinfo->dimm_params[i][j].base_address =
362 current_mem_base;
363 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
364 current_mem_base += cap;
365 total_ctlr_mem += cap;
366 }
367 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
368 pinfo->common_timing_params[i].total_mem =
369 total_ctlr_mem;
370 total_mem += total_ctlr_mem;
371 }
372 }
373 } else {
374 /*
375 * Simple linear assignment if memory
376 * controllers are not interleaved.
377 */
378 for (i = first_ctrl; i <= last_ctrl; i++) {
379 total_ctlr_mem = 0;
380 pinfo->common_timing_params[i].base_address =
381 current_mem_base;
382 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
383 /* Compute DIMM base addresses. */
384 unsigned long long cap =
385 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
386 pinfo->dimm_params[i][j].base_address =
387 current_mem_base;
388 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
389 current_mem_base += cap;
390 total_ctlr_mem += cap;
391 }
392 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
393 pinfo->common_timing_params[i].total_mem =
394 total_ctlr_mem;
395 total_mem += total_ctlr_mem;
396 }
397 }
398 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
399
400 return total_mem;
401 }
402
403 /* Use weak function to allow board file to override the address assignment */
404 __attribute__((weak, alias("__step_assign_addresses")))
405 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
406 unsigned int dbw_cap_adj[]);
407
408 unsigned long long
409 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
410 unsigned int size_only)
411 {
412 unsigned int i, j;
413 unsigned long long total_mem = 0;
414 int assert_reset = 0;
415 unsigned int first_ctrl = pinfo->first_ctrl;
416 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
417 __maybe_unused int retval;
418 __maybe_unused bool goodspd = false;
419 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
420
421 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
422 common_timing_params_t *timing_params = pinfo->common_timing_params;
423 if (pinfo->board_need_mem_reset)
424 assert_reset = pinfo->board_need_mem_reset();
425
426 /* data bus width capacity adjust shift amount */
427 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
428
429 for (i = first_ctrl; i <= last_ctrl; i++)
430 dbw_capacity_adjust[i] = 0;
431
432 debug("starting at step %u (%s)\n",
433 start_step, step_to_string(start_step));
434
435 switch (start_step) {
436 case STEP_GET_SPD:
437 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
438 /* STEP 1: Gather all DIMM SPD data */
439 for (i = first_ctrl; i <= last_ctrl; i++) {
440 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
441 dimm_slots_per_ctrl);
442 }
443
444 case STEP_COMPUTE_DIMM_PARMS:
445 /* STEP 2: Compute DIMM parameters from SPD data */
446
447 for (i = first_ctrl; i <= last_ctrl; i++) {
448 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
449 generic_spd_eeprom_t *spd =
450 &(pinfo->spd_installed_dimms[i][j]);
451 dimm_params_t *pdimm =
452 &(pinfo->dimm_params[i][j]);
453 retval = compute_dimm_parameters(spd, pdimm, i);
454 #ifdef CONFIG_SYS_DDR_RAW_TIMING
455 if (!i && !j && retval) {
456 printf("SPD error on controller %d! "
457 "Trying fallback to raw timing "
458 "calculation\n", i);
459 retval = fsl_ddr_get_dimm_params(pdimm,
460 i, j);
461 }
462 #else
463 if (retval == 2) {
464 printf("Error: compute_dimm_parameters"
465 " non-zero returned FATAL value "
466 "for memctl=%u dimm=%u\n", i, j);
467 return 0;
468 }
469 #endif
470 if (retval) {
471 debug("Warning: compute_dimm_parameters"
472 " non-zero return value for memctl=%u "
473 "dimm=%u\n", i, j);
474 } else {
475 goodspd = true;
476 }
477 }
478 }
479 if (!goodspd) {
480 /*
481 * No valid SPD found
482 * Throw an error if this is for main memory, i.e.
483 * first_ctrl == 0. Otherwise, siliently return 0
484 * as the memory size.
485 */
486 if (first_ctrl == 0)
487 printf("Error: No valid SPD detected.\n");
488
489 return 0;
490 }
491 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
492 case STEP_COMPUTE_DIMM_PARMS:
493 for (i = first_ctrl; i <= last_ctrl; i++) {
494 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
495 dimm_params_t *pdimm =
496 &(pinfo->dimm_params[i][j]);
497 fsl_ddr_get_dimm_params(pdimm, i, j);
498 }
499 }
500 debug("Filling dimm parameters from board specific file\n");
501 #endif
502 case STEP_COMPUTE_COMMON_PARMS:
503 /*
504 * STEP 3: Compute a common set of timing parameters
505 * suitable for all of the DIMMs on each memory controller
506 */
507 for (i = first_ctrl; i <= last_ctrl; i++) {
508 debug("Computing lowest common DIMM"
509 " parameters for memctl=%u\n", i);
510 compute_lowest_common_dimm_parameters(
511 pinfo->dimm_params[i],
512 &timing_params[i],
513 CONFIG_DIMM_SLOTS_PER_CTLR);
514 }
515
516 case STEP_GATHER_OPTS:
517 /* STEP 4: Gather configuration requirements from user */
518 for (i = first_ctrl; i <= last_ctrl; i++) {
519 debug("Reloading memory controller "
520 "configuration options for memctl=%u\n", i);
521 /*
522 * This "reloads" the memory controller options
523 * to defaults. If the user "edits" an option,
524 * next_step points to the step after this,
525 * which is currently STEP_ASSIGN_ADDRESSES.
526 */
527 populate_memctl_options(
528 timing_params[i].all_dimms_registered,
529 &pinfo->memctl_opts[i],
530 pinfo->dimm_params[i], i);
531 /*
532 * For RDIMMs, JEDEC spec requires clocks to be stable
533 * before reset signal is deasserted. For the boards
534 * using fixed parameters, this function should be
535 * be called from board init file.
536 */
537 if (timing_params[i].all_dimms_registered)
538 assert_reset = 1;
539 }
540 if (assert_reset && !size_only) {
541 if (pinfo->board_mem_reset) {
542 debug("Asserting mem reset\n");
543 pinfo->board_mem_reset();
544 } else {
545 debug("Asserting mem reset missing\n");
546 }
547 }
548
549 case STEP_ASSIGN_ADDRESSES:
550 /* STEP 5: Assign addresses to chip selects */
551 check_interleaving_options(pinfo);
552 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
553 debug("Total mem %llu assigned\n", total_mem);
554
555 case STEP_COMPUTE_REGS:
556 /* STEP 6: compute controller register values */
557 debug("FSL Memory ctrl register computation\n");
558 for (i = first_ctrl; i <= last_ctrl; i++) {
559 if (timing_params[i].ndimms_present == 0) {
560 memset(&ddr_reg[i], 0,
561 sizeof(fsl_ddr_cfg_regs_t));
562 continue;
563 }
564
565 compute_fsl_memctl_config_regs(
566 &pinfo->memctl_opts[i],
567 &ddr_reg[i], &timing_params[i],
568 pinfo->dimm_params[i],
569 dbw_capacity_adjust[i],
570 size_only);
571 }
572
573 default:
574 break;
575 }
576
577 {
578 /*
579 * Compute the amount of memory available just by
580 * looking for the highest valid CSn_BNDS value.
581 * This allows us to also experiment with using
582 * only CS0 when using dual-rank DIMMs.
583 */
584 unsigned int max_end = 0;
585
586 for (i = first_ctrl; i <= last_ctrl; i++) {
587 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
588 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
589 if (reg->cs[j].config & 0x80000000) {
590 unsigned int end;
591 /*
592 * 0xfffffff is a special value we put
593 * for unused bnds
594 */
595 if (reg->cs[j].bnds == 0xffffffff)
596 continue;
597 end = reg->cs[j].bnds & 0xffff;
598 if (end > max_end) {
599 max_end = end;
600 }
601 }
602 }
603 }
604
605 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
606 0xFFFFFFULL) - pinfo->mem_base;
607 }
608
609 return total_mem;
610 }
611
612 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
613 {
614 unsigned int i, first_ctrl, last_ctrl;
615 #ifdef CONFIG_PPC
616 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
617 #endif
618 unsigned long long total_memory;
619 int deassert_reset = 0;
620
621 first_ctrl = pinfo->first_ctrl;
622 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
623
624 /* Compute it once normally. */
625 #ifdef CONFIG_FSL_DDR_INTERACTIVE
626 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
627 total_memory = fsl_ddr_interactive(pinfo, 0);
628 } else if (fsl_ddr_interactive_env_var_exists()) {
629 total_memory = fsl_ddr_interactive(pinfo, 1);
630 } else
631 #endif
632 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
633
634 /* setup 3-way interleaving before enabling DDRC */
635 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
636 case FSL_DDR_3WAY_1KB_INTERLEAVING:
637 case FSL_DDR_3WAY_4KB_INTERLEAVING:
638 case FSL_DDR_3WAY_8KB_INTERLEAVING:
639 fsl_ddr_set_intl3r(
640 pinfo->memctl_opts[first_ctrl].
641 memctl_interleaving_mode);
642 break;
643 default:
644 break;
645 }
646
647 /*
648 * Program configuration registers.
649 * JEDEC specs requires clocks to be stable before deasserting reset
650 * for RDIMMs. Clocks start after chip select is enabled and clock
651 * control register is set. During step 1, all controllers have their
652 * registers set but not enabled. Step 2 proceeds after deasserting
653 * reset through board FPGA or GPIO.
654 * For non-registered DIMMs, initialization can go through but it is
655 * also OK to follow the same flow.
656 */
657 if (pinfo->board_need_mem_reset)
658 deassert_reset = pinfo->board_need_mem_reset();
659 for (i = first_ctrl; i <= last_ctrl; i++) {
660 if (pinfo->common_timing_params[i].all_dimms_registered)
661 deassert_reset = 1;
662 }
663 for (i = first_ctrl; i <= last_ctrl; i++) {
664 debug("Programming controller %u\n", i);
665 if (pinfo->common_timing_params[i].ndimms_present == 0) {
666 debug("No dimms present on controller %u; "
667 "skipping programming\n", i);
668 continue;
669 }
670 /*
671 * The following call with step = 1 returns before enabling
672 * the controller. It has to finish with step = 2 later.
673 */
674 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
675 deassert_reset ? 1 : 0);
676 }
677 if (deassert_reset) {
678 /* Use board FPGA or GPIO to deassert reset signal */
679 if (pinfo->board_mem_de_reset) {
680 debug("Deasserting mem reset\n");
681 pinfo->board_mem_de_reset();
682 } else {
683 debug("Deasserting mem reset missing\n");
684 }
685 for (i = first_ctrl; i <= last_ctrl; i++) {
686 /* Call with step = 2 to continue initialization */
687 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
688 i, 2);
689 }
690 }
691
692 #ifdef CONFIG_PPC
693 /* program LAWs */
694 for (i = first_ctrl; i <= last_ctrl; i++) {
695 if (pinfo->memctl_opts[i].memctl_interleaving) {
696 switch (pinfo->memctl_opts[i].
697 memctl_interleaving_mode) {
698 case FSL_DDR_CACHE_LINE_INTERLEAVING:
699 case FSL_DDR_PAGE_INTERLEAVING:
700 case FSL_DDR_BANK_INTERLEAVING:
701 case FSL_DDR_SUPERBANK_INTERLEAVING:
702 if (i % 2)
703 break;
704 if (i == 0) {
705 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
706 fsl_ddr_set_lawbar(
707 &pinfo->common_timing_params[i],
708 law_memctl, i);
709 }
710 #if CONFIG_NUM_DDR_CONTROLLERS > 3
711 else if (i == 2) {
712 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
713 fsl_ddr_set_lawbar(
714 &pinfo->common_timing_params[i],
715 law_memctl, i);
716 }
717 #endif
718 break;
719 case FSL_DDR_3WAY_1KB_INTERLEAVING:
720 case FSL_DDR_3WAY_4KB_INTERLEAVING:
721 case FSL_DDR_3WAY_8KB_INTERLEAVING:
722 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
723 if (i == 0) {
724 fsl_ddr_set_lawbar(
725 &pinfo->common_timing_params[i],
726 law_memctl, i);
727 }
728 break;
729 case FSL_DDR_4WAY_1KB_INTERLEAVING:
730 case FSL_DDR_4WAY_4KB_INTERLEAVING:
731 case FSL_DDR_4WAY_8KB_INTERLEAVING:
732 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
733 if (i == 0)
734 fsl_ddr_set_lawbar(
735 &pinfo->common_timing_params[i],
736 law_memctl, i);
737 /* place holder for future 4-way interleaving */
738 break;
739 default:
740 break;
741 }
742 } else {
743 switch (i) {
744 case 0:
745 law_memctl = LAW_TRGT_IF_DDR_1;
746 break;
747 case 1:
748 law_memctl = LAW_TRGT_IF_DDR_2;
749 break;
750 case 2:
751 law_memctl = LAW_TRGT_IF_DDR_3;
752 break;
753 case 3:
754 law_memctl = LAW_TRGT_IF_DDR_4;
755 break;
756 default:
757 break;
758 }
759 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
760 law_memctl, i);
761 }
762 }
763 #endif
764
765 debug("total_memory by %s = %llu\n", __func__, total_memory);
766
767 #if !defined(CONFIG_PHYS_64BIT)
768 /* Check for 4G or more. Bad. */
769 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
770 puts("Detected ");
771 print_size(total_memory, " of memory\n");
772 printf(" This U-Boot only supports < 4G of DDR\n");
773 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
774 printf(" "); /* re-align to match init_func_ram print */
775 total_memory = CONFIG_MAX_MEM_MAPPED;
776 }
777 #endif
778
779 return total_memory;
780 }
781
782 /*
783 * fsl_ddr_sdram(void) -- this is the main function to be
784 * called by initdram() in the board file.
785 *
786 * It returns amount of memory configured in bytes.
787 */
788 phys_size_t fsl_ddr_sdram(void)
789 {
790 fsl_ddr_info_t info;
791
792 /* Reset info structure. */
793 memset(&info, 0, sizeof(fsl_ddr_info_t));
794 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
795 info.first_ctrl = 0;
796 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
797 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
798 info.board_need_mem_reset = board_need_mem_reset;
799 info.board_mem_reset = board_assert_mem_reset;
800 info.board_mem_de_reset = board_deassert_mem_reset;
801
802 return __fsl_ddr_sdram(&info);
803 }
804
805 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
806 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
807 unsigned int first_ctrl,
808 unsigned int num_ctrls,
809 unsigned int dimm_slots_per_ctrl,
810 int (*board_need_reset)(void),
811 void (*board_reset)(void),
812 void (*board_de_reset)(void))
813 {
814 fsl_ddr_info_t info;
815
816 /* Reset info structure. */
817 memset(&info, 0, sizeof(fsl_ddr_info_t));
818 info.mem_base = base;
819 info.first_ctrl = first_ctrl;
820 info.num_ctrls = num_ctrls;
821 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
822 info.board_need_mem_reset = board_need_reset;
823 info.board_mem_reset = board_reset;
824 info.board_mem_de_reset = board_de_reset;
825
826 return __fsl_ddr_sdram(&info);
827 }
828 #endif
829
830 /*
831 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
832 * size of the total memory without setting ddr control registers.
833 */
834 phys_size_t
835 fsl_ddr_sdram_size(void)
836 {
837 fsl_ddr_info_t info;
838 unsigned long long total_memory = 0;
839
840 memset(&info, 0 , sizeof(fsl_ddr_info_t));
841 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
842 info.first_ctrl = 0;
843 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
844 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
845 info.board_need_mem_reset = NULL;
846
847 /* Compute it once normally. */
848 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
849
850 return total_memory;
851 }
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