drivers/ddr/fsl/mpc85xx_ddr_gen2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/processor.h>
   9 #include <fsl_ddr_sdram.h>
  10
  11 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  12 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  13 #endif
  14
  15 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  16                              unsigned int ctrl_num, int step)
  17 {
  18         unsigned int i;
  19         struct ccsr_ddr __iomem *ddr =
  20                 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  21
  22 #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
  23         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  24         uint svr;
  25 #endif
  26
  27         if (ctrl_num) {
  28                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  29                 return;
  30         }
  31
  32 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  33         /*
  34          * Set the DDR IO receiver to an acceptable bias point.
  35          * Fixed in Rev 2.1.
  36          */
  37         svr = get_svr();
  38         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
  39                 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
  40                    SDRAM_CFG_SDRAM_TYPE_DDR2)
  41                         out_be32(&gur->ddrioovcr, 0x90000000);
  42                 else
  43                         out_be32(&gur->ddrioovcr, 0xA8000000);
  44         }
  45 #endif
  46
  47         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  48                 if (i == 0) {
  49                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  50                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  51
  52                 } else if (i == 1) {
  53                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  54                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  55
  56                 } else if (i == 2) {
  57                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  58                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  59
  60                 } else if (i == 3) {
  61                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  62                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  63                 }
  64         }
  65
  66         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  67         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  68         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  69         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  70         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  71         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  72         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  73         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  74         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  75         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  76         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  77         out_be32(&ddr->init_addr, regs->ddr_init_addr);
  78         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  79
  80         /*
  81          * 200 painful micro-seconds must elapse between
  82          * the DDR clock setup and the DDR config enable.
  83          */
  84         udelay(200);
  85         asm volatile("sync;isync");
  86
  87         out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  88
  89         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
  90         while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
  91                 udelay(10000);          /* throttle polling rate */
  92         }
  93 }