2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t
*popts
,
23 unsigned int ctrl_num
);
26 unsigned int odt_rd_cfg
;
27 unsigned int odt_wr_cfg
;
28 unsigned int odt_rtt_norm
;
29 unsigned int odt_rtt_wr
;
32 #ifdef CONFIG_SYS_FSL_DDR3
33 static const struct dynamic_odt single_Q
[4] = {
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
42 FSL_DDR_ODT_NEVER
, /* tied high */
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
54 FSL_DDR_ODT_NEVER
, /* tied high */
60 static const struct dynamic_odt single_D
[4] = {
77 static const struct dynamic_odt single_S
[4] = {
89 static const struct dynamic_odt dual_DD
[4] = {
92 FSL_DDR_ODT_SAME_DIMM
,
97 FSL_DDR_ODT_OTHER_DIMM
,
98 FSL_DDR_ODT_OTHER_DIMM
,
104 FSL_DDR_ODT_SAME_DIMM
,
109 FSL_DDR_ODT_OTHER_DIMM
,
110 FSL_DDR_ODT_OTHER_DIMM
,
116 static const struct dynamic_odt dual_DS
[4] = {
119 FSL_DDR_ODT_SAME_DIMM
,
124 FSL_DDR_ODT_OTHER_DIMM
,
125 FSL_DDR_ODT_OTHER_DIMM
,
130 FSL_DDR_ODT_OTHER_DIMM
,
137 static const struct dynamic_odt dual_SD
[4] = {
139 FSL_DDR_ODT_OTHER_DIMM
,
147 FSL_DDR_ODT_SAME_DIMM
,
152 FSL_DDR_ODT_OTHER_DIMM
,
153 FSL_DDR_ODT_OTHER_DIMM
,
159 static const struct dynamic_odt dual_SS
[4] = {
161 FSL_DDR_ODT_OTHER_DIMM
,
168 FSL_DDR_ODT_OTHER_DIMM
,
176 static const struct dynamic_odt dual_D0
[4] = {
179 FSL_DDR_ODT_SAME_DIMM
,
193 static const struct dynamic_odt dual_0D
[4] = {
198 FSL_DDR_ODT_SAME_DIMM
,
210 static const struct dynamic_odt dual_S0
[4] = {
223 static const struct dynamic_odt dual_0S
[4] = {
236 static const struct dynamic_odt odt_unknown
[4] = {
262 #else /* CONFIG_SYS_FSL_DDR3 */
263 static const struct dynamic_odt single_Q
[4] = {
270 static const struct dynamic_odt single_D
[4] = {
287 static const struct dynamic_odt single_S
[4] = {
299 static const struct dynamic_odt dual_DD
[4] = {
301 FSL_DDR_ODT_OTHER_DIMM
,
302 FSL_DDR_ODT_OTHER_DIMM
,
313 FSL_DDR_ODT_OTHER_DIMM
,
314 FSL_DDR_ODT_OTHER_DIMM
,
326 static const struct dynamic_odt dual_DS
[4] = {
328 FSL_DDR_ODT_OTHER_DIMM
,
329 FSL_DDR_ODT_OTHER_DIMM
,
340 FSL_DDR_ODT_OTHER_DIMM
,
341 FSL_DDR_ODT_OTHER_DIMM
,
348 static const struct dynamic_odt dual_SD
[4] = {
350 FSL_DDR_ODT_OTHER_DIMM
,
351 FSL_DDR_ODT_OTHER_DIMM
,
357 FSL_DDR_ODT_OTHER_DIMM
,
358 FSL_DDR_ODT_OTHER_DIMM
,
370 static const struct dynamic_odt dual_SS
[4] = {
372 FSL_DDR_ODT_OTHER_DIMM
,
373 FSL_DDR_ODT_OTHER_DIMM
,
379 FSL_DDR_ODT_OTHER_DIMM
,
380 FSL_DDR_ODT_OTHER_DIMM
,
387 static const struct dynamic_odt dual_D0
[4] = {
404 static const struct dynamic_odt dual_0D
[4] = {
421 static const struct dynamic_odt dual_S0
[4] = {
434 static const struct dynamic_odt dual_0S
[4] = {
447 static const struct dynamic_odt odt_unknown
[4] = {
476 * Automatically seleect bank interleaving mode based on DIMMs
477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
478 * This function only deal with one or two slots per controller.
480 static inline unsigned int auto_bank_intlv(dimm_params_t
*pdimm
)
482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
483 if (pdimm
[0].n_ranks
== 4)
484 return FSL_DDR_CS0_CS1_CS2_CS3
;
485 else if (pdimm
[0].n_ranks
== 2)
486 return FSL_DDR_CS0_CS1
;
487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
489 if (pdimm
[0].n_ranks
== 4)
490 return FSL_DDR_CS0_CS1_CS2_CS3
;
492 if (pdimm
[0].n_ranks
== 2) {
493 if (pdimm
[1].n_ranks
== 2)
494 return FSL_DDR_CS0_CS1_CS2_CS3
;
496 return FSL_DDR_CS0_CS1
;
502 unsigned int populate_memctl_options(int all_dimms_registered
,
503 memctl_options_t
*popts
,
504 dimm_params_t
*pdimm
,
505 unsigned int ctrl_num
)
508 char buffer
[HWCONFIG_BUFFER_SIZE
];
510 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
511 const struct dynamic_odt
*pdodt
= odt_unknown
;
516 * Extract hwconfig from environment since we have not properly setup
517 * the environment but need it for ddr config params
519 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
522 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
523 /* Chip select options. */
524 if (CONFIG_DIMM_SLOTS_PER_CTLR
== 1) {
525 switch (pdimm
[0].n_ranks
) {
536 } else if (CONFIG_DIMM_SLOTS_PER_CTLR
== 2) {
537 switch (pdimm
[0].n_ranks
) {
538 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
541 if (pdimm
[1].n_ranks
)
542 printf("Error: Quad- and Dual-rank DIMMs "
543 "cannot be used together\n");
547 switch (pdimm
[1].n_ranks
) {
560 switch (pdimm
[1].n_ranks
) {
573 switch (pdimm
[1].n_ranks
) {
586 /* Pick chip-select local options. */
587 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
588 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
589 popts
->cs_local_opts
[i
].odt_rd_cfg
= pdodt
[i
].odt_rd_cfg
;
590 popts
->cs_local_opts
[i
].odt_wr_cfg
= pdodt
[i
].odt_wr_cfg
;
591 popts
->cs_local_opts
[i
].odt_rtt_norm
= pdodt
[i
].odt_rtt_norm
;
592 popts
->cs_local_opts
[i
].odt_rtt_wr
= pdodt
[i
].odt_rtt_wr
;
594 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
595 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;
597 popts
->cs_local_opts
[i
].auto_precharge
= 0;
600 /* Pick interleaving mode. */
603 * 0 = no interleaving
604 * 1 = interleaving between 2 controllers
606 popts
->memctl_interleaving
= 0;
612 * 3 = superbank (only if CS interleaving is enabled)
614 popts
->memctl_interleaving_mode
= 0;
617 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
618 * 1: page: bit to the left of the column bits selects the memctl
619 * 2: bank: bit to the left of the bank bits selects the memctl
620 * 3: superbank: bit to the left of the chip select selects the memctl
622 * NOTE: ba_intlv (rank interleaving) is independent of memory
623 * controller interleaving; it is only within a memory controller.
624 * Must use superbank interleaving if rank interleaving is used and
625 * memory controller interleaving is enabled.
632 * 0x60 = CS0,CS1 + CS2,CS3
633 * 0x04 = CS0,CS1,CS2,CS3
635 popts
->ba_intlv_ctl
= 0;
637 /* Memory Organization Parameters */
638 popts
->registered_dimm_en
= all_dimms_registered
;
640 /* Operational Mode Paramters */
643 popts
->ecc_mode
= 0; /* 0 = disabled, 1 = enabled */
644 #ifdef CONFIG_DDR_ECC
645 if (hwconfig_sub_f("fsl_ddr", "ecc", buf
)) {
646 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf
))
651 popts
->ecc_init_using_memctl
= 1; /* 0 = use DMA, 1 = use memctl */
658 #if defined(CONFIG_SYS_FSL_DDR1)
659 popts
->dqs_config
= 0;
660 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
661 popts
->dqs_config
= 1;
664 /* Choose self-refresh during sleep. */
665 popts
->self_refresh_in_sleep
= 1;
667 /* Choose dynamic power management mode. */
668 popts
->dynamic_power
= 0;
671 * check first dimm for primary sdram width
672 * presuming all dimms are similar
673 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
675 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
676 if (pdimm
[0].n_ranks
!= 0) {
677 if ((pdimm
[0].data_width
>= 64) && \
678 (pdimm
[0].data_width
<= 72))
679 popts
->data_bus_width
= 0;
680 else if ((pdimm
[0].data_width
>= 32) || \
681 (pdimm
[0].data_width
<= 40))
682 popts
->data_bus_width
= 1;
684 panic("Error: data width %u is invalid!\n",
685 pdimm
[0].data_width
);
689 if (pdimm
[0].n_ranks
!= 0) {
690 if (pdimm
[0].primary_sdram_width
== 64)
691 popts
->data_bus_width
= 0;
692 else if (pdimm
[0].primary_sdram_width
== 32)
693 popts
->data_bus_width
= 1;
694 else if (pdimm
[0].primary_sdram_width
== 16)
695 popts
->data_bus_width
= 2;
697 panic("Error: primary sdram width %u is invalid!\n",
698 pdimm
[0].primary_sdram_width
);
703 popts
->x4_en
= (pdimm
[0].device_width
== 4) ? 1 : 0;
705 /* Choose burst length. */
706 #if defined(CONFIG_SYS_FSL_DDR3)
707 #if defined(CONFIG_E500MC)
708 popts
->otf_burst_chop_en
= 0; /* on-the-fly burst chop disable */
709 popts
->burst_length
= DDR_BL8
; /* Fixed 8-beat burst len */
711 if ((popts
->data_bus_width
== 1) || (popts
->data_bus_width
== 2)) {
712 /* 32-bit or 16-bit bus */
713 popts
->otf_burst_chop_en
= 0;
714 popts
->burst_length
= DDR_BL8
;
716 popts
->otf_burst_chop_en
= 1; /* on-the-fly burst chop */
717 popts
->burst_length
= DDR_OTF
; /* on-the-fly BC4 and BL8 */
721 popts
->burst_length
= DDR_BL4
; /* has to be 4 for DDR2 */
724 /* Choose ddr controller address mirror mode */
725 #if defined(CONFIG_SYS_FSL_DDR3)
726 popts
->mirrored_dimm
= pdimm
[0].mirrored_dimm
;
729 /* Global Timing Parameters. */
730 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
732 /* Pick a caslat override. */
733 popts
->cas_latency_override
= 0;
734 popts
->cas_latency_override_value
= 3;
735 if (popts
->cas_latency_override
) {
736 debug("using caslat override value = %u\n",
737 popts
->cas_latency_override_value
);
740 /* Decide whether to use the computed derated latency */
741 popts
->use_derated_caslat
= 0;
743 /* Choose an additive latency. */
744 popts
->additive_latency_override
= 0;
745 popts
->additive_latency_override_value
= 3;
746 if (popts
->additive_latency_override
) {
747 debug("using additive latency override value = %u\n",
748 popts
->additive_latency_override_value
);
754 * Factors to consider for 2T_EN:
755 * - number of DIMMs installed
756 * - number of components, number of active ranks
757 * - how much time you want to spend playing around
760 popts
->threet_en
= 0;
762 /* for RDIMM, address parity enable */
766 * BSTTOPRE precharge interval
768 * Set this to 0 for global auto precharge
770 * FIXME: Should this be configured in picoseconds?
771 * Why it should be in ps: better understanding of this
772 * relative to actual DRAM timing parameters such as tRAS.
773 * e.g. tRAS(min) = 40 ns
775 popts
->bstopre
= 0x100;
777 /* Minimum CKE pulse width -- tCKE(MIN) */
778 popts
->tcke_clock_pulse_width_ps
779 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR
);
782 * Window for four activates -- tFAW
784 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
785 * FIXME: varies depending upon number of column addresses or data
786 * FIXME: width, was considering looking at pdimm->primary_sdram_width
788 #if defined(CONFIG_SYS_FSL_DDR1)
789 popts
->tfaw_window_four_activates_ps
= mclk_to_picos(1);
791 #elif defined(CONFIG_SYS_FSL_DDR2)
793 * x4/x8; some datasheets have 35000
794 * x16 wide columns only? Use 50000?
796 popts
->tfaw_window_four_activates_ps
= 37500;
798 #elif defined(CONFIG_SYS_FSL_DDR3)
799 popts
->tfaw_window_four_activates_ps
= pdimm
[0].tfaw_ps
;
803 #if defined(CONFIG_SYS_FSL_DDR3)
805 * due to ddr3 dimm is fly-by topology
806 * we suggest to enable write leveling to
807 * meet the tQDSS under different loading.
811 popts
->wrlvl_override
= 0;
815 * Check interleaving configuration from environment.
816 * Please refer to doc/README.fsl-ddr for the detail.
818 * If memory controller interleaving is enabled, then the data
819 * bus widths must be programmed identically for all memory controllers.
821 * Attempt to set all controllers to the same chip select
822 * interleaving mode. It will do a best effort to get the
823 * requested ranks interleaved together such that the result
824 * should be a subset of the requested configuration.
826 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
827 * with 256 Byte is enabled.
829 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
830 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf
))
831 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
836 if (pdimm
[0].n_ranks
== 0) {
837 printf("There is no rank on CS0 for controller %d.\n", ctrl_num
);
838 popts
->memctl_interleaving
= 0;
841 popts
->memctl_interleaving
= 1;
842 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
843 popts
->memctl_interleaving_mode
= FSL_DDR_256B_INTERLEAVING
;
844 popts
->memctl_interleaving
= 1;
845 debug("256 Byte interleaving\n");
849 * test null first. if CONFIG_HWCONFIG is not defined
850 * hwconfig_arg_cmp returns non-zero
852 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
854 popts
->memctl_interleaving
= 0;
855 debug("memory controller interleaving disabled.\n");
856 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
859 popts
->memctl_interleaving_mode
=
860 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
861 0 : FSL_DDR_CACHE_LINE_INTERLEAVING
;
862 popts
->memctl_interleaving
=
863 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
865 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
868 popts
->memctl_interleaving_mode
=
869 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
870 0 : FSL_DDR_PAGE_INTERLEAVING
;
871 popts
->memctl_interleaving
=
872 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
874 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
877 popts
->memctl_interleaving_mode
=
878 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
879 0 : FSL_DDR_BANK_INTERLEAVING
;
880 popts
->memctl_interleaving
=
881 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
883 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
886 popts
->memctl_interleaving_mode
=
887 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
888 0 : FSL_DDR_SUPERBANK_INTERLEAVING
;
889 popts
->memctl_interleaving
=
890 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
892 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
893 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
896 popts
->memctl_interleaving_mode
=
897 FSL_DDR_3WAY_1KB_INTERLEAVING
;
898 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
901 popts
->memctl_interleaving_mode
=
902 FSL_DDR_3WAY_4KB_INTERLEAVING
;
903 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
906 popts
->memctl_interleaving_mode
=
907 FSL_DDR_3WAY_8KB_INTERLEAVING
;
908 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
909 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
912 popts
->memctl_interleaving_mode
=
913 FSL_DDR_4WAY_1KB_INTERLEAVING
;
914 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
917 popts
->memctl_interleaving_mode
=
918 FSL_DDR_4WAY_4KB_INTERLEAVING
;
919 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
922 popts
->memctl_interleaving_mode
=
923 FSL_DDR_4WAY_8KB_INTERLEAVING
;
926 popts
->memctl_interleaving
= 0;
927 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
931 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf
)) &&
932 (CONFIG_CHIP_SELECTS_PER_CTRL
> 1)) {
933 /* test null first. if CONFIG_HWCONFIG is not defined,
934 * hwconfig_subarg_cmp_f returns non-zero */
935 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
937 debug("bank interleaving disabled.\n");
938 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
940 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1
;
941 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
943 popts
->ba_intlv_ctl
= FSL_DDR_CS2_CS3
;
944 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
945 "cs0_cs1_and_cs2_cs3", buf
))
946 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_AND_CS2_CS3
;
947 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
948 "cs0_cs1_cs2_cs3", buf
))
949 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_CS2_CS3
;
950 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
952 popts
->ba_intlv_ctl
= auto_bank_intlv(pdimm
);
954 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
955 switch (popts
->ba_intlv_ctl
& FSL_DDR_CS0_CS1_CS2_CS3
) {
956 case FSL_DDR_CS0_CS1_CS2_CS3
:
957 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
958 if (pdimm
[0].n_ranks
< 4) {
959 popts
->ba_intlv_ctl
= 0;
960 printf("Not enough bank(chip-select) for "
961 "CS0+CS1+CS2+CS3 on controller %d, "
962 "interleaving disabled!\n", ctrl_num
);
964 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
965 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
966 if (pdimm
[0].n_ranks
== 4)
969 if ((pdimm
[0].n_ranks
< 2) && (pdimm
[1].n_ranks
< 2)) {
970 popts
->ba_intlv_ctl
= 0;
971 printf("Not enough bank(chip-select) for "
972 "CS0+CS1+CS2+CS3 on controller %d, "
973 "interleaving disabled!\n", ctrl_num
);
975 if (pdimm
[0].capacity
!= pdimm
[1].capacity
) {
976 popts
->ba_intlv_ctl
= 0;
977 printf("Not identical DIMM size for "
978 "CS0+CS1+CS2+CS3 on controller %d, "
979 "interleaving disabled!\n", ctrl_num
);
983 case FSL_DDR_CS0_CS1
:
984 if (pdimm
[0].n_ranks
< 2) {
985 popts
->ba_intlv_ctl
= 0;
986 printf("Not enough bank(chip-select) for "
987 "CS0+CS1 on controller %d, "
988 "interleaving disabled!\n", ctrl_num
);
991 case FSL_DDR_CS2_CS3
:
992 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
993 if (pdimm
[0].n_ranks
< 4) {
994 popts
->ba_intlv_ctl
= 0;
995 printf("Not enough bank(chip-select) for CS2+CS3 "
996 "on controller %d, interleaving disabled!\n", ctrl_num
);
998 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
999 if (pdimm
[1].n_ranks
< 2) {
1000 popts
->ba_intlv_ctl
= 0;
1001 printf("Not enough bank(chip-select) for CS2+CS3 "
1002 "on controller %d, interleaving disabled!\n", ctrl_num
);
1006 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
1007 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1008 if (pdimm
[0].n_ranks
< 4) {
1009 popts
->ba_intlv_ctl
= 0;
1010 printf("Not enough bank(CS) for CS0+CS1 and "
1011 "CS2+CS3 on controller %d, "
1012 "interleaving disabled!\n", ctrl_num
);
1014 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1015 if ((pdimm
[0].n_ranks
< 2) || (pdimm
[1].n_ranks
< 2)) {
1016 popts
->ba_intlv_ctl
= 0;
1017 printf("Not enough bank(CS) for CS0+CS1 and "
1018 "CS2+CS3 on controller %d, "
1019 "interleaving disabled!\n", ctrl_num
);
1024 popts
->ba_intlv_ctl
= 0;
1029 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf
)) {
1030 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf
))
1031 popts
->addr_hash
= 0;
1032 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1034 popts
->addr_hash
= 1;
1037 if (pdimm
[0].n_ranks
== 4)
1038 popts
->quad_rank_present
= 1;
1040 ddr_freq
= get_ddr_freq(0) / 1000000;
1041 if (popts
->registered_dimm_en
) {
1042 popts
->rcw_override
= 1;
1043 popts
->rcw_1
= 0x000a5a00;
1044 if (ddr_freq
<= 800)
1045 popts
->rcw_2
= 0x00000000;
1046 else if (ddr_freq
<= 1066)
1047 popts
->rcw_2
= 0x00100000;
1048 else if (ddr_freq
<= 1333)
1049 popts
->rcw_2
= 0x00200000;
1051 popts
->rcw_2
= 0x00300000;
1054 fsl_ddr_board_options(popts
, pdimm
, ctrl_num
);
1059 void check_interleaving_options(fsl_ddr_info_t
*pinfo
)
1061 int i
, j
, k
, check_n_ranks
, intlv_invalid
= 0;
1062 unsigned int check_intlv
, check_n_row_addr
, check_n_col_addr
;
1063 unsigned long long check_rank_density
;
1064 struct dimm_params_s
*dimm
;
1066 * Check if all controllers are configured for memory
1067 * controller interleaving. Identical dimms are recommended. At least
1068 * the size, row and col address should be checked.
1071 check_n_ranks
= pinfo
->dimm_params
[0][0].n_ranks
;
1072 check_rank_density
= pinfo
->dimm_params
[0][0].rank_density
;
1073 check_n_row_addr
= pinfo
->dimm_params
[0][0].n_row_addr
;
1074 check_n_col_addr
= pinfo
->dimm_params
[0][0].n_col_addr
;
1075 check_intlv
= pinfo
->memctl_opts
[0].memctl_interleaving_mode
;
1076 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++) {
1077 dimm
= &pinfo
->dimm_params
[i
][0];
1078 if (!pinfo
->memctl_opts
[i
].memctl_interleaving
) {
1080 } else if (((check_rank_density
!= dimm
->rank_density
) ||
1081 (check_n_ranks
!= dimm
->n_ranks
) ||
1082 (check_n_row_addr
!= dimm
->n_row_addr
) ||
1083 (check_n_col_addr
!= dimm
->n_col_addr
) ||
1085 pinfo
->memctl_opts
[i
].memctl_interleaving_mode
))){
1093 if (intlv_invalid
) {
1094 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++)
1095 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1096 printf("Not all DIMMs are identical. "
1097 "Memory controller interleaving disabled.\n");
1099 switch (check_intlv
) {
1100 case FSL_DDR_256B_INTERLEAVING
:
1101 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
1102 case FSL_DDR_PAGE_INTERLEAVING
:
1103 case FSL_DDR_BANK_INTERLEAVING
:
1104 case FSL_DDR_SUPERBANK_INTERLEAVING
:
1105 if (3 == CONFIG_NUM_DDR_CONTROLLERS
)
1108 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1110 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
1111 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
1112 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
1113 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
1114 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
1115 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
1117 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1120 debug("%d of %d controllers are interleaving.\n", j
, k
);
1121 if (j
&& (j
!= k
)) {
1122 for (i
= 0; i
< CONFIG_NUM_DDR_CONTROLLERS
; i
++)
1123 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1124 printf("Not all controllers have compatible "
1125 "interleaving mode. All disabled.\n");
1128 debug("Checking interleaving options completed\n");
1131 int fsl_use_spd(void)
1135 #ifdef CONFIG_DDR_SPD
1136 char buffer
[HWCONFIG_BUFFER_SIZE
];
1140 * Extract hwconfig from environment since we have not properly setup
1141 * the environment but need it for ddr config params
1143 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
1146 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1147 if (hwconfig_sub_f("fsl_ddr", "sdram", buf
)) {
1148 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf
))
1150 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",