2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/fsl_law.h>
14 #include <fsl_immap.h>
16 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
18 #include <asm/arch/clock.h>
21 /* To avoid 64-bit full-divides, we factor this here */
22 #define ULL_2E12 2000000000000ULL
23 #define UL_5POW12 244140625UL
24 #define UL_2POW13 (1UL << 13)
26 #define ULL_8FS 0xFFFFFFFFULL
28 u32
fsl_ddr_get_version(unsigned int ctrl_num
)
30 struct ccsr_ddr __iomem
*ddr
;
31 u32 ver_major_minor_errata
;
35 ddr
= (void *)CONFIG_SYS_FSL_DDR_ADDR
;
37 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
39 ddr
= (void *)CONFIG_SYS_FSL_DDR2_ADDR
;
42 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
44 ddr
= (void *)CONFIG_SYS_FSL_DDR3_ADDR
;
47 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
49 ddr
= (void *)CONFIG_SYS_FSL_DDR4_ADDR
;
53 printf("%s unexpected ctrl_num = %u\n", __func__
, ctrl_num
);
56 ver_major_minor_errata
= (ddr_in32(&ddr
->ip_rev1
) & 0xFFFF) << 8;
57 ver_major_minor_errata
|= (ddr_in32(&ddr
->ip_rev2
) & 0xFF00) >> 8;
59 return ver_major_minor_errata
;
63 * Round up mclk_ps to nearest 1 ps in memory controller code
64 * if the error is 0.5ps or more.
66 * If an imprecise data rate is too high due to rounding error
67 * propagation, compute a suitably rounded mclk_ps to compute
68 * a working memory controller configuration.
70 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num
)
72 unsigned int data_rate
= get_ddr_freq(ctrl_num
);
75 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
76 unsigned long long rem
, mclk_ps
= ULL_2E12
;
78 /* Now perform the big divide, the result fits in 32-bits */
79 rem
= do_div(mclk_ps
, data_rate
);
80 result
= (rem
>= (data_rate
>> 1)) ? mclk_ps
+ 1 : mclk_ps
;
85 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
86 unsigned int picos_to_mclk(const unsigned int ctrl_num
, unsigned int picos
)
88 unsigned long long clks
, clks_rem
;
89 unsigned long data_rate
= get_ddr_freq(ctrl_num
);
91 /* Short circuit for zero picos */
95 /* First multiply the time by the data rate (32x32 => 64) */
96 clks
= picos
* (unsigned long long)data_rate
;
98 * Now divide by 5^12 and track the 32-bit remainder, then divide
99 * by 2*(2^12) using shifts (and updating the remainder).
101 clks_rem
= do_div(clks
, UL_5POW12
);
102 clks_rem
+= (clks
& (UL_2POW13
-1)) * UL_5POW12
;
105 /* If we had a remainder greater than the 1ps error, then round up */
106 if (clks_rem
> data_rate
)
109 /* Clamp to the maximum representable value */
112 return (unsigned int) clks
;
115 unsigned int mclk_to_picos(const unsigned int ctrl_num
, unsigned int mclk
)
117 return get_memory_clk_period_ps(ctrl_num
) * mclk
;
122 __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
123 unsigned int law_memctl
,
124 unsigned int ctrl_num
)
126 unsigned long long base
= memctl_common_params
->base_address
;
127 unsigned long long size
= memctl_common_params
->total_mem
;
130 * If no DIMMs on this controller, do not proceed any further.
132 if (!memctl_common_params
->ndimms_present
) {
136 #if !defined(CONFIG_PHYS_64BIT)
137 if (base
>= CONFIG_MAX_MEM_MAPPED
)
139 if ((base
+ size
) >= CONFIG_MAX_MEM_MAPPED
)
140 size
= CONFIG_MAX_MEM_MAPPED
- base
;
142 if (set_ddr_laws(base
, size
, law_memctl
) < 0) {
143 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__
, ctrl_num
,
147 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
148 base
, size
, law_memctl
);
151 __attribute__((weak
, alias("__fsl_ddr_set_lawbar"))) void
152 fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
153 unsigned int memctl_interleaved
,
154 unsigned int ctrl_num
);
157 void fsl_ddr_set_intl3r(const unsigned int granule_size
)
160 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
161 *mcintl3r
= 0x80000000 | (granule_size
& 0x1f);
162 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size
);
166 u32
fsl_ddr_get_intl3r(void)
170 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
176 void print_ddr_info(unsigned int start_ctrl
)
178 struct ccsr_ddr __iomem
*ddr
=
179 (struct ccsr_ddr __iomem
*)(CONFIG_SYS_FSL_DDR_ADDR
);
181 #if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
182 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
184 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
185 uint32_t cs0_config
= ddr_in32(&ddr
->cs0_config
);
187 uint32_t sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
190 #if CONFIG_SYS_NUM_DDR_CTLRS >= 2
191 if ((!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) ||
193 ddr
= (void __iomem
*)CONFIG_SYS_FSL_DDR2_ADDR
;
194 sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
197 #if CONFIG_SYS_NUM_DDR_CTLRS >= 3
198 if ((!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) ||
200 ddr
= (void __iomem
*)CONFIG_SYS_FSL_DDR3_ADDR
;
201 sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
205 if (!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) {
206 puts(" (DDR not enabled)\n");
211 switch ((sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
) >>
212 SDRAM_CFG_SDRAM_TYPE_SHIFT
) {
213 case SDRAM_TYPE_DDR1
:
216 case SDRAM_TYPE_DDR2
:
219 case SDRAM_TYPE_DDR3
:
222 case SDRAM_TYPE_DDR4
:
230 if (sdram_cfg
& SDRAM_CFG_32_BE
)
232 else if (sdram_cfg
& SDRAM_CFG_16_BE
)
237 /* Calculate CAS latency based on timing cfg values */
238 cas_lat
= ((ddr_in32(&ddr
->timing_cfg_1
) >> 16) & 0xf);
239 if (fsl_ddr_get_version(0) <= 0x40400)
243 cas_lat
+= ((ddr_in32(&ddr
->timing_cfg_3
) >> 12) & 3) << 4;
244 printf(", CL=%d", cas_lat
>> 1);
248 if (sdram_cfg
& SDRAM_CFG_ECC_EN
)
253 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
255 if (*mcintl3r
& 0x80000000) {
257 puts(" DDR Controller Interleaving Mode: ");
258 switch (*mcintl3r
& 0x1f) {
259 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
262 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
265 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
269 puts("3-way UNKNOWN");
275 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
276 if ((cs0_config
& 0x20000000) && (start_ctrl
== 0)) {
278 puts(" DDR Controller Interleaving Mode: ");
280 switch ((cs0_config
>> 24) & 0xf) {
281 case FSL_DDR_256B_INTERLEAVING
:
284 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
287 case FSL_DDR_PAGE_INTERLEAVING
:
290 case FSL_DDR_BANK_INTERLEAVING
:
293 case FSL_DDR_SUPERBANK_INTERLEAVING
:
303 if ((sdram_cfg
>> 8) & 0x7f) {
305 puts(" DDR Chip-Select Interleaving Mode: ");
306 switch(sdram_cfg
>> 8 & 0x7f) {
307 case FSL_DDR_CS0_CS1_CS2_CS3
:
308 puts("CS0+CS1+CS2+CS3");
310 case FSL_DDR_CS0_CS1
:
313 case FSL_DDR_CS2_CS3
:
316 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
317 puts("CS0+CS1 and CS2+CS3");
326 void __weak
detail_board_ddr_info(void)
331 void board_add_ram_info(int use_default
)
333 detail_board_ddr_info();
336 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
337 #define DDRC_DEBUG20_INIT_DONE 0x80000000
338 #define DDRC_DEBUG2_RF 0x00000040
339 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl
,
340 unsigned int last_ctrl
)
344 u32 ddrc_debug2
[CONFIG_SYS_NUM_DDR_CTLRS
] = {};
345 u32
*ddrc_debug2_p
[CONFIG_SYS_NUM_DDR_CTLRS
] = {};
346 struct ccsr_ddr __iomem
*ddr
;
348 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
351 ddr
= (void *)CONFIG_SYS_FSL_DDR_ADDR
;
353 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
355 ddr
= (void *)CONFIG_SYS_FSL_DDR2_ADDR
;
358 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
360 ddr
= (void *)CONFIG_SYS_FSL_DDR3_ADDR
;
363 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
365 ddr
= (void *)CONFIG_SYS_FSL_DDR4_ADDR
;
369 printf("%s unexpected ctrl = %u\n", __func__
, i
);
372 ddrc_debug20
= ddr_in32(&ddr
->debug
[19]);
373 ddrc_debug2_p
[i
] = &ddr
->debug
[1];
374 while (!(ddrc_debug20
& DDRC_DEBUG20_INIT_DONE
)) {
375 /* keep polling until DDRC init is done */
377 ddrc_debug20
= ddr_in32(&ddr
->debug
[19]);
379 ddrc_debug2
[i
] = ddr_in32(&ddr
->debug
[1]) | DDRC_DEBUG2_RF
;
383 * This is put together to make sure the refresh reqeusts are sent
384 * closely to each other.
386 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
387 ddr_out32(ddrc_debug2_p
[i
], ddrc_debug2
[i
]);
389 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
391 void remove_unused_controllers(fsl_ddr_info_t
*info
)
393 #ifdef CONFIG_FSL_LSCH3
396 void *hnf_sam_ctrl
= (void *)(CCI_HN_F_0_BASE
+ CCN_HN_F_SAM_CTL
);
397 bool ddr0_used
= false;
398 bool ddr1_used
= false;
400 for (i
= 0; i
< 8; i
++) {
401 nodeid
= in_le64(hnf_sam_ctrl
) & CCN_HN_F_SAM_NODEID_MASK
;
402 if (nodeid
== CCN_HN_F_SAM_NODEID_DDR0
) {
404 } else if (nodeid
== CCN_HN_F_SAM_NODEID_DDR1
) {
407 printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
410 hnf_sam_ctrl
+= (CCI_HN_F_1_BASE
- CCI_HN_F_0_BASE
);
412 if (!ddr0_used
&& !ddr1_used
) {
413 printf("Invalid configuration in HN-F SAM control\n");
417 if (!ddr0_used
&& info
->first_ctrl
== 0) {
418 info
->first_ctrl
= 1;
420 debug("First DDR controller disabled\n");
424 if (!ddr1_used
&& info
->first_ctrl
+ info
->num_ctrls
> 1) {
426 debug("Second DDR controller disabled\n");