2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "ddr3_init.h"
17 u8 debug_pbs
= DEBUG_LEVEL_ERROR
;
20 * API to change flags outside of the lib
23 /* Debug flags for other Training modules */
24 u8 debug_training_static
= DEBUG_LEVEL_ERROR
;
25 u8 debug_training
= DEBUG_LEVEL_ERROR
;
26 u8 debug_leveling
= DEBUG_LEVEL_ERROR
;
27 u8 debug_centralization
= DEBUG_LEVEL_ERROR
;
28 u8 debug_training_ip
= DEBUG_LEVEL_ERROR
;
29 u8 debug_training_bist
= DEBUG_LEVEL_ERROR
;
30 u8 debug_training_hw_alg
= DEBUG_LEVEL_ERROR
;
31 u8 debug_training_access
= DEBUG_LEVEL_ERROR
;
32 u8 debug_training_a38x
= DEBUG_LEVEL_ERROR
;
34 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block
, u8 level
)
37 case DEBUG_BLOCK_STATIC
:
38 debug_training_static
= level
;
40 case DEBUG_BLOCK_TRAINING_MAIN
:
41 debug_training
= level
;
43 case DEBUG_BLOCK_LEVELING
:
44 debug_leveling
= level
;
46 case DEBUG_BLOCK_CENTRALIZATION
:
47 debug_centralization
= level
;
53 debug_training_hw_alg
= level
;
55 case DEBUG_BLOCK_DEVICE
:
56 debug_training_a38x
= level
;
58 case DEBUG_BLOCK_ACCESS
:
59 debug_training_access
= level
;
61 case DEBUG_STAGES_REG_DUMP
:
62 if (level
== DEBUG_LEVEL_TRACE
)
69 debug_training_static
= level
;
70 debug_training
= level
;
71 debug_leveling
= level
;
72 debug_centralization
= level
;
74 debug_training_hw_alg
= level
;
75 debug_training_access
= level
;
76 debug_training_a38x
= level
;
80 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block
, u8 level
)
86 struct hws_tip_config_func_db config_func_info
[HWS_MAX_DEVICE_NUM
];
87 u8 is_default_centralization
= 0;
88 u8 is_tune_result
= 0;
89 u8 is_validate_window_per_if
= 0;
90 u8 is_validate_window_per_pup
= 0;
92 u32 is_bist_reset_bit
= 1;
93 static struct hws_xsb_info xsb_info
[HWS_MAX_DEVICE_NUM
];
96 * Dump Dunit & Phy registers
98 int ddr3_tip_reg_dump(u32 dev_num
)
100 u32 if_id
, reg_addr
, data_value
, bus_id
;
101 u32 read_data
[MAX_INTERFACE_NUM
];
102 struct hws_topology_map
*tm
= ddr3_get_topology_map();
104 printf("-- dunit registers --\n");
105 for (reg_addr
= 0x1400; reg_addr
< 0x19f0; reg_addr
+= 4) {
106 printf("0x%x ", reg_addr
);
107 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
108 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
109 CHECK_STATUS(ddr3_tip_if_read
110 (dev_num
, ACCESS_TYPE_UNICAST
,
111 if_id
, reg_addr
, read_data
,
113 printf("0x%x ", read_data
[if_id
]);
118 printf("-- Phy registers --\n");
119 for (reg_addr
= 0; reg_addr
<= 0xff; reg_addr
++) {
120 printf("0x%x ", reg_addr
);
121 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
122 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
124 bus_id
< tm
->num_of_bus_per_interface
;
126 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
127 CHECK_STATUS(ddr3_tip_bus_read
129 ACCESS_TYPE_UNICAST
, bus_id
,
130 DDR_PHY_DATA
, reg_addr
,
132 printf("0x%x ", data_value
);
135 bus_id
< tm
->num_of_bus_per_interface
;
137 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
138 CHECK_STATUS(ddr3_tip_bus_read
140 ACCESS_TYPE_UNICAST
, bus_id
,
141 DDR_PHY_CONTROL
, reg_addr
,
143 printf("0x%x ", data_value
);
153 * Register access func registration
155 int ddr3_tip_init_config_func(u32 dev_num
,
156 struct hws_tip_config_func_db
*config_func
)
158 if (config_func
== NULL
)
161 memcpy(&config_func_info
[dev_num
], config_func
,
162 sizeof(struct hws_tip_config_func_db
));
168 * Get training result info pointer
170 enum hws_result
*ddr3_tip_get_result_ptr(u32 stage
)
172 return training_result
[stage
];
178 int ddr3_tip_get_device_info(u32 dev_num
, struct ddr3_device_info
*info_ptr
)
180 if (config_func_info
[dev_num
].tip_get_device_info_func
!= NULL
) {
181 return config_func_info
[dev_num
].
182 tip_get_device_info_func((u8
) dev_num
, info_ptr
);
188 #ifndef EXCLUDE_SWITCH_DEBUG
190 * Convert freq to character string
192 static char *convert_freq(enum hws_ddr_freq freq
)
195 case DDR_FREQ_LOW_FREQ
:
196 return "DDR_FREQ_LOW_FREQ";
229 return "DDR_FREQ_360";
232 return "DDR_FREQ_1000";
234 return "Unknown Frequency";
239 * Convert device ID to character string
241 static char *convert_dev_id(u32 dev_id
)
254 return "Unknown Device";
259 * Convert device ID to character string
261 static char *convert_mem_size(u32 dev_id
)
276 return "wrong mem size";
280 int print_device_info(u8 dev_num
)
282 struct ddr3_device_info info_ptr
;
283 struct hws_topology_map
*tm
= ddr3_get_topology_map();
285 CHECK_STATUS(ddr3_tip_get_device_info(dev_num
, &info_ptr
));
286 printf("=== DDR setup START===\n");
287 printf("\tDevice ID: %s\n", convert_dev_id(info_ptr
.device_id
));
288 printf("\tDDR3 CK delay: %d\n", info_ptr
.ck_delay
);
290 printf("=== DDR setup END===\n");
295 void hws_ddr3_tip_sweep_test(int enable
)
298 is_validate_window_per_if
= 1;
299 is_validate_window_per_pup
= 1;
300 debug_training
= DEBUG_LEVEL_TRACE
;
302 is_validate_window_per_if
= 0;
303 is_validate_window_per_pup
= 0;
308 char *ddr3_tip_convert_tune_result(enum hws_result tune_result
)
310 switch (tune_result
) {
316 return "NOT COMPLETED";
325 int ddr3_tip_print_log(u32 dev_num
, u32 mem_addr
)
328 struct hws_topology_map
*tm
= ddr3_get_topology_map();
332 #ifndef EXCLUDE_SWITCH_DEBUG
333 if ((is_validate_window_per_if
!= 0) ||
334 (is_validate_window_per_pup
!= 0)) {
336 enum hws_ddr_freq freq
;
338 freq
= tm
->interface_params
[first_active_if
].memory_freq
;
340 is_pup_log
= (is_validate_window_per_pup
!= 0) ? 1 : 0;
341 printf("===VALIDATE WINDOW LOG START===\n");
342 printf("DDR Frequency: %s ======\n", convert_freq(freq
));
343 /* print sweep windows */
344 ddr3_tip_run_sweep_test(dev_num
, sweep_cnt
, 1, is_pup_log
);
345 ddr3_tip_run_sweep_test(dev_num
, sweep_cnt
, 0, is_pup_log
);
346 ddr3_tip_print_all_pbs_result(dev_num
);
347 ddr3_tip_print_wl_supp_result(dev_num
);
348 printf("===VALIDATE WINDOW LOG END ===\n");
349 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num
));
350 ddr3_tip_reg_dump(dev_num
);
354 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
355 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
357 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
358 ("IF %d Status:\n", if_id
));
360 if (mask_tune_func
& INIT_CONTROLLER_MASK_BIT
) {
361 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
362 ("\tInit Controller: %s\n",
363 ddr3_tip_convert_tune_result
364 (training_result
[INIT_CONTROLLER
]
367 if (mask_tune_func
& SET_LOW_FREQ_MASK_BIT
) {
368 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
369 ("\tLow freq Config: %s\n",
370 ddr3_tip_convert_tune_result
371 (training_result
[SET_LOW_FREQ
]
374 if (mask_tune_func
& LOAD_PATTERN_MASK_BIT
) {
375 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
376 ("\tLoad Pattern: %s\n",
377 ddr3_tip_convert_tune_result
378 (training_result
[LOAD_PATTERN
]
381 if (mask_tune_func
& SET_MEDIUM_FREQ_MASK_BIT
) {
382 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
383 ("\tMedium freq Config: %s\n",
384 ddr3_tip_convert_tune_result
385 (training_result
[SET_MEDIUM_FREQ
]
388 if (mask_tune_func
& WRITE_LEVELING_MASK_BIT
) {
389 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
391 ddr3_tip_convert_tune_result
392 (training_result
[WRITE_LEVELING
]
395 if (mask_tune_func
& LOAD_PATTERN_2_MASK_BIT
) {
396 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
397 ("\tLoad Pattern: %s\n",
398 ddr3_tip_convert_tune_result
399 (training_result
[LOAD_PATTERN_2
]
402 if (mask_tune_func
& READ_LEVELING_MASK_BIT
) {
403 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
405 ddr3_tip_convert_tune_result
406 (training_result
[READ_LEVELING
]
409 if (mask_tune_func
& WRITE_LEVELING_SUPP_MASK_BIT
) {
410 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
412 ddr3_tip_convert_tune_result
413 (training_result
[WRITE_LEVELING_SUPP
]
416 if (mask_tune_func
& PBS_RX_MASK_BIT
) {
417 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
419 ddr3_tip_convert_tune_result
420 (training_result
[PBS_RX
]
423 if (mask_tune_func
& PBS_TX_MASK_BIT
) {
424 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
426 ddr3_tip_convert_tune_result
427 (training_result
[PBS_TX
]
430 if (mask_tune_func
& SET_TARGET_FREQ_MASK_BIT
) {
431 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
432 ("\tTarget freq Config: %s\n",
433 ddr3_tip_convert_tune_result
434 (training_result
[SET_TARGET_FREQ
]
437 if (mask_tune_func
& WRITE_LEVELING_TF_MASK_BIT
) {
438 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
440 ddr3_tip_convert_tune_result
441 (training_result
[WRITE_LEVELING_TF
]
444 if (mask_tune_func
& READ_LEVELING_TF_MASK_BIT
) {
445 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
447 ddr3_tip_convert_tune_result
448 (training_result
[READ_LEVELING_TF
]
451 if (mask_tune_func
& WRITE_LEVELING_SUPP_TF_MASK_BIT
) {
452 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
453 ("\tWL TF Supp: %s\n",
454 ddr3_tip_convert_tune_result
456 [WRITE_LEVELING_SUPP_TF
]
459 if (mask_tune_func
& CENTRALIZATION_RX_MASK_BIT
) {
460 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
462 ddr3_tip_convert_tune_result
463 (training_result
[CENTRALIZATION_RX
]
466 if (mask_tune_func
& VREF_CALIBRATION_MASK_BIT
) {
467 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
468 ("\tVREF_CALIBRATION: %s\n",
469 ddr3_tip_convert_tune_result
470 (training_result
[VREF_CALIBRATION
]
473 if (mask_tune_func
& CENTRALIZATION_TX_MASK_BIT
) {
474 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
476 ddr3_tip_convert_tune_result
477 (training_result
[CENTRALIZATION_TX
]
486 * Print stability log info
488 int ddr3_tip_print_stability_log(u32 dev_num
)
490 u8 if_id
= 0, csindex
= 0, bus_id
= 0, idx
= 0;
492 u32 read_data
[MAX_INTERFACE_NUM
];
493 u32 max_cs
= hws_ddr3_tip_max_cs_get();
494 struct hws_topology_map
*tm
= ddr3_get_topology_map();
497 for (if_id
= 0; if_id
< MAX_INTERFACE_NUM
; if_id
++) {
498 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
499 printf("Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,");
500 for (csindex
= 0; csindex
< max_cs
; csindex
++) {
501 printf("CS%d , ", csindex
);
503 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
504 printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
506 for (idx
= 0; idx
< 11; idx
++)
507 printf("PBSTx-Pad%d,", idx
);
509 for (idx
= 0; idx
< 11; idx
++)
510 printf("PBSRx-Pad%d,", idx
);
516 for (if_id
= 0; if_id
< MAX_INTERFACE_NUM
; if_id
++) {
517 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
519 printf("Data: %d,%d,", if_id
,
520 (config_func_info
[dev_num
].tip_get_temperature
!= NULL
)
521 ? (config_func_info
[dev_num
].
522 tip_get_temperature(dev_num
)) : (0));
524 CHECK_STATUS(ddr3_tip_if_read
525 (dev_num
, ACCESS_TYPE_UNICAST
, if_id
, 0x14c8,
526 read_data
, MASK_ALL_BITS
));
527 printf("%d,%d,", ((read_data
[if_id
] & 0x3f0) >> 4),
528 ((read_data
[if_id
] & 0xfc00) >> 10));
529 CHECK_STATUS(ddr3_tip_if_read
530 (dev_num
, ACCESS_TYPE_UNICAST
, if_id
, 0x17c8,
531 read_data
, MASK_ALL_BITS
));
532 printf("%d,%d,", ((read_data
[if_id
] & 0x3f0) >> 4),
533 ((read_data
[if_id
] & 0xfc00) >> 10));
534 CHECK_STATUS(ddr3_tip_if_read
535 (dev_num
, ACCESS_TYPE_UNICAST
, if_id
, 0x1dc8,
536 read_data
, MASK_ALL_BITS
));
537 printf("%d,%d,", ((read_data
[if_id
] & 0x3f0000) >> 16),
538 ((read_data
[if_id
] & 0xfc00000) >> 22));
540 for (csindex
= 0; csindex
< max_cs
; csindex
++) {
541 printf("CS%d , ", csindex
);
542 for (bus_id
= 0; bus_id
< MAX_BUS_NUM
; bus_id
++) {
544 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
545 ddr3_tip_bus_read(dev_num
, if_id
,
547 bus_id
, DDR_PHY_DATA
,
548 RESULT_DB_PHY_REG_ADDR
+
550 printf("%d,%d,", (reg_data
& 0x1f),
551 ((reg_data
& 0x3e0) >> 5));
553 ddr3_tip_bus_read(dev_num
, if_id
,
555 bus_id
, DDR_PHY_DATA
,
557 csindex
* 4, ®_data
);
560 ((reg_data
& 0x1c0) >> 6) * 32,
562 (reg_data
& 0x1c0) >> 6);
564 CHECK_STATUS(ddr3_tip_if_read
565 (dev_num
, ACCESS_TYPE_UNICAST
,
567 READ_DATA_SAMPLE_DELAY
,
568 read_data
, MASK_ALL_BITS
));
571 (0xf << (4 * csindex
))) >>
573 ddr3_tip_bus_read(dev_num
, if_id
,
574 ACCESS_TYPE_UNICAST
, bus_id
,
576 RL_PHY_REG
+ csindex
* 4,
578 printf("%d,%d,%d,%d,",
580 ((reg_data
& 0x1c0) >> 6) * 32 +
581 read_data
[if_id
] * 64,
583 ((reg_data
& 0x1c0) >> 6),
586 ddr3_tip_bus_read(dev_num
, if_id
,
587 ACCESS_TYPE_UNICAST
, bus_id
,
589 WRITE_CENTRALIZATION_PHY_REG
590 + csindex
* 4, ®_data
);
591 printf("%d,", (reg_data
& 0x3f));
592 ddr3_tip_bus_read(dev_num
, if_id
,
593 ACCESS_TYPE_UNICAST
, bus_id
,
595 READ_CENTRALIZATION_PHY_REG
596 + csindex
* 4, ®_data
);
597 printf("%d,", (reg_data
& 0x1f));
599 ddr3_tip_bus_read(dev_num
, if_id
,
600 ACCESS_TYPE_UNICAST
, bus_id
,
604 printf("%d,", (reg_data
& 0x7));
606 /* Need to add the Read Function from device */
609 for (idx
= 0; idx
< 11; idx
++) {
610 ddr3_tip_bus_read(dev_num
, if_id
,
612 bus_id
, DDR_PHY_DATA
,
616 printf("%d,", (reg_data
& 0x3f));
619 for (idx
= 0; idx
< 11; idx
++) {
620 ddr3_tip_bus_read(dev_num
, if_id
,
622 bus_id
, DDR_PHY_DATA
,
626 printf("%d,", (reg_data
& 0x3f));
629 for (idx
= 0; idx
< 11; idx
++) {
630 ddr3_tip_bus_read(dev_num
, if_id
,
632 bus_id
, DDR_PHY_DATA
,
636 printf("%d,", (reg_data
& 0x3f));
647 * Register XSB information
649 int ddr3_tip_register_xsb_info(u32 dev_num
, struct hws_xsb_info
*xsb_info_table
)
651 memcpy(&xsb_info
[dev_num
], xsb_info_table
, sizeof(struct hws_xsb_info
));
658 int read_adll_value(u32 pup_values
[MAX_INTERFACE_NUM
* MAX_BUS_NUM
],
659 int reg_addr
, u32 mask
)
662 u32 if_id
= 0, bus_id
= 0;
664 struct hws_topology_map
*tm
= ddr3_get_topology_map();
667 * multi CS support - reg_addr is calucalated in calling function
670 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
671 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
672 for (bus_id
= 0; bus_id
< tm
->num_of_bus_per_interface
;
674 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
675 CHECK_STATUS(ddr3_tip_bus_read(dev_num
, if_id
,
678 DDR_PHY_DATA
, reg_addr
,
681 tm
->num_of_bus_per_interface
+ bus_id
] =
692 int write_adll_value(u32 pup_values
[MAX_INTERFACE_NUM
* MAX_BUS_NUM
],
695 u32 if_id
= 0, bus_id
= 0;
696 u32 dev_num
= 0, data
;
697 struct hws_topology_map
*tm
= ddr3_get_topology_map();
700 * multi CS support - reg_addr is calucalated in calling function
703 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
704 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
705 for (bus_id
= 0; bus_id
< tm
->num_of_bus_per_interface
;
707 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_id
);
708 data
= pup_values
[if_id
*
709 tm
->num_of_bus_per_interface
+
711 CHECK_STATUS(ddr3_tip_bus_write(dev_num
,
715 bus_id
, DDR_PHY_DATA
,
723 #ifndef EXCLUDE_SWITCH_DEBUG
724 u32 rl_version
= 1; /* 0 - old RL machine */
725 struct hws_tip_config_func_db config_func_info
[HWS_MAX_DEVICE_NUM
];
726 u32 start_xsb_offset
= 0;
729 u8 is_dfs_disabled
= 0;
730 u32 default_centrlization_value
= 0x12;
732 u32 activate_select_before_run_alg
= 1, activate_deselect_after_run_alg
= 1,
733 rl_test
= 0, reset_read_fifo
= 0;
735 u32 ctrl_sweepres
[ADLL_LENGTH
][MAX_INTERFACE_NUM
][MAX_BUS_NUM
];
736 u32 ctrl_adll
[MAX_CS_NUM
* MAX_INTERFACE_NUM
* MAX_BUS_NUM
];
738 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
741 u32 xsb_test_table
[][8] = {
742 {0x00000000, 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555,
743 0x66666666, 0x77777777},
744 {0x88888888, 0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd,
745 0xeeeeeeee, 0xffffffff},
746 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
747 0x00000000, 0xffffffff},
748 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
749 0x00000000, 0xffffffff},
750 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
751 0x00000000, 0xffffffff},
752 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
753 0x00000000, 0xffffffff},
754 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
755 0xffffffff, 0xffffffff},
756 {0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
757 0x00000000, 0x00000000},
758 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
759 0xffffffff, 0xffffffff}
762 static int ddr3_tip_access_atr(u32 dev_num
, u32 flag_id
, u32 value
, u32
**ptr
);
764 int ddr3_tip_print_adll(void)
766 u32 bus_cnt
= 0, if_id
, data_p1
, data_p2
, ui_data3
, dev_num
= 0;
767 struct hws_topology_map
*tm
= ddr3_get_topology_map();
769 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
770 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
771 for (bus_cnt
= 0; bus_cnt
< GET_TOPOLOGY_NUM_OF_BUSES();
773 VALIDATE_ACTIVE(tm
->bus_act_mask
, bus_cnt
);
774 CHECK_STATUS(ddr3_tip_bus_read
776 ACCESS_TYPE_UNICAST
, bus_cnt
,
777 DDR_PHY_DATA
, 0x1, &data_p1
));
778 CHECK_STATUS(ddr3_tip_bus_read
779 (dev_num
, if_id
, ACCESS_TYPE_UNICAST
,
780 bus_cnt
, DDR_PHY_DATA
, 0x2, &data_p2
));
781 CHECK_STATUS(ddr3_tip_bus_read
782 (dev_num
, if_id
, ACCESS_TYPE_UNICAST
,
783 bus_cnt
, DDR_PHY_DATA
, 0x3, &ui_data3
));
784 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE
,
785 (" IF %d bus_cnt %d phy_reg_1_data 0x%x phy_reg_2_data 0x%x phy_reg_3_data 0x%x\n",
786 if_id
, bus_cnt
, data_p1
, data_p2
,
795 * Set attribute value
797 int ddr3_tip_set_atr(u32 dev_num
, u32 flag_id
, u32 value
)
800 u32
*ptr_flag
= NULL
;
802 ret
= ddr3_tip_access_atr(dev_num
, flag_id
, value
, &ptr_flag
);
803 if (ptr_flag
!= NULL
) {
804 printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x (was 0x%x)\n",
805 flag_id
, value
, *ptr_flag
);
808 printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x\n",
818 static int ddr3_tip_access_atr(u32 dev_num
, u32 flag_id
, u32 value
, u32
**ptr
)
820 u32 tmp_val
= 0, if_id
= 0, pup_id
= 0;
821 struct hws_topology_map
*tm
= ddr3_get_topology_map();
828 *ptr
= (u32
*)&(tm
->if_act_mask
);
832 *ptr
= (u32
*)&mask_tune_func
;
836 *ptr
= (u32
*)&low_freq
;
840 *ptr
= (u32
*)&medium_freq
;
844 *ptr
= (u32
*)&generic_init_controller
;
848 *ptr
= (u32
*)&rl_version
;
852 *ptr
= (u32
*)&start_xsb_offset
;
856 *ptr
= (u32
*)&is_rl_old
;
860 *ptr
= (u32
*)&is_freq_old
;
864 *ptr
= (u32
*)&is_dfs_disabled
;
868 *ptr
= (u32
*)&is_pll_before_init
;
872 *ptr
= (u32
*)&is_adll_calib_before_init
;
874 #ifdef STATIC_ALGO_SUPPORT
876 *ptr
= (u32
*)&(silicon_delay
[0]);
880 *ptr
= (u32
*)&wl_debug_delay
;
884 *ptr
= (u32
*)&is_tune_result
;
888 *ptr
= (u32
*)&is_validate_window_per_if
;
892 *ptr
= (u32
*)&is_validate_window_per_pup
;
896 *ptr
= (u32
*)&sweep_cnt
;
900 *ptr
= (u32
*)&is_bist_reset_bit
;
904 *ptr
= (u32
*)&is_dfs_in_init
;
908 *ptr
= (u32
*)&p_finger
;
912 *ptr
= (u32
*)&n_finger
;
916 *ptr
= (u32
*)&init_freq
;
920 *ptr
= (u32
*)&(freq_val
[DDR_FREQ_LOW_FREQ
]);
924 *ptr
= (u32
*)&start_pattern
;
928 *ptr
= (u32
*)&end_pattern
;
932 *ptr
= (u32
*)&phy_reg0_val
;
936 *ptr
= (u32
*)&phy_reg1_val
;
940 *ptr
= (u32
*)&phy_reg2_val
;
944 *ptr
= (u32
*)&phy_reg3_val
;
948 *ptr
= (u32
*)&sweep_pattern
;
952 *ptr
= (u32
*)&is_rzq6
;
956 *ptr
= (u32
*)&znri_data_phy_val
;
960 *ptr
= (u32
*)&zpri_data_phy_val
;
964 *ptr
= (u32
*)&finger_test
;
968 *ptr
= (u32
*)&n_finger_start
;
972 *ptr
= (u32
*)&n_finger_end
;
976 *ptr
= (u32
*)&p_finger_start
;
980 *ptr
= (u32
*)&p_finger_end
;
984 *ptr
= (u32
*)&p_finger_step
;
988 *ptr
= (u32
*)&n_finger_step
;
992 *ptr
= (u32
*)&znri_ctrl_phy_val
;
996 *ptr
= (u32
*)&zpri_ctrl_phy_val
;
1000 *ptr
= (u32
*)&is_reg_dump
;
1004 *ptr
= (u32
*)&vref
;
1008 *ptr
= (u32
*)&mode2_t
;
1012 *ptr
= (u32
*)&xsb_validate_type
;
1016 *ptr
= (u32
*)&xsb_validation_base_address
;
1020 *ptr
= (u32
*)&activate_select_before_run_alg
;
1024 *ptr
= (u32
*)&activate_deselect_after_run_alg
;
1028 *ptr
= (u32
*)&odt_additional
;
1032 *ptr
= (u32
*)&debug_mode
;
1036 *ptr
= (u32
*)&pbs_pattern
;
1040 *ptr
= (u32
*)&delay_enable
;
1044 *ptr
= (u32
*)&ck_delay
;
1048 *ptr
= (u32
*)&ck_delay_16
;
1052 *ptr
= (u32
*)&ca_delay
;
1056 *ptr
= (u32
*)&debug_dunit
;
1060 debug_acc
= (int)value
;
1064 debug_training
= (u8
)value
;
1068 debug_training_bist
= (u8
)value
;
1072 debug_centralization
= (u8
)value
;
1076 debug_training_ip
= (u8
)value
;
1080 debug_leveling
= (u8
)value
;
1084 debug_pbs
= (u8
)value
;
1088 debug_training_static
= (u8
)value
;
1092 debug_training_access
= (u8
)value
;
1096 *ptr
= &start_pattern
;
1100 *ptr
= &end_pattern
;
1104 if ((flag_id
>= 0x200) && (flag_id
< 0x210)) {
1105 if_id
= flag_id
- 0x200;
1106 *ptr
= (u32
*)&(tm
->interface_params
1107 [if_id
].memory_freq
);
1108 } else if ((flag_id
>= 0x210) && (flag_id
< 0x220)) {
1109 if_id
= flag_id
- 0x210;
1110 *ptr
= (u32
*)&(tm
->interface_params
1111 [if_id
].speed_bin_index
);
1112 } else if ((flag_id
>= 0x220) && (flag_id
< 0x230)) {
1113 if_id
= flag_id
- 0x220;
1114 *ptr
= (u32
*)&(tm
->interface_params
1116 } else if ((flag_id
>= 0x230) && (flag_id
< 0x240)) {
1117 if_id
= flag_id
- 0x230;
1118 *ptr
= (u32
*)&(tm
->interface_params
1119 [if_id
].memory_size
);
1120 } else if ((flag_id
>= 0x240) && (flag_id
< 0x250)) {
1121 if_id
= flag_id
- 0x240;
1122 *ptr
= (u32
*)&(tm
->interface_params
1124 } else if ((flag_id
>= 0x250) && (flag_id
< 0x260)) {
1125 if_id
= flag_id
- 0x250;
1126 *ptr
= (u32
*)&(tm
->interface_params
1128 } else if ((flag_id
>= 0x270) && (flag_id
< 0x2cf)) {
1129 if_id
= (flag_id
- 0x270) / MAX_BUS_NUM
;
1130 pup_id
= (flag_id
- 0x270) % MAX_BUS_NUM
;
1131 *ptr
= (u32
*)&(tm
->interface_params
[if_id
].
1132 as_bus_params
[pup_id
].is_ck_swap
);
1133 } else if ((flag_id
>= 0x2d0) && (flag_id
< 0x32f)) {
1134 if_id
= (flag_id
- 0x2d0) / MAX_BUS_NUM
;
1135 pup_id
= (flag_id
- 0x2d0) % MAX_BUS_NUM
;
1136 *ptr
= (u32
*)&(tm
->interface_params
[if_id
].
1137 as_bus_params
[pup_id
].is_dqs_swap
);
1138 } else if ((flag_id
>= 0x330) && (flag_id
< 0x38f)) {
1139 if_id
= (flag_id
- 0x330) / MAX_BUS_NUM
;
1140 pup_id
= (flag_id
- 0x330) % MAX_BUS_NUM
;
1141 *ptr
= (u32
*)&(tm
->interface_params
[if_id
].
1142 as_bus_params
[pup_id
].cs_bitmask
);
1143 } else if ((flag_id
>= 0x390) && (flag_id
< 0x3ef)) {
1144 if_id
= (flag_id
- 0x390) / MAX_BUS_NUM
;
1145 pup_id
= (flag_id
- 0x390) % MAX_BUS_NUM
;
1146 *ptr
= (u32
*)&(tm
->interface_params
1147 [if_id
].as_bus_params
1148 [pup_id
].mirror_enable_bitmask
);
1149 } else if ((flag_id
>= 0x500) && (flag_id
<= 0x50f)) {
1150 tmp_val
= flag_id
- 0x320;
1151 *ptr
= (u32
*)&(clamp_tbl
[tmp_val
]);
1153 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
,
1154 ("flag_id out of boundary %d\n",
1156 return MV_BAD_PARAM
;
1163 #ifndef EXCLUDE_SWITCH_DEBUG
1167 int print_adll(u32 dev_num
, u32 adll
[MAX_INTERFACE_NUM
* MAX_BUS_NUM
])
1170 struct hws_topology_map
*tm
= ddr3_get_topology_map();
1174 for (j
= 0; j
< tm
->num_of_bus_per_interface
; j
++) {
1175 VALIDATE_ACTIVE(tm
->bus_act_mask
, j
);
1176 for (i
= 0; i
< MAX_INTERFACE_NUM
; i
++) {
1178 adll
[i
* tm
->num_of_bus_per_interface
+ j
]);
1187 /* byte_index - only byte 0, 1, 2, or 3, oxff - test all bytes */
1188 static u32
ddr3_tip_compare(u32 if_id
, u32
*p_src
, u32
*p_dst
,
1191 u32 burst_cnt
= 0, addr_offset
, i_id
;
1196 0xff) ? (u32
) 0xffffffff : (u32
) (0xff << (byte_index
* 8));
1197 for (burst_cnt
= 0; burst_cnt
< EXT_ACCESS_BURST_LENGTH
; burst_cnt
++) {
1198 if ((p_src
[burst_cnt
] & addr_offset
) !=
1199 (p_dst
[burst_cnt
] & addr_offset
))
1203 if (b_is_fail
== 1) {
1204 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
,
1205 ("IF %d exp: ", if_id
));
1206 for (i_id
= 0; i_id
<= MAX_INTERFACE_NUM
- 1; i_id
++) {
1207 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
,
1208 ("0x%8x ", p_src
[i_id
]));
1210 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
,
1211 ("\n_i_f %d rcv: ", if_id
));
1212 for (i_id
= 0; i_id
<= MAX_INTERFACE_NUM
- 1; i_id
++) {
1213 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
,
1214 ("(0x%8x ", p_dst
[i_id
]));
1216 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR
, ("\n "));
1222 /* test_type = 0-tx , 1-rx */
1223 int ddr3_tip_sweep_test(u32 dev_num
, u32 test_type
,
1224 u32 mem_addr
, u32 is_modify_adll
,
1225 u32 start_if
, u32 end_if
, u32 startpup
, u32 endpup
)
1227 u32 bus_cnt
= 0, adll_val
= 0, if_id
, ui_prev_adll
, ui_mask_bit
,
1228 end_adll
, start_adll
;
1230 struct hws_topology_map
*tm
= ddr3_get_topology_map();
1232 mem_addr
= mem_addr
;
1234 if (test_type
== 0) {
1238 end_adll
= ui_mask_bit
;
1243 end_adll
= ui_mask_bit
;
1246 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
1247 ("==============================\n"));
1248 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
,
1249 ("Test type %d (0-tx, 1-rx)\n", test_type
));
1251 for (if_id
= start_if
; if_id
<= end_if
; if_id
++) {
1252 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
1253 for (bus_cnt
= startpup
; bus_cnt
< endpup
; bus_cnt
++) {
1254 CHECK_STATUS(ddr3_tip_bus_read
1255 (dev_num
, if_id
, ACCESS_TYPE_UNICAST
,
1256 bus_cnt
, DDR_PHY_DATA
, reg_addr
,
1259 for (adll_val
= start_adll
; adll_val
<= end_adll
;
1261 if (is_modify_adll
== 1) {
1262 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1264 ACCESS_TYPE_UNICAST
,
1266 DDR_PHY_DATA
, reg_addr
,
1267 adll_val
, ui_mask_bit
));
1270 if (is_modify_adll
== 1) {
1271 CHECK_STATUS(ddr3_tip_bus_write
1272 (dev_num
, ACCESS_TYPE_UNICAST
,
1273 if_id
, ACCESS_TYPE_UNICAST
,
1274 bus_cnt
, DDR_PHY_DATA
, reg_addr
,
1277 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
, ("\n"));
1279 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO
, ("\n"));
1285 #ifndef EXCLUDE_SWITCH_DEBUG
1289 int ddr3_tip_run_sweep_test(int dev_num
, u32 repeat_num
, u32 direction
,
1292 u32 pup
= 0, start_pup
= 0, end_pup
= 0;
1294 u32 res
[MAX_INTERFACE_NUM
] = { 0 };
1297 int reg
= (direction
== 0) ? WRITE_CENTRALIZATION_PHY_REG
:
1298 READ_CENTRALIZATION_PHY_REG
;
1299 enum hws_access_type pup_access
;
1301 u32 max_cs
= hws_ddr3_tip_max_cs_get();
1302 struct hws_topology_map
*tm
= ddr3_get_topology_map();
1304 repeat_num
= repeat_num
;
1309 end_pup
= tm
->num_of_bus_per_interface
- 1;
1310 pup_access
= ACCESS_TYPE_UNICAST
;
1314 pup_access
= ACCESS_TYPE_MULTICAST
;
1317 for (cs
= 0; cs
< max_cs
; cs
++) {
1318 for (adll
= 0; adll
< ADLL_LENGTH
; adll
++) {
1320 if_id
<= MAX_INTERFACE_NUM
- 1;
1325 for (pup
= start_pup
; pup
<= end_pup
; pup
++) {
1326 ctrl_sweepres
[adll
][if_id
][pup
] =
1332 for (adll
= 0; adll
< (MAX_INTERFACE_NUM
* MAX_BUS_NUM
); adll
++)
1333 ctrl_adll
[adll
] = 0;
1334 /* Save DQS value(after algorithm run) */
1335 read_adll_value(ctrl_adll
,
1336 (reg
+ (cs
* CS_REGISTER_ADDR_OFFSET
)),
1340 * Sweep ADLL from 0:31 on all I/F on all Pup and perform
1341 * BIST on each stage.
1343 for (pup
= start_pup
; pup
<= end_pup
; pup
++) {
1344 for (adll
= 0; adll
< ADLL_LENGTH
; adll
++) {
1346 (direction
== 0) ? (adll
* 2) : adll
;
1347 CHECK_STATUS(ddr3_tip_bus_write
1348 (dev_num
, ACCESS_TYPE_MULTICAST
, 0,
1349 pup_access
, pup
, DDR_PHY_DATA
,
1350 reg
+ CS_REG_VALUE(cs
),
1352 hws_ddr3_run_bist(dev_num
, sweep_pattern
, res
,
1354 /* ddr3_tip_reset_fifo_ptr(dev_num); */
1356 if_id
<= MAX_INTERFACE_NUM
- 1;
1361 ctrl_sweepres
[adll
][if_id
][pup
]
1367 ACCESS_TYPE_UNICAST
,
1369 ACCESS_TYPE_UNICAST
,
1372 reg
+ CS_REG_VALUE(cs
),
1375 tm
->num_of_bus_per_interface
1381 printf("Final, CS %d,%s, Sweep, Result, Adll,", cs
,
1382 ((direction
== 0) ? "TX" : "RX"));
1383 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
1384 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
1386 for (pup
= start_pup
; pup
<= end_pup
; pup
++) {
1387 VALIDATE_ACTIVE(tm
->bus_act_mask
, pup
);
1388 printf("I/F%d-PHY%d , ", if_id
, pup
);
1391 printf("I/F%d , ", if_id
);
1396 for (adll
= 0; adll
< ADLL_LENGTH
; adll
++) {
1397 adll_value
= (direction
== 0) ? (adll
* 2) : adll
;
1398 printf("Final,%s, Sweep, Result, %d ,",
1399 ((direction
== 0) ? "TX" : "RX"), adll_value
);
1402 if_id
<= MAX_INTERFACE_NUM
- 1;
1404 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
1405 for (pup
= start_pup
; pup
<= end_pup
; pup
++) {
1407 ctrl_sweepres
[adll
][if_id
]
1415 * Write back to the phy the Rx DQS value, we store in
1418 write_adll_value(ctrl_adll
,
1419 (reg
+ cs
* CS_REGISTER_ADDR_OFFSET
));
1420 /* print adll results */
1421 read_adll_value(ctrl_adll
, (reg
+ cs
* CS_REGISTER_ADDR_OFFSET
),
1423 printf("%s, DQS, ADLL,,,", (direction
== 0) ? "Tx" : "Rx");
1424 print_adll(dev_num
, ctrl_adll
);
1426 ddr3_tip_reset_fifo_ptr(dev_num
);
1431 void print_topology(struct hws_topology_map
*topology_db
)
1435 printf("\tinterface_mask: 0x%x\n", topology_db
->if_act_mask
);
1436 printf("\tNum Bus: %d\n", topology_db
->num_of_bus_per_interface
);
1437 printf("\tbus_act_mask: 0x%x\n", topology_db
->bus_act_mask
);
1439 for (ui
= 0; ui
< MAX_INTERFACE_NUM
; ui
++) {
1440 VALIDATE_ACTIVE(topology_db
->if_act_mask
, ui
);
1441 printf("\n\tInterface ID: %d\n", ui
);
1442 printf("\t\tDDR Frequency: %s\n",
1443 convert_freq(topology_db
->
1444 interface_params
[ui
].memory_freq
));
1445 printf("\t\tSpeed_bin: %d\n",
1446 topology_db
->interface_params
[ui
].speed_bin_index
);
1447 printf("\t\tBus_width: %d\n",
1448 (4 << topology_db
->interface_params
[ui
].bus_width
));
1449 printf("\t\tMem_size: %s\n",
1450 convert_mem_size(topology_db
->
1451 interface_params
[ui
].memory_size
));
1452 printf("\t\tCAS-WL: %d\n",
1453 topology_db
->interface_params
[ui
].cas_wl
);
1454 printf("\t\tCAS-L: %d\n",
1455 topology_db
->interface_params
[ui
].cas_l
);
1456 printf("\t\tTemperature: %d\n",
1457 topology_db
->interface_params
[ui
].interface_temp
);
1459 for (uj
= 0; uj
< 4; uj
++) {
1460 printf("\t\tBus %d parameters- CS Mask: 0x%x\t", uj
,
1461 topology_db
->interface_params
[ui
].
1462 as_bus_params
[uj
].cs_bitmask
);
1463 printf("Mirror: 0x%x\t",
1464 topology_db
->interface_params
[ui
].
1465 as_bus_params
[uj
].mirror_enable_bitmask
);
1466 printf("DQS Swap is %s \t",
1468 interface_params
[ui
].as_bus_params
[uj
].
1469 is_dqs_swap
== 1) ? "enabled" : "disabled");
1470 printf("Ck Swap:%s\t",
1472 interface_params
[ui
].as_bus_params
[uj
].
1473 is_ck_swap
== 1) ? "enabled" : "disabled");
1481 * Execute XSB Test transaction (rd/wr/both)
1483 int run_xsb_test(u32 dev_num
, u32 mem_addr
, u32 write_type
,
1484 u32 read_type
, u32 burst_length
)
1486 u32 seq
= 0, if_id
= 0, addr
, cnt
;
1487 int ret
= MV_OK
, ret_tmp
;
1488 u32 data_read
[MAX_INTERFACE_NUM
];
1489 struct hws_topology_map
*tm
= ddr3_get_topology_map();
1491 for (if_id
= 0; if_id
<= MAX_INTERFACE_NUM
- 1; if_id
++) {
1492 VALIDATE_ACTIVE(tm
->if_act_mask
, if_id
);
1494 for (cnt
= 0; cnt
<= burst_length
; cnt
++) {
1495 seq
= (seq
+ 1) % 8;
1496 if (write_type
!= 0) {
1497 CHECK_STATUS(ddr3_tip_ext_write
1498 (dev_num
, if_id
, addr
, 1,
1499 xsb_test_table
[seq
]));
1501 if (read_type
!= 0) {
1502 CHECK_STATUS(ddr3_tip_ext_read
1503 (dev_num
, if_id
, addr
, 1,
1506 if ((read_type
!= 0) && (write_type
!= 0)) {
1508 ddr3_tip_compare(if_id
,
1509 xsb_test_table
[seq
],
1512 addr
+= (EXT_ACCESS_BURST_LENGTH
* 4);
1513 ret
= (ret
!= MV_OK
) ? ret
: ret_tmp
;
1521 #else /*EXCLUDE_SWITCH_DEBUG */
1523 u32 rl_version
= 1; /* 0 - old RL machine */
1525 u32 start_xsb_offset
= 0;
1526 u8 cs_mask_reg
[] = {
1527 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1530 int run_xsb_test(u32 dev_num
, u32 mem_addr
, u32 write_type
,
1531 u32 read_type
, u32 burst_length
)