drivers/ddr/marvell/a38x/ddr3_topology_def.h

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef _DDR3_TOPOLOGY_DEF_H
   8 #define _DDR3_TOPOLOGY_DEF_H
   9
  10 /* TOPOLOGY */
  11
  12 enum hws_speed_bin {
  13         SPEED_BIN_DDR_800D,
  14         SPEED_BIN_DDR_800E,
  15         SPEED_BIN_DDR_1066E,
  16         SPEED_BIN_DDR_1066F,
  17         SPEED_BIN_DDR_1066G,
  18         SPEED_BIN_DDR_1333F,
  19         SPEED_BIN_DDR_1333G,
  20         SPEED_BIN_DDR_1333H,
  21         SPEED_BIN_DDR_1333J,
  22         SPEED_BIN_DDR_1600G,
  23         SPEED_BIN_DDR_1600H,
  24         SPEED_BIN_DDR_1600J,
  25         SPEED_BIN_DDR_1600K,
  26         SPEED_BIN_DDR_1866J,
  27         SPEED_BIN_DDR_1866K,
  28         SPEED_BIN_DDR_1866L,
  29         SPEED_BIN_DDR_1866M,
  30         SPEED_BIN_DDR_2133K,
  31         SPEED_BIN_DDR_2133L,
  32         SPEED_BIN_DDR_2133M,
  33         SPEED_BIN_DDR_2133N,
  34
  35         SPEED_BIN_DDR_1333H_EXT,
  36         SPEED_BIN_DDR_1600K_EXT,
  37         SPEED_BIN_DDR_1866M_EXT
  38 };
  39
  40 enum hws_ddr_freq {
  41         DDR_FREQ_LOW_FREQ,
  42         DDR_FREQ_400,
  43         DDR_FREQ_533,
  44         DDR_FREQ_667,
  45         DDR_FREQ_800,
  46         DDR_FREQ_933,
  47         DDR_FREQ_1066,
  48         DDR_FREQ_311,
  49         DDR_FREQ_333,
  50         DDR_FREQ_467,
  51         DDR_FREQ_850,
  52         DDR_FREQ_600,
  53         DDR_FREQ_300,
  54         DDR_FREQ_900,
  55         DDR_FREQ_360,
  56         DDR_FREQ_1000,
  57         DDR_FREQ_LIMIT
  58 };
  59
  60 enum speed_bin_table_elements {
  61         SPEED_BIN_TRCD,
  62         SPEED_BIN_TRP,
  63         SPEED_BIN_TRAS,
  64         SPEED_BIN_TRC,
  65         SPEED_BIN_TRRD1K,
  66         SPEED_BIN_TRRD2K,
  67         SPEED_BIN_TPD,
  68         SPEED_BIN_TFAW1K,
  69         SPEED_BIN_TFAW2K,
  70         SPEED_BIN_TWTR,
  71         SPEED_BIN_TRTP,
  72         SPEED_BIN_TWR,
  73         SPEED_BIN_TMOD
  74 };
  75
  76 #endif /* _DDR3_TOPOLOGY_DEF_H */