drivers/ddr/marvell/a38x/ddr3_training_ip_def.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #ifndef _DDR3_TRAINING_IP_DEF_H
   7 #define _DDR3_TRAINING_IP_DEF_H
   8
   9 #include "silicon_if.h"
  10
  11 #define PATTERN_55                      0x55555555
  12 #define PATTERN_AA                      0xaaaaaaaa
  13 #define PATTERN_80                      0x80808080
  14 #define PATTERN_20                      0x20202020
  15 #define PATTERN_01                      0x01010101
  16 #define PATTERN_FF                      0xffffffff
  17 #define PATTERN_00                      0x00000000
  18
  19 /* 16bit bus width patterns */
  20 #define PATTERN_55AA                    0x5555aaaa
  21 #define PATTERN_00FF                    0x0000ffff
  22 #define PATTERN_0080                    0x00008080
  23
  24 #define INVALID_VALUE                   0xffffffff
  25 #define MAX_NUM_OF_DUNITS               32
  26 /*
  27  * length *2 = length in words of pattern, first low address,
  28  * second high address
  29  */
  30 #define TEST_PATTERN_LENGTH             4
  31 #define KILLER_PATTERN_DQ_NUMBER        8
  32 #define SSO_DQ_NUMBER                   4
  33 #define PATTERN_MAXIMUM_LENGTH          64
  34 #define ADLL_TX_LENGTH                  64
  35 #define ADLL_RX_LENGTH                  32
  36
  37 #define PARAM_NOT_CARE                  0
  38
  39 #define READ_LEVELING_PHY_OFFSET        2
  40 #define WRITE_LEVELING_PHY_OFFSET       0
  41
  42 #define MASK_ALL_BITS                   0xffffffff
  43
  44 #define CS_BIT_MASK                     0xf
  45
  46 /* DFX access */
  47 #define BROADCAST_ID                    28
  48 #define MULTICAST_ID                    29
  49
  50 #define XSB_BASE_ADDR                   0x00004000
  51 #define XSB_CTRL_0_REG                  0x00000000
  52 #define XSB_CTRL_1_REG                  0x00000004
  53 #define XSB_CMD_REG                     0x00000008
  54 #define XSB_ADDRESS_REG                 0x0000000c
  55 #define XSB_DATA_REG                    0x00000010
  56 #define PIPE_ENABLE_ADDR                0x000f8000
  57 #define ENABLE_DDR_TUNING_ADDR          0x000f829c
  58
  59 #define CLIENT_BASE_ADDR                0x00002000
  60 #define CLIENT_CTRL_REG                 0x00000000
  61
  62 #define TARGET_INT                      0x1801
  63 #define TARGET_EXT                      0x180e
  64 #define BYTE_EN                         0
  65 #define CMD_READ                        0
  66 #define CMD_WRITE                       1
  67
  68 #define INTERNAL_ACCESS_PORT            1
  69 #define EXECUTING                       1
  70 #define ACCESS_EXT                      1
  71 #define CS2_EXIST_BIT                   2
  72 #define TRAINING_ID                     0xf
  73 #define EXT_TRAINING_ID                 1
  74 #define EXT_MODE                        0x4
  75
  76 #define GET_RESULT_STATE(res)           (res)
  77 #define SET_RESULT_STATE(res, state)    (res = state)
  78
  79 #define _1K                             0x00000400
  80 #define _4K                             0x00001000
  81 #define _8K                             0x00002000
  82 #define _16K                            0x00004000
  83 #define _32K                            0x00008000
  84 #define _64K                            0x00010000
  85 #define _128K                           0x00020000
  86 #define _256K                           0x00040000
  87 #define _512K                           0x00080000
  88
  89 #define _1M                             0x00100000
  90 #define _2M                             0x00200000
  91 #define _4M                             0x00400000
  92 #define _8M                             0x00800000
  93 #define _16M                            0x01000000
  94 #define _32M                            0x02000000
  95 #define _64M                            0x04000000
  96 #define _128M                           0x08000000
  97 #define _256M                           0x10000000
  98 #define _512M                           0x20000000
  99
 100 #define _1G                             0x40000000
 101 #define _2G                             0x80000000
 102
 103 #define ADDR_SIZE_512MB                 0x04000000
 104 #define ADDR_SIZE_1GB                   0x08000000
 105 #define ADDR_SIZE_2GB                   0x10000000
 106 #define ADDR_SIZE_4GB                   0x20000000
 107 #define ADDR_SIZE_8GB                   0x40000000
 108
 109 enum hws_edge_compare {
 110         EDGE_PF,
 111         EDGE_FP,
 112         EDGE_FPF,
 113         EDGE_PFP
 114 };
 115
 116 enum hws_control_element {
 117         HWS_CONTROL_ELEMENT_ADLL,               /* per bit 1 edge */
 118         HWS_CONTROL_ELEMENT_DQ_SKEW,
 119         HWS_CONTROL_ELEMENT_DQS_SKEW
 120 };
 121
 122 enum hws_search_dir {
 123         HWS_LOW2HIGH,
 124         HWS_HIGH2LOW,
 125         HWS_SEARCH_DIR_LIMIT
 126 };
 127
 128 enum hws_page_size {
 129         PAGE_SIZE_1K,
 130         PAGE_SIZE_2K
 131 };
 132
 133 enum hws_operation {
 134         OPERATION_READ = 0,
 135         OPERATION_WRITE = 1
 136 };
 137
 138 enum hws_training_ip_stat {
 139         HWS_TRAINING_IP_STATUS_FAIL,
 140         HWS_TRAINING_IP_STATUS_SUCCESS,
 141         HWS_TRAINING_IP_STATUS_TIMEOUT
 142 };
 143
 144 enum hws_ddr_cs {
 145         CS_SINGLE,
 146         CS_NON_SINGLE
 147 };
 148
 149 enum hws_ddr_phy {
 150         DDR_PHY_DATA = 0,
 151         DDR_PHY_CONTROL = 1
 152 };
 153
 154 enum hws_dir {
 155         OPER_WRITE,
 156         OPER_READ,
 157         OPER_WRITE_AND_READ
 158 };
 159
 160 enum hws_wl_supp {
 161         PHASE_SHIFT,
 162         CLOCK_SHIFT,
 163         ALIGN_SHIFT
 164 };
 165
 166 struct reg_data {
 167         u32 reg_addr;
 168         u32 reg_data;
 169         u32 reg_mask;
 170 };
 171
 172 #endif /* _DDR3_TRAINING_IP_DEF_H */