drivers/ddr/marvell/axp/ddr3_axp_config.h

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef __DDR3_AXP_CONFIG_H
   8 #define __DDR3_AXP_CONFIG_H
   9
  10 /*
  11  * DDR3_LOG_LEVEL Information
  12  *
  13  * Level 0: Provides an error code in a case of failure, RL, WL errors
  14  *          and other algorithm failure
  15  * Level 1: Provides the D-Unit setup (SPD/Static configuration)
  16  * Level 2: Provides the windows margin as a results of DQS centeralization
  17  * Level 3: Provides the windows margin of each DQ as a results of DQS
  18  *          centeralization
  19  */
  20 #ifdef CONFIG_DDR_LOG_LEVEL
  21 #define DDR3_LOG_LEVEL  CONFIG_DDR_LOG_LEVEL
  22 #else
  23 #define DDR3_LOG_LEVEL  0
  24 #endif
  25
  26 #define DDR3_PBS        1
  27
  28 /* This flag allows the execution of SW WL/RL upon HW failure */
  29 #define DDR3_RUN_SW_WHEN_HW_FAIL    1
  30
  31 /*
  32  * General Configurations
  33  *
  34  * The following parameters are required for proper setup:
  35  *
  36  * DDR_TARGET_FABRIC   - Set desired fabric configuration
  37  *                       (for sample@Reset fabfreq parameter)
  38  * DRAM_ECC            - Set ECC support 1/0
  39  * BUS_WIDTH           - 64/32 bit
  40  * CONFIG_SPD_EEPROM   - Enables auto detection of DIMMs and their timing values
  41  * DQS_CLK_ALIGNED     - Set this if CLK and DQS signals are aligned on board
  42  * MIXED_DIMM_STATIC   - Mixed DIMM + On board devices support (ODT registers
  43  *                       values are taken statically)
  44  * DDR3_TRAINING_DEBUG - Debug prints of internal code
  45  */
  46 #define DDR_TARGET_FABRIC                       5
  47 /* Only enable ECC if the board selects it */
  48 #ifdef CONFIG_BOARD_ECC_SUPPORT
  49 #define DRAM_ECC                                1
  50 #else
  51 #define DRAM_ECC                                0
  52 #endif
  53
  54 #ifdef CONFIG_DDR_32BIT
  55 #define BUS_WIDTH                               32
  56 #else
  57 #define BUS_WIDTH                               64
  58 #endif
  59
  60 #undef DQS_CLK_ALIGNED
  61 #undef MIXED_DIMM_STATIC
  62 #define DDR3_TRAINING_DEBUG                     0
  63 #define REG_DIMM_SKIP_WL                        0
  64
  65 /* Marvell boards specific configurations */
  66 #if defined(DB_78X60_PCAC)
  67 #undef CONFIG_SPD_EEPROM
  68 #define STATIC_TRAINING
  69 #endif
  70
  71 #if defined(DB_78X60_AMC)
  72 #undef CONFIG_SPD_EEPROM
  73 #undef  DRAM_ECC
  74 #define DRAM_ECC                                1
  75 #endif
  76
  77 #ifdef CONFIG_SPD_EEPROM
  78 /*
  79  * DIMM support parameters:
  80  * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
  81  * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
  82  * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
  83  */
  84 #define DRAM_2T                                 0x0
  85 #define DIMM_CS_BITMAP                          0xF
  86 #define DUNIT_SPD
  87 #endif
  88
  89 #ifdef DRAM_ECC
  90 /*
  91  * ECC support parameters:
  92  *
  93  * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
  94  * to configure the scrubbing area
  95  */
  96 #define TRAINING_SIZE                           0x20000
  97 #define U_BOOT_START_ADDR                       0
  98 #define U_BOOT_SCRUB_SIZE                       0x1000000 /* TRAINING_SIZE */
  99 #endif
 100
 101 /*
 102  * Registered DIMM Support - In case registered DIMM is attached,
 103  * please supply the following values:
 104  * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
 105  * Driver with Parity and Quad Chip
 106  * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
 107  * RC0: Global Features Control Word
 108  * RC1: Clock Driver Enable Control Word
 109  * RC2: Timing Control Word
 110  * RC3-RC5 - taken from SPD
 111  * RC8: Additional IBT Setting Control Word
 112  * RC9: Power Saving Settings Control Word
 113  * RC10: Encoding for RDIMM Operating Speed
 114  * RC11: Operating Voltage VDD and VREFCA Control Word
 115  */
 116 #define RDIMM_RC0                               0
 117 #define RDIMM_RC1                               0
 118 #define RDIMM_RC2                               0
 119 #define RDIMM_RC8                               0
 120 #define RDIMM_RC9                               0
 121 #define RDIMM_RC10                              0x2
 122 #define RDIMM_RC11                              0x0
 123
 124 #if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
 125 #define DUNIT_STATIC
 126 #endif
 127
 128 #if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
 129 /*
 130  * This flag allows the user to change the dram refresh cycle in ps,
 131  * only in case of SPD or MIX DIMM topology
 132  */
 133 #define TREFI_USER_EN
 134
 135 #ifdef TREFI_USER_EN
 136 #define TREFI_USER                              3900000
 137 #endif
 138 #endif
 139
 140 #ifdef CONFIG_SPD_EEPROM
 141 /*
 142  * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
 143  * Enables I2C auto detection different options
 144  */
 145 #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
 146     defined(CONFIG_DB_784MP_GP)
 147 #define AUTO_DETECTION_SUPPORT
 148 #endif
 149 #endif
 150
 151 #endif /* __DDR3_AXP_CONFIG_H */