drivers/dm9000x.c

   1 /*
   2   dm9000.c: Version 1.2 12/15/2003
   3
   4         A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
   5         Copyright (C) 1997  Sten Wang
   6
   7         This program is free software; you can redistribute it and/or
   8         modify it under the terms of the GNU General Public License
   9         as published by the Free Software Foundation; either version 2
  10         of the License, or (at your option) any later version.
  11
  12         This program is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17   (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  18
  19 V0.11   06/20/2001      REG_0A bit3=1, default enable BP with DA match
  20         06/22/2001      Support DM9801 progrmming
  21                         E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  22                         E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  23                 R17 = (R17 & 0xfff0) | NF + 3
  24                         E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  25                 R17 = (R17 & 0xfff0) | NF
  26
  27 v1.00                   modify by simon 2001.9.5
  28                         change for kernel 2.4.x
  29
  30 v1.1   11/09/2001       fix force mode bug
  31
  32 v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
  33                         Fixed phy reset.
  34                         Added tx/rx 32 bit mode.
  35                         Cleaned up for kernel merge.
  36
  37 --------------------------------------
  38
  39        12/15/2003       Initial port to u-boot by Sascha Hauer <saschahauer@web.de>
  40
  41 TODO: Homerun NIC and longrun NIC are not functional, only internal at the
  42       moment.
  43 */
  44
  45 #include <common.h>
  46 #include <command.h>
  47 #include <net.h>
  48 #include <asm/io.h>
  49
  50 #ifdef CONFIG_DRIVER_DM9000
  51
  52 #include "dm9000x.h"
  53
  54 /* Board/System/Debug information/definition ---------------- */
  55
  56 #define DM9801_NOISE_FLOOR      0x08
  57 #define DM9802_NOISE_FLOOR      0x05
  58
  59 /* #define CONFIG_DM9000_DEBUG */
  60
  61 #ifdef CONFIG_DM9000_DEBUG
  62 #define DM9000_DBG(fmt,args...) printf(fmt ,##args)
  63 #else                           /*  */
  64 #define DM9000_DBG(fmt,args...)
  65 #endif                          /*  */
  66 enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
  67             1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
  68             8, DM9000_1M_HPNA = 0x10
  69 };
  70 enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
  71 };
  72
  73 /* Structure/enum declaration ------------------------------- */
  74 typedef struct board_info {
  75         u32 runt_length_counter;        /* counter: RX length < 64byte */
  76         u32 long_length_counter;        /* counter: RX length > 1514byte */
  77         u32 reset_counter;      /* counter: RESET */
  78         u32 reset_tx_timeout;   /* RESET caused by TX Timeout */
  79         u32 reset_rx_status;    /* RESET caused by RX Statsus wrong */
  80         u16 tx_pkt_cnt;
  81         u16 queue_start_addr;
  82         u16 dbug_cnt;
  83         u8 phy_addr;
  84         u8 device_wait_reset;   /* device state */
  85         u8 nic_type;            /* NIC type */
  86         unsigned char srom[128];
  87 } board_info_t;
  88 board_info_t dmfe_info;
  89
  90 /* For module input parameter */
  91 static int media_mode = DM9000_AUTO;
  92 static u8 nfloor = 0;
  93
  94 /* function declaration ------------------------------------- */
  95 int eth_init(bd_t * bd);
  96 int eth_send(volatile void *, int);
  97 int eth_rx(void);
  98 void eth_halt(void);
  99 static int dm9000_probe(void);
 100 static u16 phy_read(int);
 101 static void phy_write(int, u16);
 102 static u16 read_srom_word(int);
 103 static u8 DM9000_ior(int);
 104 static void DM9000_iow(int reg, u8 value);
 105
 106 /* DM9000 network board routine ---------------------------- */
 107
 108 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
 109 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
 110 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
 111 #define DM9000_inb(r) (*(volatile u8 *)r)
 112 #define DM9000_inw(r) (*(volatile u16 *)r)
 113 #define DM9000_inl(r) (*(volatile u32 *)r)
 114
 115 #ifdef CONFIG_DM9000_DEBUG
 116 static void
 117 dump_regs(void)
 118 {
 119         DM9000_DBG("\n");
 120         DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));
 121         DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));
 122         DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));
 123         DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));
 124         DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
 125         DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));
 126         DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));
 127         DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(ISR));
 128         DM9000_DBG("\n");
 129 }
 130 #endif                          /*  */
 131
 132 /*
 133   Search DM9000 board, allocate space and register it
 134 */
 135 int
 136 dm9000_probe(void)
 137 {
 138         u32 id_val;
 139         id_val = DM9000_ior(DM9000_VIDL);
 140         id_val |= DM9000_ior(DM9000_VIDH) << 8;
 141         id_val |= DM9000_ior(DM9000_PIDL) << 16;
 142         id_val |= DM9000_ior(DM9000_PIDH) << 24;
 143         if (id_val == DM9000_ID) {
 144                 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
 145                        id_val);
 146                 return 0;
 147         } else {
 148                 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
 149                        CONFIG_DM9000_BASE, id_val);
 150                 return -1;
 151         }
 152 }
 153
 154 /* Set PHY operationg mode
 155 */
 156 static void
 157 set_PHY_mode(void)
 158 {
 159         u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
 160         if (!(media_mode & DM9000_AUTO)) {
 161                 switch (media_mode) {
 162                 case DM9000_10MHD:
 163                         phy_reg4 = 0x21;
 164                         phy_reg0 = 0x0000;
 165                         break;
 166                 case DM9000_10MFD:
 167                         phy_reg4 = 0x41;
 168                         phy_reg0 = 0x1100;
 169                         break;
 170                 case DM9000_100MHD:
 171                         phy_reg4 = 0x81;
 172                         phy_reg0 = 0x2000;
 173                         break;
 174                 case DM9000_100MFD:
 175                         phy_reg4 = 0x101;
 176                         phy_reg0 = 0x3100;
 177                         break;
 178                 }
 179                 phy_write(4, phy_reg4); /* Set PHY media mode */
 180                 phy_write(0, phy_reg0); /*  Tmp */
 181         }
 182         DM9000_iow(DM9000_GPCR, 0x01);  /* Let GPIO0 output */
 183         DM9000_iow(DM9000_GPR, 0x00);   /* Enable PHY */
 184 }
 185
 186 /*
 187         Init HomeRun DM9801
 188 */
 189 static void
 190 program_dm9801(u16 HPNA_rev)
 191 {
 192         __u16 reg16, reg17, reg24, reg25;
 193         if (!nfloor)
 194                 nfloor = DM9801_NOISE_FLOOR;
 195         reg16 = phy_read(16);
 196         reg17 = phy_read(17);
 197         reg24 = phy_read(24);
 198         reg25 = phy_read(25);
 199         switch (HPNA_rev) {
 200         case 0xb900:            /* DM9801 E3 */
 201                 reg16 |= 0x1000;
 202                 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
 203                 break;
 204         case 0xb901:            /* DM9801 E4 */
 205                 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
 206                 reg17 = (reg17 & 0xfff0) + nfloor + 3;
 207                 break;
 208         case 0xb902:            /* DM9801 E5 */
 209         case 0xb903:            /* DM9801 E6 */
 210         default:
 211                 reg16 |= 0x1000;
 212                 reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
 213                 reg17 = (reg17 & 0xfff0) + nfloor;
 214         }
 215         phy_write(16, reg16);
 216         phy_write(17, reg17);
 217         phy_write(25, reg25);
 218 }
 219
 220 /*
 221         Init LongRun DM9802
 222 */
 223 static void
 224 program_dm9802(void)
 225 {
 226         __u16 reg25;
 227         if (!nfloor)
 228                 nfloor = DM9802_NOISE_FLOOR;
 229         reg25 = phy_read(25);
 230         reg25 = (reg25 & 0xff00) + nfloor;
 231         phy_write(25, reg25);
 232 }
 233
 234 /* Identify NIC type
 235 */
 236 static void
 237 identify_nic(void)
 238 {
 239         struct board_info *db = &dmfe_info;     /* Point a board information structure */
 240         u16 phy_reg3;
 241         DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
 242         phy_reg3 = phy_read(3);
 243         switch (phy_reg3 & 0xfff0) {
 244         case 0xb900:
 245                 if (phy_read(31) == 0x4404) {
 246                         db->nic_type = HOMERUN_NIC;
 247                         program_dm9801(phy_reg3);
 248                         DM9000_DBG("found homerun NIC\n");
 249                 } else {
 250                         db->nic_type = LONGRUN_NIC;
 251                         DM9000_DBG("found longrun NIC\n");
 252                         program_dm9802();
 253                 }
 254                 break;
 255         default:
 256                 db->nic_type = FASTETHER_NIC;
 257                 break;
 258         }
 259         DM9000_iow(DM9000_NCR, 0);
 260 }
 261
 262 /* General Purpose dm9000 reset routine */
 263 static void
 264 dm9000_reset(void)
 265 {
 266         DM9000_DBG("resetting\n");
 267         DM9000_iow(DM9000_NCR, NCR_RST);
 268         udelay(1000);           /* delay 1ms */
 269 }
 270
 271 /* Initilize dm9000 board
 272 */
 273 int
 274 eth_init(bd_t * bd)
 275 {
 276         int i, oft, lnk;
 277         DM9000_DBG("eth_init()\n");
 278
 279         /* RESET device */
 280         dm9000_reset();
 281         dm9000_probe();
 282
 283         /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
 284         identify_nic();
 285
 286         /* GPIO0 on pre-activate PHY */
 287         DM9000_iow(DM9000_GPR, 0x00);   /*REG_1F bit0 activate phyxcer */
 288
 289         /* Set PHY */
 290         set_PHY_mode();
 291
 292         /* Program operating register */
 293         DM9000_iow(DM9000_NCR, 0x0);    /* only intern phy supported by now */
 294         DM9000_iow(DM9000_TCR, 0);      /* TX Polling clear */
 295         DM9000_iow(DM9000_BPTR, 0x3f);  /* Less 3Kb, 200us */
 296         DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));   /* Flow Control : High/Low Water */
 297         DM9000_iow(DM9000_FCR, 0x0);    /* SH FIXME: This looks strange! Flow Control */
 298         DM9000_iow(DM9000_SMCR, 0);     /* Special Mode */
 299         DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);   /* clear TX status */
 300         DM9000_iow(DM9000_ISR, 0x0f);   /* Clear interrupt status */
 301
 302         /* Set Node address */
 303         for (i = 0; i < 6; i++)
 304                 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
 305         printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
 306                bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
 307                bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
 308         for (i = 0, oft = 0x10; i < 6; i++, oft++)
 309                 DM9000_iow(oft, bd->bi_enetaddr[i]);
 310         for (i = 0, oft = 0x16; i < 8; i++, oft++)
 311                 DM9000_iow(oft, 0xff);
 312
 313         /* read back mac, just to be sure */
 314         for (i = 0, oft = 0x10; i < 6; i++, oft++)
 315                 DM9000_DBG("%02x:", DM9000_ior(oft));
 316         DM9000_DBG("\n");
 317
 318         /* Activate DM9000 */
 319         DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);  /* RX enable */
 320         DM9000_iow(DM9000_IMR, IMR_PAR);        /* Enable TX/RX interrupt mask */
 321         i = 0;
 322         while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
 323                 udelay(1000);
 324                 i++;
 325                 if (i == 10000) {
 326                         printf("could not establish link\n");
 327                         return 0;
 328                 }
 329         }
 330
 331         /* see what we've got */
 332         lnk = phy_read(17) >> 12;
 333         printf("operating at ");
 334         switch (lnk) {
 335         case 1:
 336                 printf("10M half duplex ");
 337                 break;
 338         case 2:
 339                 printf("10M full duplex ");
 340                 break;
 341         case 4:
 342                 printf("100M half duplex ");
 343                 break;
 344         case 8:
 345                 printf("100M full duplex ");
 346                 break;
 347         default:
 348                 printf("unknown: %d ", lnk);
 349                 break;
 350         }
 351         printf("mode\n");
 352         return 0;
 353 }
 354
 355 /*
 356   Hardware start transmission.
 357   Send a packet to media from the upper layer.
 358 */
 359 int
 360 eth_send(volatile void *packet, int length)
 361 {
 362         char *data_ptr;
 363         u32 tmplen, i;
 364         int tmo;
 365         DM9000_DBG("eth_send: length: %d\n", length);
 366         for (i = 0; i < length; i++) {
 367                 if (i % 8 == 0)
 368                         DM9000_DBG("\nSend: 02x: ", i);
 369                 DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
 370         } DM9000_DBG("\n");
 371
 372         /* Move data to DM9000 TX RAM */
 373         data_ptr = (char *) packet;
 374         DM9000_outb(DM9000_MWCMD, DM9000_IO);
 375
 376 #ifdef CONFIG_DM9000_USE_8BIT
 377         /* Byte mode */
 378         for (i = 0; i < length; i++)
 379                 DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);
 380
 381 #endif                          /*  */
 382 #ifdef CONFIG_DM9000_USE_16BIT
 383         tmplen = (length + 1) / 2;
 384         for (i = 0; i < tmplen; i++)
 385                 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
 386
 387 #endif                          /*  */
 388 #ifdef CONFIG_DM9000_USE_32BIT
 389         tmplen = (length + 3) / 4;
 390         for (i = 0; i < tmplen; i++)
 391                 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
 392
 393 #endif                          /*  */
 394
 395         /* Set TX length to DM9000 */
 396         DM9000_iow(DM9000_TXPLL, length & 0xff);
 397         DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
 398
 399         /* Issue TX polling command */
 400         DM9000_iow(DM9000_TCR, TCR_TXREQ);      /* Cleared after TX complete */
 401
 402         /* wait for end of transmission */
 403         tmo = get_timer(0) + 5 * CFG_HZ;
 404         while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
 405                 if (get_timer(0) >= tmo) {
 406                         printf("transmission timeout\n");
 407                         break;
 408                 }
 409         }
 410         DM9000_DBG("transmit done\n\n");
 411         return 0;
 412 }
 413
 414 /*
 415   Stop the interface.
 416   The interface is stopped when it is brought.
 417 */
 418 void
 419 eth_halt(void)
 420 {
 421         DM9000_DBG("eth_halt\n");
 422
 423         /* RESET devie */
 424         phy_write(0, 0x8000);   /* PHY RESET */
 425         DM9000_iow(DM9000_GPR, 0x01);   /* Power-Down PHY */
 426         DM9000_iow(DM9000_IMR, 0x80);   /* Disable all interrupt */
 427         DM9000_iow(DM9000_RCR, 0x00);   /* Disable RX */
 428 }
 429
 430 /*
 431   Received a packet and pass to upper layer
 432 */
 433 int
 434 eth_rx(void)
 435 {
 436         u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
 437         u16 RxStatus, RxLen = 0;
 438         u32 tmplen, i;
 439 #ifdef CONFIG_DM9000_USE_32BIT
 440         u32 tmpdata;
 441 #endif
 442
 443         /* Check packet ready or not */
 444         DM9000_ior(DM9000_MRCMDX);      /* Dummy read */
 445         rxbyte = DM9000_inb(DM9000_DATA);       /* Got most updated data */
 446         if (rxbyte == 0)
 447                 return 0;
 448
 449         /* Status check: this byte must be 0 or 1 */
 450         if (rxbyte > 1) {
 451                 DM9000_iow(DM9000_RCR, 0x00);   /* Stop Device */
 452                 DM9000_iow(DM9000_ISR, 0x80);   /* Stop INT request */
 453                 DM9000_DBG("rx status check: %d\n", rxbyte);
 454         }
 455         DM9000_DBG("receiving packet\n");
 456
 457         /* A packet ready now  & Get status/length */
 458         DM9000_outb(DM9000_MRCMD, DM9000_IO);
 459
 460 #ifdef CONFIG_DM9000_USE_8BIT
 461         RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
 462         RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
 463
 464 #endif                          /*  */
 465 #ifdef CONFIG_DM9000_USE_16BIT
 466         RxStatus = DM9000_inw(DM9000_DATA);
 467         RxLen = DM9000_inw(DM9000_DATA);
 468
 469 #endif                          /*  */
 470 #ifdef CONFIG_DM9000_USE_32BIT
 471         tmpdata = DM9000_inl(DM9000_DATA);
 472         RxStatus = tmpdata;
 473         RxLen = tmpdata >> 16;
 474
 475 #endif                          /*  */
 476         DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
 477
 478         /* Move data from DM9000 */
 479         /* Read received packet from RX SRAM */
 480 #ifdef CONFIG_DM9000_USE_8BIT
 481         for (i = 0; i < RxLen; i++)
 482                 rdptr[i] = DM9000_inb(DM9000_DATA);
 483
 484 #endif                          /*  */
 485 #ifdef CONFIG_DM9000_USE_16BIT
 486         tmplen = (RxLen + 1) / 2;
 487         for (i = 0; i < tmplen; i++)
 488                 ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
 489
 490 #endif                          /*  */
 491 #ifdef CONFIG_DM9000_USE_32BIT
 492         tmplen = (RxLen + 3) / 4;
 493         for (i = 0; i < tmplen; i++)
 494                 ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);
 495
 496 #endif                          /*  */
 497         if ((RxStatus & 0xbf00) || (RxLen < 0x40)
 498             || (RxLen > DM9000_PKT_MAX)) {
 499                 if (RxStatus & 0x100) {
 500                         printf("rx fifo error\n");
 501                 }
 502                 if (RxStatus & 0x200) {
 503                         printf("rx crc error\n");
 504                 }
 505                 if (RxStatus & 0x8000) {
 506                         printf("rx length error\n");
 507                 }
 508                 if (RxLen > DM9000_PKT_MAX) {
 509                         printf("rx length too big\n");
 510                         dm9000_reset();
 511                 }
 512         } else {
 513
 514                 /* Pass to upper layer */
 515                 DM9000_DBG("passing packet to upper layer\n");
 516                 NetReceive(NetRxPackets[0], RxLen);
 517                 return RxLen;
 518         }
 519         return 0;
 520 }
 521
 522 /*
 523   Read a word data from SROM
 524 */
 525 static u16
 526 read_srom_word(int offset)
 527 {
 528         DM9000_iow(DM9000_EPAR, offset);
 529         DM9000_iow(DM9000_EPCR, 0x4);
 530         udelay(200);
 531         DM9000_iow(DM9000_EPCR, 0x0);
 532         return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
 533 }
 534
 535 /*
 536    Read a byte from I/O port
 537 */
 538 static u8
 539 DM9000_ior(int reg)
 540 {
 541         DM9000_outb(reg, DM9000_IO);
 542         return DM9000_inb(DM9000_DATA);
 543 }
 544
 545 /*
 546    Write a byte to I/O port
 547 */
 548 static void
 549 DM9000_iow(int reg, u8 value)
 550 {
 551         DM9000_outb(reg, DM9000_IO);
 552         DM9000_outb(value, DM9000_DATA);
 553 }
 554
 555 /*
 556    Read a word from phyxcer
 557 */
 558 static u16
 559 phy_read(int reg)
 560 {
 561         u16 val;
 562
 563         /* Fill the phyxcer register into REG_0C */
 564         DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
 565         DM9000_iow(DM9000_EPCR, 0xc);   /* Issue phyxcer read command */
 566         udelay(100);            /* Wait read complete */
 567         DM9000_iow(DM9000_EPCR, 0x0);   /* Clear phyxcer read command */
 568         val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
 569
 570         /* The read data keeps on REG_0D & REG_0E */
 571         DM9000_DBG("phy_read(%d): %d\n", reg, val);
 572         return val;
 573 }
 574
 575 /*
 576    Write a word to phyxcer
 577 */
 578 static void
 579 phy_write(int reg, u16 value)
 580 {
 581
 582         /* Fill the phyxcer register into REG_0C */
 583         DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
 584
 585         /* Fill the written data into REG_0D & REG_0E */
 586         DM9000_iow(DM9000_EPDRL, (value & 0xff));
 587         DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
 588         DM9000_iow(DM9000_EPCR, 0xa);   /* Issue phyxcer write command */
 589         udelay(500);            /* Wait write complete */
 590         DM9000_iow(DM9000_EPCR, 0x0);   /* Clear phyxcer write command */
 591         DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value);
 592 }
 593 #endif                          /* CONFIG_DRIVER_DM9000 */