1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
6 #define pr_fmt(fmt) "udma: " fmt
11 #include <asm/cache.h>
13 #include <asm/bitops.h>
15 #include <linux/bitops.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sizes.h>
19 #include <dm/device_compat.h>
20 #include <dm/devres.h>
22 #include <dm/of_access.h>
24 #include <dma-uclass.h>
25 #include <linux/delay.h>
26 #include <linux/bitmap.h>
27 #include <linux/err.h>
28 #include <linux/printk.h>
29 #include <linux/soc/ti/k3-navss-ringacc.h>
30 #include <linux/soc/ti/cppi5.h>
31 #include <linux/soc/ti/ti-udma.h>
32 #include <linux/soc/ti/ti_sci_protocol.h>
33 #include <linux/soc/ti/cppi5.h>
35 #include "k3-udma-hwdef.h"
36 #include "k3-psil-priv.h"
38 #define K3_UDMA_MAX_RFLOWS 1024
59 static const char * const mmr_names
[] = {
61 [MMR_BCHANRT
] = "bchanrt",
62 [MMR_RCHANRT
] = "rchanrt",
63 [MMR_TCHANRT
] = "tchanrt",
64 [MMR_RCHAN
] = "rchan",
65 [MMR_TCHAN
] = "tchan",
66 [MMR_RFLOW
] = "rflow",
70 void __iomem
*reg_chan
;
74 struct k3_nav_ring
*t_ring
; /* Transmit ring */
75 struct k3_nav_ring
*tc_ring
; /* Transmit Completion ring */
76 int tflow_id
; /* applicable only for PKTDMA */
80 #define udma_bchan udma_tchan
83 void __iomem
*reg_rflow
;
85 struct k3_nav_ring
*fd_ring
; /* Free Descriptor ring */
86 struct k3_nav_ring
*r_ring
; /* Receive ring */
90 void __iomem
*reg_chan
;
96 struct udma_oes_offsets
{
97 /* K3 UDMA Output Event Offset */
100 /* BCDMA Output Event Offsets */
101 u32 bcdma_bchan_data
;
102 u32 bcdma_bchan_ring
;
103 u32 bcdma_tchan_data
;
104 u32 bcdma_tchan_ring
;
105 u32 bcdma_rchan_data
;
106 u32 bcdma_rchan_ring
;
108 /* PKTDMA Output Event Offsets */
109 u32 pktdma_tchan_flow
;
110 u32 pktdma_rchan_flow
;
113 #define UDMA_FLAG_PDMA_ACC32 BIT(0)
114 #define UDMA_FLAG_PDMA_BURST BIT(1)
115 #define UDMA_FLAG_TDTYPE BIT(2)
117 struct udma_match_data
{
118 enum k3_dma_type type
;
120 bool enable_memcpy_support
;
123 struct udma_oes_offsets oes
;
126 u32 level_start_idx
[];
138 struct udma_tisci_rm
{
139 const struct ti_sci_handle
*tisci
;
140 const struct ti_sci_rm_udmap_ops
*tisci_udmap_ops
;
143 /* tisci information for PSI-L thread pairing/unpairing */
144 const struct ti_sci_rm_psil_ops
*tisci_psil_ops
;
145 u32 tisci_navss_dev_id
;
147 struct ti_sci_resource
*rm_ranges
[RM_RANGE_LAST
];
152 void __iomem
*mmrs
[MMR_LAST
];
154 struct udma_tisci_rm tisci_rm
;
155 struct k3_nav_ringacc
*ringacc
;
165 unsigned long *bchan_map
;
166 unsigned long *tchan_map
;
167 unsigned long *rchan_map
;
168 unsigned long *rflow_map
;
169 unsigned long *rflow_map_reserved
;
170 unsigned long *tflow_map
;
172 struct udma_bchan
*bchans
;
173 struct udma_tchan
*tchans
;
174 struct udma_rchan
*rchans
;
175 struct udma_rflow
*rflows
;
177 struct udma_match_data
*match_data
;
179 struct udma_chan
*channels
;
185 struct udma_chan_config
{
186 u32 psd_size
; /* size of Protocol Specific Data */
187 u32 metadata_size
; /* (needs_epib ? 16:0) + psd_size */
188 u32 hdesc_size
; /* Size of a packet descriptor in packet mode */
189 int remote_thread_id
;
193 enum psil_endpoint_type ep_type
;
194 enum udma_tp_level channel_tpl
; /* Channel Throughput Level */
196 /* PKTDMA mapped channel */
197 int mapped_channel_id
;
198 /* PKTDMA default tflow or rflow for mapped channel */
201 enum dma_direction dir
;
203 unsigned int pkt_mode
:1; /* TR or packet */
204 unsigned int needs_epib
:1; /* EPIB is needed for the communication or not */
205 unsigned int enable_acc32
:1;
206 unsigned int enable_burst
:1;
207 unsigned int notdpkt
:1; /* Suppress sending TDC packet */
214 struct udma_bchan
*bchan
;
215 struct udma_tchan
*tchan
;
216 struct udma_rchan
*rchan
;
217 struct udma_rflow
*rflow
;
219 struct ti_udma_drv_chan_cfg_data cfg_data
;
221 u32 bcnt
; /* number of bytes completed since the start of the channel */
223 struct udma_chan_config config
;
227 struct cppi5_host_desc_t
*desc_tx
;
235 #define UDMA_CH_1000(ch) (ch * 0x1000)
236 #define UDMA_CH_100(ch) (ch * 0x100)
237 #define UDMA_CH_40(ch) (ch * 0x40)
240 #define UDMA_RX_DESC_NUM PKTBUFSRX
242 #define UDMA_RX_DESC_NUM 4
245 /* Generic register access functions */
246 static inline u32
udma_read(void __iomem
*base
, int reg
)
250 v
= __raw_readl(base
+ reg
);
251 pr_debug("READL(32): v(%08X)<--reg(%p)\n", v
, base
+ reg
);
255 static inline void udma_write(void __iomem
*base
, int reg
, u32 val
)
257 pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val
, base
+ reg
);
258 __raw_writel(val
, base
+ reg
);
261 static inline void udma_update_bits(void __iomem
*base
, int reg
,
266 orig
= udma_read(base
, reg
);
271 udma_write(base
, reg
, tmp
);
275 static inline u32
udma_tchanrt_read(struct udma_tchan
*tchan
, int reg
)
279 return udma_read(tchan
->reg_rt
, reg
);
282 static inline void udma_tchanrt_write(struct udma_tchan
*tchan
,
287 udma_write(tchan
->reg_rt
, reg
, val
);
291 static inline u32
udma_rchanrt_read(struct udma_rchan
*rchan
, int reg
)
295 return udma_read(rchan
->reg_rt
, reg
);
298 static inline void udma_rchanrt_write(struct udma_rchan
*rchan
,
303 udma_write(rchan
->reg_rt
, reg
, val
);
306 static inline int udma_navss_psil_pair(struct udma_dev
*ud
, u32 src_thread
,
309 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
311 dst_thread
|= UDMA_PSIL_DST_THREAD_ID_OFFSET
;
313 return tisci_rm
->tisci_psil_ops
->pair(tisci_rm
->tisci
,
314 tisci_rm
->tisci_navss_dev_id
,
315 src_thread
, dst_thread
);
318 static inline int udma_navss_psil_unpair(struct udma_dev
*ud
, u32 src_thread
,
321 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
323 dst_thread
|= UDMA_PSIL_DST_THREAD_ID_OFFSET
;
325 return tisci_rm
->tisci_psil_ops
->unpair(tisci_rm
->tisci
,
326 tisci_rm
->tisci_navss_dev_id
,
327 src_thread
, dst_thread
);
330 static inline char *udma_get_dir_text(enum dma_direction dir
)
348 #include "k3-udma-u-boot.c"
350 static void udma_reset_uchan(struct udma_chan
*uc
)
352 memset(&uc
->config
, 0, sizeof(uc
->config
));
353 uc
->config
.remote_thread_id
= -1;
354 uc
->config
.mapped_channel_id
= -1;
355 uc
->config
.default_flow_id
= -1;
358 static inline bool udma_is_chan_running(struct udma_chan
*uc
)
363 switch (uc
->config
.dir
) {
365 rrt_ctl
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
);
366 pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
368 udma_rchanrt_read(uc
->rchan
,
369 UDMA_RCHAN_RT_PEER_RT_EN_REG
));
372 trt_ctl
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
);
373 pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
375 udma_tchanrt_read(uc
->tchan
,
376 UDMA_TCHAN_RT_PEER_RT_EN_REG
));
379 trt_ctl
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
);
380 rrt_ctl
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
);
386 if (trt_ctl
& UDMA_CHAN_RT_CTL_EN
|| rrt_ctl
& UDMA_CHAN_RT_CTL_EN
)
392 static int udma_pop_from_ring(struct udma_chan
*uc
, dma_addr_t
*addr
)
394 struct k3_nav_ring
*ring
= NULL
;
397 switch (uc
->config
.dir
) {
399 ring
= uc
->rflow
->r_ring
;
402 ring
= uc
->tchan
->tc_ring
;
405 ring
= uc
->tchan
->tc_ring
;
411 if (ring
&& k3_nav_ringacc_ring_get_occ(ring
))
412 ret
= k3_nav_ringacc_ring_pop(ring
, addr
);
417 static void udma_reset_rings(struct udma_chan
*uc
)
419 struct k3_nav_ring
*ring1
= NULL
;
420 struct k3_nav_ring
*ring2
= NULL
;
422 switch (uc
->config
.dir
) {
424 ring1
= uc
->rflow
->fd_ring
;
425 ring2
= uc
->rflow
->r_ring
;
428 ring1
= uc
->tchan
->t_ring
;
429 ring2
= uc
->tchan
->tc_ring
;
432 ring1
= uc
->tchan
->t_ring
;
433 ring2
= uc
->tchan
->tc_ring
;
440 k3_nav_ringacc_ring_reset_dma(ring1
, k3_nav_ringacc_ring_get_occ(ring1
));
442 k3_nav_ringacc_ring_reset(ring2
);
445 static void udma_reset_counters(struct udma_chan
*uc
)
450 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_BCNT_REG
);
451 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_BCNT_REG
, val
);
453 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_SBCNT_REG
);
454 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_SBCNT_REG
, val
);
456 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_PCNT_REG
);
457 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_PCNT_REG
, val
);
460 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_PEER_BCNT_REG
);
461 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_PEER_BCNT_REG
, val
);
466 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_BCNT_REG
);
467 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_BCNT_REG
, val
);
469 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_SBCNT_REG
);
470 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_SBCNT_REG
, val
);
472 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_PCNT_REG
);
473 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_PCNT_REG
, val
);
475 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_PEER_BCNT_REG
);
476 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_PEER_BCNT_REG
, val
);
482 static inline int udma_stop_hard(struct udma_chan
*uc
)
484 pr_debug("%s: ENTER (chan%d)\n", __func__
, uc
->id
);
486 switch (uc
->config
.dir
) {
488 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_PEER_RT_EN_REG
, 0);
489 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
, 0);
492 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
, 0);
493 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_PEER_RT_EN_REG
, 0);
496 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
, 0);
497 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
, 0);
506 static int udma_start(struct udma_chan
*uc
)
508 /* Channel is already running, no need to proceed further */
509 if (udma_is_chan_running(uc
))
512 pr_debug("%s: chan:%d dir:%s\n",
513 __func__
, uc
->id
, udma_get_dir_text(uc
->config
.dir
));
515 /* Make sure that we clear the teardown bit, if it is set */
518 /* Reset all counters */
519 udma_reset_counters(uc
);
521 switch (uc
->config
.dir
) {
523 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
,
524 UDMA_CHAN_RT_CTL_EN
);
527 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_PEER_RT_EN_REG
,
528 UDMA_PEER_RT_EN_ENABLE
);
530 pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
532 udma_rchanrt_read(uc
->rchan
,
533 UDMA_RCHAN_RT_CTL_REG
),
534 udma_rchanrt_read(uc
->rchan
,
535 UDMA_RCHAN_RT_PEER_RT_EN_REG
));
539 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_PEER_RT_EN_REG
,
540 UDMA_PEER_RT_EN_ENABLE
);
542 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
,
543 UDMA_CHAN_RT_CTL_EN
);
545 pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
547 udma_tchanrt_read(uc
->tchan
,
548 UDMA_TCHAN_RT_CTL_REG
),
549 udma_tchanrt_read(uc
->tchan
,
550 UDMA_TCHAN_RT_PEER_RT_EN_REG
));
553 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
,
554 UDMA_CHAN_RT_CTL_EN
);
555 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
,
556 UDMA_CHAN_RT_CTL_EN
);
563 pr_debug("%s: DONE chan:%d\n", __func__
, uc
->id
);
568 static inline void udma_stop_mem2dev(struct udma_chan
*uc
, bool sync
)
573 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
,
574 UDMA_CHAN_RT_CTL_EN
|
575 UDMA_CHAN_RT_CTL_TDOWN
);
577 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
);
579 while (sync
&& (val
& UDMA_CHAN_RT_CTL_EN
)) {
580 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
);
583 printf(" %s TIMEOUT !\n", __func__
);
589 val
= udma_tchanrt_read(uc
->tchan
, UDMA_TCHAN_RT_PEER_RT_EN_REG
);
590 if (val
& UDMA_PEER_RT_EN_ENABLE
)
591 printf("%s: peer not stopped TIMEOUT !\n", __func__
);
594 static inline void udma_stop_dev2mem(struct udma_chan
*uc
, bool sync
)
599 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_PEER_RT_EN_REG
,
600 UDMA_PEER_RT_EN_ENABLE
|
601 UDMA_PEER_RT_EN_TEARDOWN
);
603 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
);
605 while (sync
&& (val
& UDMA_CHAN_RT_CTL_EN
)) {
606 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
);
609 printf("%s TIMEOUT !\n", __func__
);
615 val
= udma_rchanrt_read(uc
->rchan
, UDMA_RCHAN_RT_PEER_RT_EN_REG
);
616 if (val
& UDMA_PEER_RT_EN_ENABLE
)
617 printf("%s: peer not stopped TIMEOUT !\n", __func__
);
620 static inline int udma_stop(struct udma_chan
*uc
)
622 pr_debug("%s: chan:%d dir:%s\n",
623 __func__
, uc
->id
, udma_get_dir_text(uc
->config
.dir
));
625 udma_reset_counters(uc
);
626 switch (uc
->config
.dir
) {
628 udma_stop_dev2mem(uc
, true);
631 udma_stop_mem2dev(uc
, true);
634 udma_rchanrt_write(uc
->rchan
, UDMA_RCHAN_RT_CTL_REG
, 0);
635 udma_tchanrt_write(uc
->tchan
, UDMA_TCHAN_RT_CTL_REG
, 0);
644 static void udma_poll_completion(struct udma_chan
*uc
, dma_addr_t
*paddr
)
648 while (udma_pop_from_ring(uc
, paddr
)) {
656 static struct udma_rflow
*__udma_reserve_rflow(struct udma_dev
*ud
, int id
)
658 DECLARE_BITMAP(tmp
, K3_UDMA_MAX_RFLOWS
);
661 if (test_bit(id
, ud
->rflow_map
)) {
662 dev_err(ud
->dev
, "rflow%d is in use\n", id
);
663 return ERR_PTR(-ENOENT
);
666 bitmap_or(tmp
, ud
->rflow_map
, ud
->rflow_map_reserved
,
669 id
= find_next_zero_bit(tmp
, ud
->rflow_cnt
, ud
->rchan_cnt
);
670 if (id
>= ud
->rflow_cnt
)
671 return ERR_PTR(-ENOENT
);
674 __set_bit(id
, ud
->rflow_map
);
675 return &ud
->rflows
[id
];
678 #define UDMA_RESERVE_RESOURCE(res) \
679 static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud, \
683 if (test_bit(id, ud->res##_map)) { \
684 dev_err(ud->dev, "res##%d is in use\n", id); \
685 return ERR_PTR(-ENOENT); \
688 id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
689 if (id == ud->res##_cnt) { \
690 return ERR_PTR(-ENOENT); \
694 __set_bit(id, ud->res##_map); \
695 return &ud->res##s[id]; \
698 UDMA_RESERVE_RESOURCE(tchan
);
699 UDMA_RESERVE_RESOURCE(rchan
);
701 static int udma_get_tchan(struct udma_chan
*uc
)
703 struct udma_dev
*ud
= uc
->ud
;
706 dev_dbg(ud
->dev
, "chan%d: already have tchan%d allocated\n",
707 uc
->id
, uc
->tchan
->id
);
711 uc
->tchan
= __udma_reserve_tchan(ud
, uc
->config
.mapped_channel_id
);
712 if (IS_ERR(uc
->tchan
))
713 return PTR_ERR(uc
->tchan
);
718 /* Only PKTDMA have support for tx flows */
719 if (uc
->config
.default_flow_id
>= 0)
720 tflow_id
= uc
->config
.default_flow_id
;
722 tflow_id
= uc
->tchan
->id
;
724 if (test_bit(tflow_id
, ud
->tflow_map
)) {
725 dev_err(ud
->dev
, "tflow%d is in use\n", tflow_id
);
726 __clear_bit(uc
->tchan
->id
, ud
->tchan_map
);
731 uc
->tchan
->tflow_id
= tflow_id
;
732 __set_bit(tflow_id
, ud
->tflow_map
);
734 uc
->tchan
->tflow_id
= -1;
737 pr_debug("chan%d: got tchan%d\n", uc
->id
, uc
->tchan
->id
);
742 static int udma_get_rchan(struct udma_chan
*uc
)
744 struct udma_dev
*ud
= uc
->ud
;
747 dev_dbg(ud
->dev
, "chan%d: already have rchan%d allocated\n",
748 uc
->id
, uc
->rchan
->id
);
752 uc
->rchan
= __udma_reserve_rchan(ud
, uc
->config
.mapped_channel_id
);
753 if (IS_ERR(uc
->rchan
))
754 return PTR_ERR(uc
->rchan
);
756 pr_debug("chan%d: got rchan%d\n", uc
->id
, uc
->rchan
->id
);
761 static int udma_get_chan_pair(struct udma_chan
*uc
)
763 struct udma_dev
*ud
= uc
->ud
;
766 if ((uc
->tchan
&& uc
->rchan
) && uc
->tchan
->id
== uc
->rchan
->id
) {
767 dev_info(ud
->dev
, "chan%d: already have %d pair allocated\n",
768 uc
->id
, uc
->tchan
->id
);
773 dev_err(ud
->dev
, "chan%d: already have tchan%d allocated\n",
774 uc
->id
, uc
->tchan
->id
);
776 } else if (uc
->rchan
) {
777 dev_err(ud
->dev
, "chan%d: already have rchan%d allocated\n",
778 uc
->id
, uc
->rchan
->id
);
782 /* Can be optimized, but let's have it like this for now */
783 end
= min(ud
->tchan_cnt
, ud
->rchan_cnt
);
784 for (chan_id
= 0; chan_id
< end
; chan_id
++) {
785 if (!test_bit(chan_id
, ud
->tchan_map
) &&
786 !test_bit(chan_id
, ud
->rchan_map
))
793 __set_bit(chan_id
, ud
->tchan_map
);
794 __set_bit(chan_id
, ud
->rchan_map
);
795 uc
->tchan
= &ud
->tchans
[chan_id
];
796 uc
->rchan
= &ud
->rchans
[chan_id
];
798 pr_debug("chan%d: got t/rchan%d pair\n", uc
->id
, chan_id
);
803 static int udma_get_rflow(struct udma_chan
*uc
, int flow_id
)
805 struct udma_dev
*ud
= uc
->ud
;
808 dev_dbg(ud
->dev
, "chan%d: already have rflow%d allocated\n",
809 uc
->id
, uc
->rflow
->id
);
814 dev_warn(ud
->dev
, "chan%d: does not have rchan??\n", uc
->id
);
816 uc
->rflow
= __udma_reserve_rflow(ud
, flow_id
);
817 if (IS_ERR(uc
->rflow
))
818 return PTR_ERR(uc
->rflow
);
820 pr_debug("chan%d: got rflow%d\n", uc
->id
, uc
->rflow
->id
);
824 static void udma_put_rchan(struct udma_chan
*uc
)
826 struct udma_dev
*ud
= uc
->ud
;
829 dev_dbg(ud
->dev
, "chan%d: put rchan%d\n", uc
->id
,
831 __clear_bit(uc
->rchan
->id
, ud
->rchan_map
);
836 static void udma_put_tchan(struct udma_chan
*uc
)
838 struct udma_dev
*ud
= uc
->ud
;
841 dev_dbg(ud
->dev
, "chan%d: put tchan%d\n", uc
->id
,
843 __clear_bit(uc
->tchan
->id
, ud
->tchan_map
);
844 if (uc
->tchan
->tflow_id
>= 0)
845 __clear_bit(uc
->tchan
->tflow_id
, ud
->tflow_map
);
850 static void udma_put_rflow(struct udma_chan
*uc
)
852 struct udma_dev
*ud
= uc
->ud
;
855 dev_dbg(ud
->dev
, "chan%d: put rflow%d\n", uc
->id
,
857 __clear_bit(uc
->rflow
->id
, ud
->rflow_map
);
862 static void udma_free_tx_resources(struct udma_chan
*uc
)
867 k3_nav_ringacc_ring_free(uc
->tchan
->t_ring
);
868 k3_nav_ringacc_ring_free(uc
->tchan
->tc_ring
);
869 uc
->tchan
->t_ring
= NULL
;
870 uc
->tchan
->tc_ring
= NULL
;
875 static int udma_alloc_tx_resources(struct udma_chan
*uc
)
877 struct k3_nav_ring_cfg ring_cfg
;
878 struct udma_dev
*ud
= uc
->ud
;
879 struct udma_tchan
*tchan
;
882 ret
= udma_get_tchan(uc
);
887 if (tchan
->tflow_id
>= 0)
888 ring_idx
= tchan
->tflow_id
;
890 ring_idx
= ud
->bchan_cnt
+ tchan
->id
;
892 ret
= k3_nav_ringacc_request_rings_pair(ud
->ringacc
, ring_idx
, -1,
894 &uc
->tchan
->tc_ring
);
900 memset(&ring_cfg
, 0, sizeof(ring_cfg
));
902 ring_cfg
.elm_size
= K3_NAV_RINGACC_RING_ELSIZE_8
;
903 ring_cfg
.mode
= K3_NAV_RINGACC_RING_MODE_RING
;
905 ret
= k3_nav_ringacc_ring_cfg(uc
->tchan
->t_ring
, &ring_cfg
);
906 ret
|= k3_nav_ringacc_ring_cfg(uc
->tchan
->tc_ring
, &ring_cfg
);
914 k3_nav_ringacc_ring_free(uc
->tchan
->tc_ring
);
915 uc
->tchan
->tc_ring
= NULL
;
916 k3_nav_ringacc_ring_free(uc
->tchan
->t_ring
);
917 uc
->tchan
->t_ring
= NULL
;
924 static void udma_free_rx_resources(struct udma_chan
*uc
)
930 k3_nav_ringacc_ring_free(uc
->rflow
->fd_ring
);
931 k3_nav_ringacc_ring_free(uc
->rflow
->r_ring
);
932 uc
->rflow
->fd_ring
= NULL
;
933 uc
->rflow
->r_ring
= NULL
;
941 static int udma_alloc_rx_resources(struct udma_chan
*uc
)
943 struct k3_nav_ring_cfg ring_cfg
;
944 struct udma_dev
*ud
= uc
->ud
;
945 struct udma_rflow
*rflow
;
949 ret
= udma_get_rchan(uc
);
953 /* For MEM_TO_MEM we don't need rflow or rings */
954 if (uc
->config
.dir
== DMA_MEM_TO_MEM
)
957 if (uc
->config
.default_flow_id
>= 0)
958 ret
= udma_get_rflow(uc
, uc
->config
.default_flow_id
);
960 ret
= udma_get_rflow(uc
, uc
->rchan
->id
);
969 fd_ring_id
= ud
->tflow_cnt
+ rflow
->id
;
971 fd_ring_id
= ud
->bchan_cnt
+ ud
->tchan_cnt
+ ud
->echan_cnt
+
975 ret
= k3_nav_ringacc_request_rings_pair(ud
->ringacc
, fd_ring_id
, -1,
976 &rflow
->fd_ring
, &rflow
->r_ring
);
982 memset(&ring_cfg
, 0, sizeof(ring_cfg
));
984 ring_cfg
.elm_size
= K3_NAV_RINGACC_RING_ELSIZE_8
;
985 ring_cfg
.mode
= K3_NAV_RINGACC_RING_MODE_RING
;
987 ret
= k3_nav_ringacc_ring_cfg(rflow
->fd_ring
, &ring_cfg
);
988 ret
|= k3_nav_ringacc_ring_cfg(rflow
->r_ring
, &ring_cfg
);
995 k3_nav_ringacc_ring_free(rflow
->r_ring
);
996 rflow
->r_ring
= NULL
;
997 k3_nav_ringacc_ring_free(rflow
->fd_ring
);
998 rflow
->fd_ring
= NULL
;
1007 static int udma_alloc_tchan_sci_req(struct udma_chan
*uc
)
1009 struct udma_dev
*ud
= uc
->ud
;
1010 int tc_ring
= k3_nav_ringacc_get_ring_id(uc
->tchan
->tc_ring
);
1011 struct ti_sci_msg_rm_udmap_tx_ch_cfg req
;
1012 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1016 if (uc
->config
.pkt_mode
)
1017 mode
= TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR
;
1019 mode
= TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR
;
1021 req
.valid_params
= TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID
|
1022 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID
|
1023 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID
;
1024 req
.nav_id
= tisci_rm
->tisci_dev_id
;
1025 req
.index
= uc
->tchan
->id
;
1026 req
.tx_chan_type
= mode
;
1027 if (uc
->config
.dir
== DMA_MEM_TO_MEM
)
1028 req
.tx_fetch_size
= sizeof(struct cppi5_desc_hdr_t
) >> 2;
1030 req
.tx_fetch_size
= cppi5_hdesc_calc_size(uc
->config
.needs_epib
,
1031 uc
->config
.psd_size
,
1033 req
.txcq_qnum
= tc_ring
;
1035 ret
= tisci_rm
->tisci_udmap_ops
->tx_ch_cfg(tisci_rm
->tisci
, &req
);
1037 dev_err(ud
->dev
, "tisci tx alloc failed %d\n", ret
);
1042 * Above TI SCI call handles firewall configuration, cfg
1043 * register configuration still has to be done locally in
1044 * absence of RM services.
1046 if (IS_ENABLED(CONFIG_K3_DM_FW
))
1047 udma_alloc_tchan_raw(uc
);
1052 static int udma_alloc_rchan_sci_req(struct udma_chan
*uc
)
1054 struct udma_dev
*ud
= uc
->ud
;
1055 int fd_ring
= k3_nav_ringacc_get_ring_id(uc
->rflow
->fd_ring
);
1056 int rx_ring
= k3_nav_ringacc_get_ring_id(uc
->rflow
->r_ring
);
1057 int tc_ring
= k3_nav_ringacc_get_ring_id(uc
->tchan
->tc_ring
);
1058 struct ti_sci_msg_rm_udmap_rx_ch_cfg req
= { 0 };
1059 struct ti_sci_msg_rm_udmap_flow_cfg flow_req
= { 0 };
1060 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1064 if (uc
->config
.pkt_mode
)
1065 mode
= TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR
;
1067 mode
= TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR
;
1069 req
.valid_params
= TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID
|
1070 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID
|
1071 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID
;
1072 req
.nav_id
= tisci_rm
->tisci_dev_id
;
1073 req
.index
= uc
->rchan
->id
;
1074 req
.rx_chan_type
= mode
;
1075 if (uc
->config
.dir
== DMA_MEM_TO_MEM
) {
1076 req
.rx_fetch_size
= sizeof(struct cppi5_desc_hdr_t
) >> 2;
1077 req
.rxcq_qnum
= tc_ring
;
1079 req
.rx_fetch_size
= cppi5_hdesc_calc_size(uc
->config
.needs_epib
,
1080 uc
->config
.psd_size
,
1082 req
.rxcq_qnum
= rx_ring
;
1084 if (ud
->match_data
->type
== DMA_TYPE_UDMA
&&
1085 uc
->rflow
->id
!= uc
->rchan
->id
&&
1086 uc
->config
.dir
!= DMA_MEM_TO_MEM
) {
1087 req
.flowid_start
= uc
->rflow
->id
;
1089 req
.valid_params
|= TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID
|
1090 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID
;
1093 ret
= tisci_rm
->tisci_udmap_ops
->rx_ch_cfg(tisci_rm
->tisci
, &req
);
1095 dev_err(ud
->dev
, "tisci rx %u cfg failed %d\n",
1096 uc
->rchan
->id
, ret
);
1099 if (uc
->config
.dir
== DMA_MEM_TO_MEM
)
1102 flow_req
.valid_params
=
1103 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID
|
1104 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID
|
1105 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID
|
1106 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID
|
1107 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID
|
1108 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID
|
1109 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID
|
1110 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID
|
1111 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID
|
1112 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID
|
1113 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID
|
1114 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID
|
1115 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID
|
1116 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID
;
1118 flow_req
.nav_id
= tisci_rm
->tisci_dev_id
;
1119 flow_req
.flow_index
= uc
->rflow
->id
;
1121 if (uc
->config
.needs_epib
)
1122 flow_req
.rx_einfo_present
= 1;
1124 flow_req
.rx_einfo_present
= 0;
1126 if (uc
->config
.psd_size
)
1127 flow_req
.rx_psinfo_present
= 1;
1129 flow_req
.rx_psinfo_present
= 0;
1131 flow_req
.rx_error_handling
= 0;
1132 flow_req
.rx_desc_type
= 0;
1133 flow_req
.rx_dest_qnum
= rx_ring
;
1134 flow_req
.rx_src_tag_hi_sel
= 2;
1135 flow_req
.rx_src_tag_lo_sel
= 4;
1136 flow_req
.rx_dest_tag_hi_sel
= 5;
1137 flow_req
.rx_dest_tag_lo_sel
= 4;
1138 flow_req
.rx_fdq0_sz0_qnum
= fd_ring
;
1139 flow_req
.rx_fdq1_qnum
= fd_ring
;
1140 flow_req
.rx_fdq2_qnum
= fd_ring
;
1141 flow_req
.rx_fdq3_qnum
= fd_ring
;
1142 flow_req
.rx_ps_location
= 0;
1144 ret
= tisci_rm
->tisci_udmap_ops
->rx_flow_cfg(tisci_rm
->tisci
,
1147 dev_err(ud
->dev
, "tisci rx %u flow %u cfg failed %d\n",
1148 uc
->rchan
->id
, uc
->rflow
->id
, ret
);
1153 * Above TI SCI call handles firewall configuration, cfg
1154 * register configuration still has to be done locally in
1155 * absence of RM services.
1157 if (IS_ENABLED(CONFIG_K3_DM_FW
))
1158 udma_alloc_rchan_raw(uc
);
1163 static int udma_alloc_chan_resources(struct udma_chan
*uc
)
1165 struct udma_dev
*ud
= uc
->ud
;
1168 pr_debug("%s: chan:%d as %s\n",
1169 __func__
, uc
->id
, udma_get_dir_text(uc
->config
.dir
));
1171 switch (uc
->config
.dir
) {
1172 case DMA_MEM_TO_MEM
:
1173 /* Non synchronized - mem to mem type of transfer */
1174 uc
->config
.pkt_mode
= false;
1175 ret
= udma_get_chan_pair(uc
);
1179 ret
= udma_alloc_tx_resources(uc
);
1183 ret
= udma_alloc_rx_resources(uc
);
1187 uc
->config
.src_thread
= ud
->psil_base
+ uc
->tchan
->id
;
1188 uc
->config
.dst_thread
= (ud
->psil_base
+ uc
->rchan
->id
) | 0x8000;
1190 case DMA_MEM_TO_DEV
:
1191 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
1192 ret
= udma_alloc_tx_resources(uc
);
1196 uc
->config
.src_thread
= ud
->psil_base
+ uc
->tchan
->id
;
1197 uc
->config
.dst_thread
= uc
->config
.remote_thread_id
;
1198 uc
->config
.dst_thread
|= 0x8000;
1201 case DMA_DEV_TO_MEM
:
1202 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
1203 ret
= udma_alloc_rx_resources(uc
);
1207 uc
->config
.src_thread
= uc
->config
.remote_thread_id
;
1208 uc
->config
.dst_thread
= (ud
->psil_base
+ uc
->rchan
->id
) | 0x8000;
1212 /* Can not happen */
1213 pr_debug("%s: chan:%d invalid direction (%u)\n",
1214 __func__
, uc
->id
, uc
->config
.dir
);
1218 /* We have channel indexes and rings */
1219 if (uc
->config
.dir
== DMA_MEM_TO_MEM
) {
1220 ret
= udma_alloc_tchan_sci_req(uc
);
1224 ret
= udma_alloc_rchan_sci_req(uc
);
1228 /* Slave transfer */
1229 if (uc
->config
.dir
== DMA_MEM_TO_DEV
) {
1230 ret
= udma_alloc_tchan_sci_req(uc
);
1234 ret
= udma_alloc_rchan_sci_req(uc
);
1240 if (udma_is_chan_running(uc
)) {
1241 dev_warn(ud
->dev
, "chan%d: is running!\n", uc
->id
);
1243 if (udma_is_chan_running(uc
)) {
1244 dev_err(ud
->dev
, "chan%d: won't stop!\n", uc
->id
);
1250 ret
= udma_navss_psil_pair(ud
, uc
->config
.src_thread
, uc
->config
.dst_thread
);
1252 dev_err(ud
->dev
, "k3_nav_psil_request_link fail\n");
1259 udma_free_tx_resources(uc
);
1260 udma_free_rx_resources(uc
);
1261 uc
->config
.remote_thread_id
= -1;
1265 static void udma_free_chan_resources(struct udma_chan
*uc
)
1267 /* Hard reset UDMA channel */
1269 udma_reset_counters(uc
);
1271 /* Release PSI-L pairing */
1272 udma_navss_psil_unpair(uc
->ud
, uc
->config
.src_thread
, uc
->config
.dst_thread
);
1274 /* Reset the rings for a new start */
1275 udma_reset_rings(uc
);
1276 udma_free_tx_resources(uc
);
1277 udma_free_rx_resources(uc
);
1279 uc
->config
.remote_thread_id
= -1;
1280 uc
->config
.dir
= DMA_MEM_TO_MEM
;
1283 static const char * const range_names
[] = {
1284 [RM_RANGE_BCHAN
] = "ti,sci-rm-range-bchan",
1285 [RM_RANGE_TCHAN
] = "ti,sci-rm-range-tchan",
1286 [RM_RANGE_RCHAN
] = "ti,sci-rm-range-rchan",
1287 [RM_RANGE_RFLOW
] = "ti,sci-rm-range-rflow",
1288 [RM_RANGE_TFLOW
] = "ti,sci-rm-range-tflow",
1291 static int udma_get_mmrs(struct udevice
*dev
)
1293 struct udma_dev
*ud
= dev_get_priv(dev
);
1294 u32 cap2
, cap3
, cap4
;
1297 ud
->mmrs
[MMR_GCFG
] = dev_read_addr_name_ptr(dev
, mmr_names
[MMR_GCFG
]);
1298 if (!ud
->mmrs
[MMR_GCFG
])
1301 cap2
= udma_read(ud
->mmrs
[MMR_GCFG
], 0x28);
1302 cap3
= udma_read(ud
->mmrs
[MMR_GCFG
], 0x2c);
1304 switch (ud
->match_data
->type
) {
1306 ud
->rflow_cnt
= cap3
& 0x3fff;
1307 ud
->tchan_cnt
= cap2
& 0x1ff;
1308 ud
->echan_cnt
= (cap2
>> 9) & 0x1ff;
1309 ud
->rchan_cnt
= (cap2
>> 18) & 0x1ff;
1311 case DMA_TYPE_BCDMA
:
1312 ud
->bchan_cnt
= cap2
& 0x1ff;
1313 ud
->tchan_cnt
= (cap2
>> 9) & 0x1ff;
1314 ud
->rchan_cnt
= (cap2
>> 18) & 0x1ff;
1316 case DMA_TYPE_PKTDMA
:
1317 cap4
= udma_read(ud
->mmrs
[MMR_GCFG
], 0x30);
1318 ud
->tchan_cnt
= cap2
& 0x1ff;
1319 ud
->rchan_cnt
= (cap2
>> 18) & 0x1ff;
1320 ud
->rflow_cnt
= cap3
& 0x3fff;
1321 ud
->tflow_cnt
= cap4
& 0x3fff;
1327 for (i
= 1; i
< MMR_LAST
; i
++) {
1328 if (i
== MMR_BCHANRT
&& ud
->bchan_cnt
== 0)
1330 if (i
== MMR_TCHANRT
&& ud
->tchan_cnt
== 0)
1332 if (i
== MMR_RCHANRT
&& ud
->rchan_cnt
== 0)
1335 ud
->mmrs
[i
] = dev_read_addr_name_ptr(dev
, mmr_names
[i
]);
1343 static int udma_setup_resources(struct udma_dev
*ud
)
1345 struct udevice
*dev
= ud
->dev
;
1347 struct ti_sci_resource_desc
*rm_desc
;
1348 struct ti_sci_resource
*rm_res
;
1349 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1351 ud
->tchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->tchan_cnt
),
1352 sizeof(unsigned long), GFP_KERNEL
);
1353 ud
->tchans
= devm_kcalloc(dev
, ud
->tchan_cnt
, sizeof(*ud
->tchans
),
1355 ud
->rchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->rchan_cnt
),
1356 sizeof(unsigned long), GFP_KERNEL
);
1357 ud
->rchans
= devm_kcalloc(dev
, ud
->rchan_cnt
, sizeof(*ud
->rchans
),
1359 ud
->rflow_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->rflow_cnt
),
1360 sizeof(unsigned long), GFP_KERNEL
);
1361 ud
->rflow_map_reserved
= devm_kcalloc(dev
, BITS_TO_LONGS(ud
->rflow_cnt
),
1362 sizeof(unsigned long),
1364 ud
->rflows
= devm_kcalloc(dev
, ud
->rflow_cnt
, sizeof(*ud
->rflows
),
1367 if (!ud
->tchan_map
|| !ud
->rchan_map
|| !ud
->rflow_map
||
1368 !ud
->rflow_map_reserved
|| !ud
->tchans
|| !ud
->rchans
||
1373 * RX flows with the same Ids as RX channels are reserved to be used
1374 * as default flows if remote HW can't generate flow_ids. Those
1375 * RX flows can be requested only explicitly by id.
1377 bitmap_set(ud
->rflow_map_reserved
, 0, ud
->rchan_cnt
);
1379 /* Get resource ranges from tisci */
1380 for (i
= 0; i
< RM_RANGE_LAST
; i
++) {
1381 if (i
== RM_RANGE_BCHAN
|| i
== RM_RANGE_TFLOW
)
1384 tisci_rm
->rm_ranges
[i
] =
1385 devm_ti_sci_get_of_resource(tisci_rm
->tisci
, dev
,
1386 tisci_rm
->tisci_dev_id
,
1387 (char *)range_names
[i
]);
1391 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_TCHAN
];
1392 if (IS_ERR(rm_res
)) {
1393 bitmap_zero(ud
->tchan_map
, ud
->tchan_cnt
);
1395 bitmap_fill(ud
->tchan_map
, ud
->tchan_cnt
);
1396 for (i
= 0; i
< rm_res
->sets
; i
++) {
1397 rm_desc
= &rm_res
->desc
[i
];
1398 bitmap_clear(ud
->tchan_map
, rm_desc
->start
,
1403 /* rchan and matching default flow ranges */
1404 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_RCHAN
];
1405 if (IS_ERR(rm_res
)) {
1406 bitmap_zero(ud
->rchan_map
, ud
->rchan_cnt
);
1407 bitmap_zero(ud
->rflow_map
, ud
->rchan_cnt
);
1409 bitmap_fill(ud
->rchan_map
, ud
->rchan_cnt
);
1410 bitmap_fill(ud
->rflow_map
, ud
->rchan_cnt
);
1411 for (i
= 0; i
< rm_res
->sets
; i
++) {
1412 rm_desc
= &rm_res
->desc
[i
];
1413 bitmap_clear(ud
->rchan_map
, rm_desc
->start
,
1415 bitmap_clear(ud
->rflow_map
, rm_desc
->start
,
1420 /* GP rflow ranges */
1421 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_RFLOW
];
1422 if (IS_ERR(rm_res
)) {
1423 bitmap_clear(ud
->rflow_map
, ud
->rchan_cnt
,
1424 ud
->rflow_cnt
- ud
->rchan_cnt
);
1426 bitmap_set(ud
->rflow_map
, ud
->rchan_cnt
,
1427 ud
->rflow_cnt
- ud
->rchan_cnt
);
1428 for (i
= 0; i
< rm_res
->sets
; i
++) {
1429 rm_desc
= &rm_res
->desc
[i
];
1430 bitmap_clear(ud
->rflow_map
, rm_desc
->start
,
1438 static int bcdma_setup_resources(struct udma_dev
*ud
)
1441 struct udevice
*dev
= ud
->dev
;
1442 struct ti_sci_resource_desc
*rm_desc
;
1443 struct ti_sci_resource
*rm_res
;
1444 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1446 ud
->bchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->bchan_cnt
),
1447 sizeof(unsigned long), GFP_KERNEL
);
1448 ud
->bchans
= devm_kcalloc(dev
, ud
->bchan_cnt
, sizeof(*ud
->bchans
),
1450 ud
->tchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->tchan_cnt
),
1451 sizeof(unsigned long), GFP_KERNEL
);
1452 ud
->tchans
= devm_kcalloc(dev
, ud
->tchan_cnt
, sizeof(*ud
->tchans
),
1454 ud
->rchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->rchan_cnt
),
1455 sizeof(unsigned long), GFP_KERNEL
);
1456 ud
->rchans
= devm_kcalloc(dev
, ud
->rchan_cnt
, sizeof(*ud
->rchans
),
1458 ud
->rflows
= devm_kcalloc(dev
, ud
->rchan_cnt
, sizeof(*ud
->rflows
),
1461 if (!ud
->bchan_map
|| !ud
->tchan_map
|| !ud
->rchan_map
||
1462 !ud
->bchans
|| !ud
->tchans
|| !ud
->rchans
||
1466 /* Get resource ranges from tisci */
1467 for (i
= 0; i
< RM_RANGE_LAST
; i
++) {
1468 if (i
== RM_RANGE_RFLOW
|| i
== RM_RANGE_TFLOW
)
1471 tisci_rm
->rm_ranges
[i
] =
1472 devm_ti_sci_get_of_resource(tisci_rm
->tisci
, dev
,
1473 tisci_rm
->tisci_dev_id
,
1474 (char *)range_names
[i
]);
1478 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_BCHAN
];
1479 if (IS_ERR(rm_res
)) {
1480 bitmap_zero(ud
->bchan_map
, ud
->bchan_cnt
);
1482 bitmap_fill(ud
->bchan_map
, ud
->bchan_cnt
);
1483 for (i
= 0; i
< rm_res
->sets
; i
++) {
1484 rm_desc
= &rm_res
->desc
[i
];
1485 bitmap_clear(ud
->bchan_map
, rm_desc
->start
,
1487 dev_dbg(dev
, "ti-sci-res: bchan: %d:%d\n",
1488 rm_desc
->start
, rm_desc
->num
);
1493 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_TCHAN
];
1494 if (IS_ERR(rm_res
)) {
1495 bitmap_zero(ud
->tchan_map
, ud
->tchan_cnt
);
1497 bitmap_fill(ud
->tchan_map
, ud
->tchan_cnt
);
1498 for (i
= 0; i
< rm_res
->sets
; i
++) {
1499 rm_desc
= &rm_res
->desc
[i
];
1500 bitmap_clear(ud
->tchan_map
, rm_desc
->start
,
1502 dev_dbg(dev
, "ti-sci-res: tchan: %d:%d\n",
1503 rm_desc
->start
, rm_desc
->num
);
1508 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_RCHAN
];
1509 if (IS_ERR(rm_res
)) {
1510 bitmap_zero(ud
->rchan_map
, ud
->rchan_cnt
);
1512 bitmap_fill(ud
->rchan_map
, ud
->rchan_cnt
);
1513 for (i
= 0; i
< rm_res
->sets
; i
++) {
1514 rm_desc
= &rm_res
->desc
[i
];
1515 bitmap_clear(ud
->rchan_map
, rm_desc
->start
,
1517 dev_dbg(dev
, "ti-sci-res: rchan: %d:%d\n",
1518 rm_desc
->start
, rm_desc
->num
);
1525 static int pktdma_setup_resources(struct udma_dev
*ud
)
1528 struct udevice
*dev
= ud
->dev
;
1529 struct ti_sci_resource
*rm_res
;
1530 struct ti_sci_resource_desc
*rm_desc
;
1531 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1533 ud
->tchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->tchan_cnt
),
1534 sizeof(unsigned long), GFP_KERNEL
);
1535 ud
->tchans
= devm_kcalloc(dev
, ud
->tchan_cnt
, sizeof(*ud
->tchans
),
1537 ud
->rchan_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->rchan_cnt
),
1538 sizeof(unsigned long), GFP_KERNEL
);
1539 ud
->rchans
= devm_kcalloc(dev
, ud
->rchan_cnt
, sizeof(*ud
->rchans
),
1541 ud
->rflow_map
= devm_kcalloc(dev
, BITS_TO_LONGS(ud
->rflow_cnt
),
1542 sizeof(unsigned long),
1544 ud
->rflows
= devm_kcalloc(dev
, ud
->rflow_cnt
, sizeof(*ud
->rflows
),
1546 ud
->tflow_map
= devm_kmalloc_array(dev
, BITS_TO_LONGS(ud
->tflow_cnt
),
1547 sizeof(unsigned long), GFP_KERNEL
);
1549 if (!ud
->tchan_map
|| !ud
->rchan_map
|| !ud
->tflow_map
|| !ud
->tchans
||
1550 !ud
->rchans
|| !ud
->rflows
|| !ud
->rflow_map
)
1553 /* Get resource ranges from tisci */
1554 for (i
= 0; i
< RM_RANGE_LAST
; i
++) {
1555 if (i
== RM_RANGE_BCHAN
)
1558 tisci_rm
->rm_ranges
[i
] =
1559 devm_ti_sci_get_of_resource(tisci_rm
->tisci
, dev
,
1560 tisci_rm
->tisci_dev_id
,
1561 (char *)range_names
[i
]);
1565 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_TCHAN
];
1566 if (IS_ERR(rm_res
)) {
1567 bitmap_zero(ud
->tchan_map
, ud
->tchan_cnt
);
1569 bitmap_fill(ud
->tchan_map
, ud
->tchan_cnt
);
1570 for (i
= 0; i
< rm_res
->sets
; i
++) {
1571 rm_desc
= &rm_res
->desc
[i
];
1572 bitmap_clear(ud
->tchan_map
, rm_desc
->start
,
1574 dev_dbg(dev
, "ti-sci-res: tchan: %d:%d\n",
1575 rm_desc
->start
, rm_desc
->num
);
1580 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_RCHAN
];
1581 if (IS_ERR(rm_res
)) {
1582 bitmap_zero(ud
->rchan_map
, ud
->rchan_cnt
);
1584 bitmap_fill(ud
->rchan_map
, ud
->rchan_cnt
);
1585 for (i
= 0; i
< rm_res
->sets
; i
++) {
1586 rm_desc
= &rm_res
->desc
[i
];
1587 bitmap_clear(ud
->rchan_map
, rm_desc
->start
,
1589 dev_dbg(dev
, "ti-sci-res: rchan: %d:%d\n",
1590 rm_desc
->start
, rm_desc
->num
);
1595 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_RFLOW
];
1596 if (IS_ERR(rm_res
)) {
1597 /* all rflows are assigned exclusively to Linux */
1598 bitmap_zero(ud
->rflow_map
, ud
->rflow_cnt
);
1600 bitmap_fill(ud
->rflow_map
, ud
->rflow_cnt
);
1601 for (i
= 0; i
< rm_res
->sets
; i
++) {
1602 rm_desc
= &rm_res
->desc
[i
];
1603 bitmap_clear(ud
->rflow_map
, rm_desc
->start
,
1605 dev_dbg(dev
, "ti-sci-res: rflow: %d:%d\n",
1606 rm_desc
->start
, rm_desc
->num
);
1611 rm_res
= tisci_rm
->rm_ranges
[RM_RANGE_TFLOW
];
1612 if (IS_ERR(rm_res
)) {
1613 /* all tflows are assigned exclusively to Linux */
1614 bitmap_zero(ud
->tflow_map
, ud
->tflow_cnt
);
1616 bitmap_fill(ud
->tflow_map
, ud
->tflow_cnt
);
1617 for (i
= 0; i
< rm_res
->sets
; i
++) {
1618 rm_desc
= &rm_res
->desc
[i
];
1619 bitmap_clear(ud
->tflow_map
, rm_desc
->start
,
1621 dev_dbg(dev
, "ti-sci-res: tflow: %d:%d\n",
1622 rm_desc
->start
, rm_desc
->num
);
1629 static int setup_resources(struct udma_dev
*ud
)
1631 struct udevice
*dev
= ud
->dev
;
1634 switch (ud
->match_data
->type
) {
1636 ret
= udma_setup_resources(ud
);
1638 case DMA_TYPE_BCDMA
:
1639 ret
= bcdma_setup_resources(ud
);
1641 case DMA_TYPE_PKTDMA
:
1642 ret
= pktdma_setup_resources(ud
);
1651 ch_count
= ud
->bchan_cnt
+ ud
->tchan_cnt
+ ud
->rchan_cnt
;
1653 ch_count
-= bitmap_weight(ud
->bchan_map
, ud
->bchan_cnt
);
1654 ch_count
-= bitmap_weight(ud
->tchan_map
, ud
->tchan_cnt
);
1655 ch_count
-= bitmap_weight(ud
->rchan_map
, ud
->rchan_cnt
);
1659 ud
->channels
= devm_kcalloc(dev
, ch_count
, sizeof(*ud
->channels
),
1664 switch (ud
->match_data
->type
) {
1667 "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
1669 ud
->tchan_cnt
- bitmap_weight(ud
->tchan_map
,
1671 ud
->rchan_cnt
- bitmap_weight(ud
->rchan_map
,
1673 ud
->rflow_cnt
- bitmap_weight(ud
->rflow_map
,
1676 case DMA_TYPE_BCDMA
:
1678 "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
1680 ud
->bchan_cnt
- bitmap_weight(ud
->bchan_map
,
1682 ud
->tchan_cnt
- bitmap_weight(ud
->tchan_map
,
1684 ud
->rchan_cnt
- bitmap_weight(ud
->rchan_map
,
1687 case DMA_TYPE_PKTDMA
:
1689 "Channels: %d (tchan: %u, rchan: %u)\n",
1691 ud
->tchan_cnt
- bitmap_weight(ud
->tchan_map
,
1693 ud
->rchan_cnt
- bitmap_weight(ud
->rchan_map
,
1703 static int udma_probe(struct udevice
*dev
)
1705 struct dma_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
1706 struct udma_dev
*ud
= dev_get_priv(dev
);
1708 struct udevice
*tmp
;
1709 struct udevice
*tisci_dev
= NULL
;
1710 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1711 ofnode navss_ofnode
= ofnode_get_parent(dev_ofnode(dev
));
1714 ud
->match_data
= (void *)dev_get_driver_data(dev
);
1715 ret
= udma_get_mmrs(dev
);
1719 ud
->psil_base
= ud
->match_data
->psil_base
;
1721 ret
= uclass_get_device_by_phandle(UCLASS_FIRMWARE
, dev
,
1722 "ti,sci", &tisci_dev
);
1724 debug("Failed to get TISCI phandle (%d)\n", ret
);
1725 tisci_rm
->tisci
= NULL
;
1728 tisci_rm
->tisci
= (struct ti_sci_handle
*)
1729 (ti_sci_get_handle_from_sysfw(tisci_dev
));
1731 tisci_rm
->tisci_dev_id
= -1;
1732 ret
= dev_read_u32(dev
, "ti,sci-dev-id", &tisci_rm
->tisci_dev_id
);
1734 dev_err(dev
, "ti,sci-dev-id read failure %d\n", ret
);
1738 tisci_rm
->tisci_navss_dev_id
= -1;
1739 ret
= ofnode_read_u32(navss_ofnode
, "ti,sci-dev-id",
1740 &tisci_rm
->tisci_navss_dev_id
);
1742 dev_err(dev
, "navss sci-dev-id read failure %d\n", ret
);
1746 tisci_rm
->tisci_udmap_ops
= &tisci_rm
->tisci
->ops
.rm_udmap_ops
;
1747 tisci_rm
->tisci_psil_ops
= &tisci_rm
->tisci
->ops
.rm_psil_ops
;
1749 if (ud
->match_data
->type
== DMA_TYPE_UDMA
) {
1750 ret
= uclass_get_device_by_phandle(UCLASS_MISC
, dev
,
1751 "ti,ringacc", &tmp
);
1752 ud
->ringacc
= dev_get_priv(tmp
);
1754 struct k3_ringacc_init_data ring_init_data
;
1756 ring_init_data
.tisci
= ud
->tisci_rm
.tisci
;
1757 ring_init_data
.tisci_dev_id
= ud
->tisci_rm
.tisci_dev_id
;
1758 if (ud
->match_data
->type
== DMA_TYPE_BCDMA
) {
1759 ring_init_data
.num_rings
= ud
->bchan_cnt
+
1763 ring_init_data
.num_rings
= ud
->rflow_cnt
+
1767 ud
->ringacc
= k3_ringacc_dmarings_init(dev
, &ring_init_data
);
1769 if (IS_ERR(ud
->ringacc
))
1770 return PTR_ERR(ud
->ringacc
);
1773 ud
->ch_count
= setup_resources(ud
);
1774 if (ud
->ch_count
<= 0)
1775 return ud
->ch_count
;
1777 for (i
= 0; i
< ud
->bchan_cnt
; i
++) {
1778 struct udma_bchan
*bchan
= &ud
->bchans
[i
];
1781 bchan
->reg_rt
= ud
->mmrs
[MMR_BCHANRT
] + i
* 0x1000;
1784 for (i
= 0; i
< ud
->tchan_cnt
; i
++) {
1785 struct udma_tchan
*tchan
= &ud
->tchans
[i
];
1788 tchan
->reg_chan
= ud
->mmrs
[MMR_TCHAN
] + UDMA_CH_100(i
);
1789 tchan
->reg_rt
= ud
->mmrs
[MMR_TCHANRT
] + UDMA_CH_1000(i
);
1792 for (i
= 0; i
< ud
->rchan_cnt
; i
++) {
1793 struct udma_rchan
*rchan
= &ud
->rchans
[i
];
1796 rchan
->reg_chan
= ud
->mmrs
[MMR_RCHAN
] + UDMA_CH_100(i
);
1797 rchan
->reg_rt
= ud
->mmrs
[MMR_RCHANRT
] + UDMA_CH_1000(i
);
1800 for (i
= 0; i
< ud
->rflow_cnt
; i
++) {
1801 struct udma_rflow
*rflow
= &ud
->rflows
[i
];
1804 rflow
->reg_rflow
= ud
->mmrs
[MMR_RFLOW
] + UDMA_CH_40(i
);
1807 for (i
= 0; i
< ud
->ch_count
; i
++) {
1808 struct udma_chan
*uc
= &ud
->channels
[i
];
1812 uc
->config
.remote_thread_id
= -1;
1816 uc
->config
.mapped_channel_id
= -1;
1817 uc
->config
.default_flow_id
= -1;
1818 uc
->config
.dir
= DMA_MEM_TO_MEM
;
1819 sprintf(uc
->name
, "UDMA chan%d\n", i
);
1824 pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1826 udma_read(ud
->mmrs
[MMR_GCFG
], 0),
1827 udma_read(ud
->mmrs
[MMR_GCFG
], 0x20),
1828 udma_read(ud
->mmrs
[MMR_GCFG
], 0x24),
1829 udma_read(ud
->mmrs
[MMR_GCFG
], 0x28),
1830 udma_read(ud
->mmrs
[MMR_GCFG
], 0x2c));
1832 uc_priv
->supported
= DMA_SUPPORTS_MEM_TO_MEM
| DMA_SUPPORTS_MEM_TO_DEV
;
1837 static int udma_push_to_ring(struct k3_nav_ring
*ring
, void *elem
)
1841 memcpy(&addr
, &elem
, sizeof(elem
));
1842 return k3_nav_ringacc_ring_push(ring
, &addr
);
1845 static int *udma_prep_dma_memcpy(struct udma_chan
*uc
, dma_addr_t dest
,
1846 dma_addr_t src
, size_t len
)
1848 u32 tc_ring_id
= k3_nav_ringacc_get_ring_id(uc
->tchan
->tc_ring
);
1849 struct cppi5_tr_type15_t
*tr_req
;
1851 size_t tr_size
= sizeof(struct cppi5_tr_type15_t
);
1852 u16 tr0_cnt0
, tr0_cnt1
, tr1_cnt0
;
1853 unsigned long dummy
;
1862 unsigned long align_to
= __ffs(src
| dest
);
1867 * Keep simple: tr0: SZ_64K-alignment blocks,
1868 * tr1: the remaining
1871 tr0_cnt0
= (SZ_64K
- BIT(align_to
));
1872 if (len
/ tr0_cnt0
>= SZ_64K
) {
1873 dev_err(uc
->ud
->dev
, "size %zu is not supported\n",
1878 tr0_cnt1
= len
/ tr0_cnt0
;
1879 tr1_cnt0
= len
% tr0_cnt0
;
1882 desc_size
= cppi5_trdesc_calc_size(num_tr
, tr_size
);
1883 tr_desc
= dma_alloc_coherent(desc_size
, &dummy
);
1886 memset(tr_desc
, 0, desc_size
);
1888 cppi5_trdesc_init(tr_desc
, num_tr
, tr_size
, 0, 0);
1889 cppi5_desc_set_pktids(tr_desc
, uc
->id
, 0x3fff);
1890 cppi5_desc_set_retpolicy(tr_desc
, 0, tc_ring_id
);
1892 tr_req
= tr_desc
+ tr_size
;
1894 cppi5_tr_init(&tr_req
[0].flags
, CPPI5_TR_TYPE15
, false, true,
1895 CPPI5_TR_EVENT_SIZE_COMPLETION
, 1);
1896 cppi5_tr_csf_set(&tr_req
[0].flags
, CPPI5_TR_CSF_SUPR_EVT
);
1898 tr_req
[0].addr
= src
;
1899 tr_req
[0].icnt0
= tr0_cnt0
;
1900 tr_req
[0].icnt1
= tr0_cnt1
;
1901 tr_req
[0].icnt2
= 1;
1902 tr_req
[0].icnt3
= 1;
1903 tr_req
[0].dim1
= tr0_cnt0
;
1905 tr_req
[0].daddr
= dest
;
1906 tr_req
[0].dicnt0
= tr0_cnt0
;
1907 tr_req
[0].dicnt1
= tr0_cnt1
;
1908 tr_req
[0].dicnt2
= 1;
1909 tr_req
[0].dicnt3
= 1;
1910 tr_req
[0].ddim1
= tr0_cnt0
;
1913 cppi5_tr_init(&tr_req
[1].flags
, CPPI5_TR_TYPE15
, false, true,
1914 CPPI5_TR_EVENT_SIZE_COMPLETION
, 0);
1915 cppi5_tr_csf_set(&tr_req
[1].flags
, CPPI5_TR_CSF_SUPR_EVT
);
1917 tr_req
[1].addr
= src
+ tr0_cnt1
* tr0_cnt0
;
1918 tr_req
[1].icnt0
= tr1_cnt0
;
1919 tr_req
[1].icnt1
= 1;
1920 tr_req
[1].icnt2
= 1;
1921 tr_req
[1].icnt3
= 1;
1923 tr_req
[1].daddr
= dest
+ tr0_cnt1
* tr0_cnt0
;
1924 tr_req
[1].dicnt0
= tr1_cnt0
;
1925 tr_req
[1].dicnt1
= 1;
1926 tr_req
[1].dicnt2
= 1;
1927 tr_req
[1].dicnt3
= 1;
1930 cppi5_tr_csf_set(&tr_req
[num_tr
- 1].flags
, CPPI5_TR_CSF_EOP
);
1932 flush_dcache_range((unsigned long)tr_desc
,
1933 ALIGN((unsigned long)tr_desc
+ desc_size
,
1934 ARCH_DMA_MINALIGN
));
1936 udma_push_to_ring(uc
->tchan
->t_ring
, tr_desc
);
1941 #define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
1942 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1943 TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
1945 #define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \
1946 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1947 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
1949 #define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \
1950 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
1952 #define TISCI_UDMA_TCHAN_VALID_PARAMS ( \
1953 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1954 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \
1955 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \
1956 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
1957 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \
1958 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
1959 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
1960 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
1962 #define TISCI_UDMA_RCHAN_VALID_PARAMS ( \
1963 TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
1964 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
1965 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
1966 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
1967 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \
1968 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \
1969 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \
1970 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \
1971 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
1973 static int bcdma_tisci_m2m_channel_config(struct udma_chan
*uc
)
1975 struct udma_dev
*ud
= uc
->ud
;
1976 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
1977 const struct ti_sci_rm_udmap_ops
*tisci_ops
= tisci_rm
->tisci_udmap_ops
;
1978 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx
= { 0 };
1979 struct udma_bchan
*bchan
= uc
->bchan
;
1982 req_tx
.valid_params
= TISCI_BCDMA_BCHAN_VALID_PARAMS
;
1983 req_tx
.nav_id
= tisci_rm
->tisci_dev_id
;
1984 req_tx
.extended_ch_type
= TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN
;
1985 req_tx
.index
= bchan
->id
;
1987 ret
= tisci_ops
->tx_ch_cfg(tisci_rm
->tisci
, &req_tx
);
1989 dev_err(ud
->dev
, "bchan%d cfg failed %d\n", bchan
->id
, ret
);
1994 static struct udma_bchan
*__bcdma_reserve_bchan(struct udma_dev
*ud
, int id
)
1997 if (test_bit(id
, ud
->bchan_map
)) {
1998 dev_err(ud
->dev
, "bchan%d is in use\n", id
);
1999 return ERR_PTR(-ENOENT
);
2002 id
= find_next_zero_bit(ud
->bchan_map
, ud
->bchan_cnt
, 0);
2003 if (id
== ud
->bchan_cnt
)
2004 return ERR_PTR(-ENOENT
);
2006 __set_bit(id
, ud
->bchan_map
);
2007 return &ud
->bchans
[id
];
2010 static int bcdma_get_bchan(struct udma_chan
*uc
)
2012 struct udma_dev
*ud
= uc
->ud
;
2015 dev_err(ud
->dev
, "chan%d: already have bchan%d allocated\n",
2016 uc
->id
, uc
->bchan
->id
);
2020 uc
->bchan
= __bcdma_reserve_bchan(ud
, -1);
2021 if (IS_ERR(uc
->bchan
))
2022 return PTR_ERR(uc
->bchan
);
2024 uc
->tchan
= uc
->bchan
;
2029 static void bcdma_put_bchan(struct udma_chan
*uc
)
2031 struct udma_dev
*ud
= uc
->ud
;
2034 dev_dbg(ud
->dev
, "chan%d: put bchan%d\n", uc
->id
,
2036 __clear_bit(uc
->bchan
->id
, ud
->bchan_map
);
2042 static void bcdma_free_bchan_resources(struct udma_chan
*uc
)
2047 k3_nav_ringacc_ring_free(uc
->bchan
->tc_ring
);
2048 k3_nav_ringacc_ring_free(uc
->bchan
->t_ring
);
2049 uc
->bchan
->tc_ring
= NULL
;
2050 uc
->bchan
->t_ring
= NULL
;
2052 bcdma_put_bchan(uc
);
2055 static int bcdma_alloc_bchan_resources(struct udma_chan
*uc
)
2057 struct k3_nav_ring_cfg ring_cfg
;
2058 struct udma_dev
*ud
= uc
->ud
;
2061 ret
= bcdma_get_bchan(uc
);
2065 ret
= k3_nav_ringacc_request_rings_pair(ud
->ringacc
, uc
->bchan
->id
, -1,
2067 &uc
->bchan
->tc_ring
);
2073 memset(&ring_cfg
, 0, sizeof(ring_cfg
));
2075 ring_cfg
.elm_size
= K3_NAV_RINGACC_RING_ELSIZE_8
;
2076 ring_cfg
.mode
= K3_NAV_RINGACC_RING_MODE_RING
;
2078 ret
= k3_nav_ringacc_ring_cfg(uc
->bchan
->t_ring
, &ring_cfg
);
2085 k3_nav_ringacc_ring_free(uc
->bchan
->tc_ring
);
2086 uc
->bchan
->tc_ring
= NULL
;
2087 k3_nav_ringacc_ring_free(uc
->bchan
->t_ring
);
2088 uc
->bchan
->t_ring
= NULL
;
2090 bcdma_put_bchan(uc
);
2095 static int bcdma_tisci_tx_channel_config(struct udma_chan
*uc
)
2097 struct udma_dev
*ud
= uc
->ud
;
2098 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
2099 const struct ti_sci_rm_udmap_ops
*tisci_ops
= tisci_rm
->tisci_udmap_ops
;
2100 struct udma_tchan
*tchan
= uc
->tchan
;
2101 struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx
= { 0 };
2104 req_tx
.valid_params
= TISCI_BCDMA_TCHAN_VALID_PARAMS
;
2105 req_tx
.nav_id
= tisci_rm
->tisci_dev_id
;
2106 req_tx
.index
= tchan
->id
;
2107 req_tx
.tx_supr_tdpkt
= uc
->config
.notdpkt
;
2108 if (uc
->config
.ep_type
== PSIL_EP_PDMA_XY
&&
2109 ud
->match_data
->flags
& UDMA_FLAG_TDTYPE
) {
2110 /* wait for peer to complete the teardown for PDMAs */
2111 req_tx
.valid_params
|=
2112 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID
;
2113 req_tx
.tx_tdtype
= 1;
2116 ret
= tisci_ops
->tx_ch_cfg(tisci_rm
->tisci
, &req_tx
);
2118 dev_err(ud
->dev
, "tchan%d cfg failed %d\n", tchan
->id
, ret
);
2123 #define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
2125 static int pktdma_tisci_rx_channel_config(struct udma_chan
*uc
)
2127 struct udma_dev
*ud
= uc
->ud
;
2128 struct udma_tisci_rm
*tisci_rm
= &ud
->tisci_rm
;
2129 const struct ti_sci_rm_udmap_ops
*tisci_ops
= tisci_rm
->tisci_udmap_ops
;
2130 struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx
= { 0 };
2131 struct ti_sci_msg_rm_udmap_flow_cfg flow_req
= { 0 };
2134 req_rx
.valid_params
= TISCI_BCDMA_RCHAN_VALID_PARAMS
;
2135 req_rx
.nav_id
= tisci_rm
->tisci_dev_id
;
2136 req_rx
.index
= uc
->rchan
->id
;
2138 ret
= tisci_ops
->rx_ch_cfg(tisci_rm
->tisci
, &req_rx
);
2140 dev_err(ud
->dev
, "rchan%d cfg failed %d\n", uc
->rchan
->id
, ret
);
2144 flow_req
.valid_params
=
2145 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID
|
2146 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID
|
2147 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID
;
2149 flow_req
.nav_id
= tisci_rm
->tisci_dev_id
;
2150 flow_req
.flow_index
= uc
->rflow
->id
;
2152 if (uc
->config
.needs_epib
)
2153 flow_req
.rx_einfo_present
= 1;
2155 flow_req
.rx_einfo_present
= 0;
2156 if (uc
->config
.psd_size
)
2157 flow_req
.rx_psinfo_present
= 1;
2159 flow_req
.rx_psinfo_present
= 0;
2160 flow_req
.rx_error_handling
= 0;
2162 ret
= tisci_ops
->rx_flow_cfg(tisci_rm
->tisci
, &flow_req
);
2165 dev_err(ud
->dev
, "flow%d config failed: %d\n", uc
->rflow
->id
,
2171 static int bcdma_alloc_chan_resources(struct udma_chan
*uc
)
2175 uc
->config
.pkt_mode
= false;
2177 switch (uc
->config
.dir
) {
2178 case DMA_MEM_TO_MEM
:
2179 /* Non synchronized - mem to mem type of transfer */
2180 dev_dbg(uc
->ud
->dev
, "%s: chan%d as MEM-to-MEM\n", __func__
,
2183 ret
= bcdma_alloc_bchan_resources(uc
);
2187 ret
= bcdma_tisci_m2m_channel_config(uc
);
2190 /* Can not happen */
2191 dev_err(uc
->ud
->dev
, "%s: chan%d invalid direction (%u)\n",
2192 __func__
, uc
->id
, uc
->config
.dir
);
2196 /* check if the channel configuration was successful */
2200 if (udma_is_chan_running(uc
)) {
2201 dev_warn(uc
->ud
->dev
, "chan%d: is running!\n", uc
->id
);
2203 if (udma_is_chan_running(uc
)) {
2204 dev_err(uc
->ud
->dev
, "chan%d: won't stop!\n", uc
->id
);
2209 udma_reset_rings(uc
);
2214 bcdma_free_bchan_resources(uc
);
2215 udma_free_tx_resources(uc
);
2216 udma_free_rx_resources(uc
);
2218 udma_reset_uchan(uc
);
2223 static int pktdma_alloc_chan_resources(struct udma_chan
*uc
)
2225 struct udma_dev
*ud
= uc
->ud
;
2228 switch (uc
->config
.dir
) {
2229 case DMA_MEM_TO_DEV
:
2230 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
2231 dev_dbg(uc
->ud
->dev
, "%s: chan%d as MEM-to-DEV\n", __func__
,
2234 ret
= udma_alloc_tx_resources(uc
);
2236 uc
->config
.remote_thread_id
= -1;
2240 uc
->config
.src_thread
= ud
->psil_base
+ uc
->tchan
->id
;
2241 uc
->config
.dst_thread
= uc
->config
.remote_thread_id
;
2242 uc
->config
.dst_thread
|= K3_PSIL_DST_THREAD_ID_OFFSET
;
2244 ret
= pktdma_tisci_tx_channel_config(uc
);
2246 case DMA_DEV_TO_MEM
:
2247 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
2248 dev_dbg(uc
->ud
->dev
, "%s: chan%d as DEV-to-MEM\n", __func__
,
2251 ret
= udma_alloc_rx_resources(uc
);
2253 uc
->config
.remote_thread_id
= -1;
2257 uc
->config
.src_thread
= uc
->config
.remote_thread_id
;
2258 uc
->config
.dst_thread
= (ud
->psil_base
+ uc
->rchan
->id
) |
2259 K3_PSIL_DST_THREAD_ID_OFFSET
;
2261 ret
= pktdma_tisci_rx_channel_config(uc
);
2264 /* Can not happen */
2265 dev_err(uc
->ud
->dev
, "%s: chan%d invalid direction (%u)\n",
2266 __func__
, uc
->id
, uc
->config
.dir
);
2270 /* check if the channel configuration was successful */
2275 ret
= udma_navss_psil_pair(ud
, uc
->config
.src_thread
, uc
->config
.dst_thread
);
2277 dev_err(ud
->dev
, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
2278 uc
->config
.src_thread
, uc
->config
.dst_thread
);
2282 if (udma_is_chan_running(uc
)) {
2283 dev_warn(ud
->dev
, "chan%d: is running!\n", uc
->id
);
2285 if (udma_is_chan_running(uc
)) {
2286 dev_err(ud
->dev
, "chan%d: won't stop!\n", uc
->id
);
2291 udma_reset_rings(uc
);
2295 "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
2296 uc
->id
, uc
->tchan
->id
, uc
->tchan
->tflow_id
,
2297 uc
->config
.remote_thread_id
);
2300 "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
2301 uc
->id
, uc
->rchan
->id
, uc
->rflow
->id
,
2302 uc
->config
.remote_thread_id
);
2306 udma_free_tx_resources(uc
);
2307 udma_free_rx_resources(uc
);
2309 udma_reset_uchan(uc
);
2314 static int udma_transfer(struct udevice
*dev
, int direction
,
2315 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2317 struct udma_dev
*ud
= dev_get_priv(dev
);
2318 /* Channel0 is reserved for memcpy */
2319 struct udma_chan
*uc
= &ud
->channels
[0];
2320 dma_addr_t paddr
= 0;
2323 switch (ud
->match_data
->type
) {
2325 ret
= udma_alloc_chan_resources(uc
);
2327 case DMA_TYPE_BCDMA
:
2328 ret
= bcdma_alloc_chan_resources(uc
);
2336 udma_prep_dma_memcpy(uc
, dst
, src
, len
);
2338 udma_poll_completion(uc
, &paddr
);
2341 switch (ud
->match_data
->type
) {
2343 udma_free_chan_resources(uc
);
2345 case DMA_TYPE_BCDMA
:
2346 bcdma_free_bchan_resources(uc
);
2355 static int udma_request(struct dma
*dma
)
2357 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2358 struct udma_chan_config
*ucc
;
2359 struct udma_chan
*uc
;
2360 unsigned long dummy
;
2363 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2364 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2368 uc
= &ud
->channels
[dma
->id
];
2370 switch (ud
->match_data
->type
) {
2372 ret
= udma_alloc_chan_resources(uc
);
2374 case DMA_TYPE_BCDMA
:
2375 ret
= bcdma_alloc_chan_resources(uc
);
2377 case DMA_TYPE_PKTDMA
:
2378 ret
= pktdma_alloc_chan_resources(uc
);
2384 dev_err(dma
->dev
, "alloc dma res failed %d\n", ret
);
2388 if (uc
->config
.dir
== DMA_MEM_TO_DEV
) {
2389 uc
->desc_tx
= dma_alloc_coherent(ucc
->hdesc_size
, &dummy
);
2390 memset(uc
->desc_tx
, 0, ucc
->hdesc_size
);
2392 uc
->desc_rx
= dma_alloc_coherent(
2393 ucc
->hdesc_size
* UDMA_RX_DESC_NUM
, &dummy
);
2394 memset(uc
->desc_rx
, 0, ucc
->hdesc_size
* UDMA_RX_DESC_NUM
);
2398 uc
->desc_rx_cur
= 0;
2399 uc
->num_rx_bufs
= 0;
2401 if (uc
->config
.dir
== DMA_DEV_TO_MEM
) {
2402 uc
->cfg_data
.flow_id_base
= uc
->rflow
->id
;
2403 uc
->cfg_data
.flow_id_cnt
= 1;
2409 static int udma_rfree(struct dma
*dma
)
2411 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2412 struct udma_chan
*uc
;
2414 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2415 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2418 uc
= &ud
->channels
[dma
->id
];
2420 if (udma_is_chan_running(uc
))
2423 udma_navss_psil_unpair(ud
, uc
->config
.src_thread
,
2424 uc
->config
.dst_thread
);
2426 bcdma_free_bchan_resources(uc
);
2427 udma_free_tx_resources(uc
);
2428 udma_free_rx_resources(uc
);
2429 udma_reset_uchan(uc
);
2436 static int udma_enable(struct dma
*dma
)
2438 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2439 struct udma_chan
*uc
;
2442 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2443 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2446 uc
= &ud
->channels
[dma
->id
];
2448 ret
= udma_start(uc
);
2453 static int udma_disable(struct dma
*dma
)
2455 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2456 struct udma_chan
*uc
;
2459 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2460 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2463 uc
= &ud
->channels
[dma
->id
];
2465 if (udma_is_chan_running(uc
))
2466 ret
= udma_stop(uc
);
2468 dev_err(dma
->dev
, "%s not running\n", __func__
);
2473 static int udma_send(struct dma
*dma
, void *src
, size_t len
, void *metadata
)
2475 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2476 struct cppi5_host_desc_t
*desc_tx
;
2477 dma_addr_t dma_src
= (dma_addr_t
)src
;
2478 struct ti_udma_drv_packet_data packet_data
= { 0 };
2480 struct udma_chan
*uc
;
2485 packet_data
= *((struct ti_udma_drv_packet_data
*)metadata
);
2487 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2488 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2491 uc
= &ud
->channels
[dma
->id
];
2493 if (uc
->config
.dir
!= DMA_MEM_TO_DEV
)
2496 tc_ring_id
= k3_nav_ringacc_get_ring_id(uc
->tchan
->tc_ring
);
2498 desc_tx
= uc
->desc_tx
;
2500 cppi5_hdesc_reset_hbdesc(desc_tx
);
2502 cppi5_hdesc_init(desc_tx
,
2503 uc
->config
.needs_epib
? CPPI5_INFO0_HDESC_EPIB_PRESENT
: 0,
2504 uc
->config
.psd_size
);
2505 cppi5_hdesc_set_pktlen(desc_tx
, len
);
2506 cppi5_hdesc_attach_buf(desc_tx
, dma_src
, len
, dma_src
, len
);
2507 cppi5_desc_set_pktids(&desc_tx
->hdr
, uc
->id
, 0x3fff);
2508 cppi5_desc_set_retpolicy(&desc_tx
->hdr
, 0, tc_ring_id
);
2509 /* pass below information from caller */
2510 cppi5_hdesc_set_pkttype(desc_tx
, packet_data
.pkt_type
);
2511 cppi5_desc_set_tags_ids(&desc_tx
->hdr
, 0, packet_data
.dest_tag
);
2513 flush_dcache_range((unsigned long)dma_src
,
2514 ALIGN((unsigned long)dma_src
+ len
,
2515 ARCH_DMA_MINALIGN
));
2516 flush_dcache_range((unsigned long)desc_tx
,
2517 ALIGN((unsigned long)desc_tx
+ uc
->config
.hdesc_size
,
2518 ARCH_DMA_MINALIGN
));
2520 ret
= udma_push_to_ring(uc
->tchan
->t_ring
, uc
->desc_tx
);
2522 dev_err(dma
->dev
, "TX dma push fail ch_id %lu %d\n",
2527 udma_poll_completion(uc
, &paddr
);
2532 static int udma_receive(struct dma
*dma
, void **dst
, void *metadata
)
2534 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2535 struct udma_chan_config
*ucc
;
2536 struct cppi5_host_desc_t
*desc_rx
;
2538 struct udma_chan
*uc
;
2539 u32 buf_dma_len
, pkt_len
;
2543 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2544 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2547 uc
= &ud
->channels
[dma
->id
];
2550 if (uc
->config
.dir
!= DMA_DEV_TO_MEM
)
2552 if (!uc
->num_rx_bufs
)
2555 ret
= k3_nav_ringacc_ring_pop(uc
->rflow
->r_ring
, &desc_rx
);
2556 if (ret
&& ret
!= -ENODATA
) {
2557 dev_err(dma
->dev
, "rx dma fail ch_id:%lu %d\n", dma
->id
, ret
);
2559 } else if (ret
== -ENODATA
) {
2563 /* invalidate cache data */
2564 invalidate_dcache_range((ulong
)desc_rx
,
2565 (ulong
)(desc_rx
+ ucc
->hdesc_size
));
2567 cppi5_hdesc_get_obuf(desc_rx
, &buf_dma
, &buf_dma_len
);
2568 pkt_len
= cppi5_hdesc_get_pktlen(desc_rx
);
2570 /* invalidate cache data */
2571 invalidate_dcache_range((ulong
)buf_dma
,
2572 (ulong
)(buf_dma
+ buf_dma_len
));
2574 cppi5_desc_get_tags_ids(&desc_rx
->hdr
, &port_id
, NULL
);
2576 *dst
= (void *)buf_dma
;
2582 static int udma_of_xlate(struct dma
*dma
, struct ofnode_phandle_args
*args
)
2584 struct udma_chan_config
*ucc
;
2585 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2586 struct udma_chan
*uc
= &ud
->channels
[0];
2587 struct psil_endpoint_config
*ep_config
;
2590 for (val
= 0; val
< ud
->ch_count
; val
++) {
2591 uc
= &ud
->channels
[val
];
2596 if (val
== ud
->ch_count
)
2600 ucc
->remote_thread_id
= args
->args
[0];
2601 if (ucc
->remote_thread_id
& K3_PSIL_DST_THREAD_ID_OFFSET
)
2602 ucc
->dir
= DMA_MEM_TO_DEV
;
2604 ucc
->dir
= DMA_DEV_TO_MEM
;
2606 ep_config
= psil_get_ep_config(ucc
->remote_thread_id
);
2607 if (IS_ERR(ep_config
)) {
2608 dev_err(ud
->dev
, "No configuration for psi-l thread 0x%04x\n",
2609 uc
->config
.remote_thread_id
);
2610 ucc
->dir
= DMA_MEM_TO_MEM
;
2611 ucc
->remote_thread_id
= -1;
2615 ucc
->pkt_mode
= ep_config
->pkt_mode
;
2616 ucc
->channel_tpl
= ep_config
->channel_tpl
;
2617 ucc
->notdpkt
= ep_config
->notdpkt
;
2618 ucc
->ep_type
= ep_config
->ep_type
;
2620 if (ud
->match_data
->type
== DMA_TYPE_PKTDMA
&&
2621 ep_config
->mapped_channel_id
>= 0) {
2622 ucc
->mapped_channel_id
= ep_config
->mapped_channel_id
;
2623 ucc
->default_flow_id
= ep_config
->default_flow_id
;
2625 ucc
->mapped_channel_id
= -1;
2626 ucc
->default_flow_id
= -1;
2629 ucc
->needs_epib
= ep_config
->needs_epib
;
2630 ucc
->psd_size
= ep_config
->psd_size
;
2631 ucc
->metadata_size
= (ucc
->needs_epib
? CPPI5_INFO0_HDESC_EPIB_SIZE
: 0) + ucc
->psd_size
;
2633 ucc
->hdesc_size
= cppi5_hdesc_calc_size(ucc
->needs_epib
,
2635 ucc
->hdesc_size
= ALIGN(ucc
->hdesc_size
, ARCH_DMA_MINALIGN
);
2638 pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
2639 dma
->id
, ucc
->needs_epib
,
2640 ucc
->psd_size
, ucc
->metadata_size
,
2641 ucc
->remote_thread_id
);
2646 int udma_prepare_rcv_buf(struct dma
*dma
, void *dst
, size_t size
)
2648 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2649 struct cppi5_host_desc_t
*desc_rx
;
2651 struct udma_chan
*uc
;
2654 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2655 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2658 uc
= &ud
->channels
[dma
->id
];
2660 if (uc
->config
.dir
!= DMA_DEV_TO_MEM
)
2663 if (uc
->num_rx_bufs
>= UDMA_RX_DESC_NUM
)
2666 desc_num
= uc
->desc_rx_cur
% UDMA_RX_DESC_NUM
;
2667 desc_rx
= uc
->desc_rx
+ (desc_num
* uc
->config
.hdesc_size
);
2668 dma_dst
= (dma_addr_t
)dst
;
2670 cppi5_hdesc_reset_hbdesc(desc_rx
);
2672 cppi5_hdesc_init(desc_rx
,
2673 uc
->config
.needs_epib
? CPPI5_INFO0_HDESC_EPIB_PRESENT
: 0,
2674 uc
->config
.psd_size
);
2675 cppi5_hdesc_set_pktlen(desc_rx
, size
);
2676 cppi5_hdesc_attach_buf(desc_rx
, dma_dst
, size
, dma_dst
, size
);
2678 flush_dcache_range((unsigned long)desc_rx
,
2679 ALIGN((unsigned long)desc_rx
+ uc
->config
.hdesc_size
,
2680 ARCH_DMA_MINALIGN
));
2682 udma_push_to_ring(uc
->rflow
->fd_ring
, desc_rx
);
2690 static int udma_get_cfg(struct dma
*dma
, u32 id
, void **data
)
2692 struct udma_dev
*ud
= dev_get_priv(dma
->dev
);
2693 struct udma_chan
*uc
;
2695 if (dma
->id
>= (ud
->rchan_cnt
+ ud
->tchan_cnt
)) {
2696 dev_err(dma
->dev
, "invalid dma ch_id %lu\n", dma
->id
);
2701 case TI_UDMA_CHAN_PRIV_INFO
:
2702 uc
= &ud
->channels
[dma
->id
];
2703 *data
= &uc
->cfg_data
;
2710 static const struct dma_ops udma_ops
= {
2711 .transfer
= udma_transfer
,
2712 .of_xlate
= udma_of_xlate
,
2713 .request
= udma_request
,
2714 .rfree
= udma_rfree
,
2715 .enable
= udma_enable
,
2716 .disable
= udma_disable
,
2718 .receive
= udma_receive
,
2719 .prepare_rcv_buf
= udma_prepare_rcv_buf
,
2720 .get_cfg
= udma_get_cfg
,
2723 static struct udma_match_data am654_main_data
= {
2724 .type
= DMA_TYPE_UDMA
,
2725 .psil_base
= 0x1000,
2726 .enable_memcpy_support
= true,
2727 .statictr_z_mask
= GENMASK(11, 0),
2729 .udma_rchan
= 0x200,
2732 .level_start_idx
= {
2733 [0] = 8, /* Normal channels */
2734 [1] = 0, /* High Throughput channels */
2738 static struct udma_match_data am654_mcu_data
= {
2739 .type
= DMA_TYPE_UDMA
,
2740 .psil_base
= 0x6000,
2741 .enable_memcpy_support
= true,
2742 .statictr_z_mask
= GENMASK(11, 0),
2744 .udma_rchan
= 0x200,
2747 .level_start_idx
= {
2748 [0] = 2, /* Normal channels */
2749 [1] = 0, /* High Throughput channels */
2753 static struct udma_match_data j721e_main_data
= {
2754 .type
= DMA_TYPE_UDMA
,
2755 .psil_base
= 0x1000,
2756 .enable_memcpy_support
= true,
2757 .flags
= UDMA_FLAG_PDMA_ACC32
| UDMA_FLAG_PDMA_BURST
| UDMA_FLAG_TDTYPE
,
2758 .statictr_z_mask
= GENMASK(23, 0),
2760 .udma_rchan
= 0x400,
2763 .level_start_idx
= {
2764 [0] = 16, /* Normal channels */
2765 [1] = 4, /* High Throughput channels */
2766 [2] = 0, /* Ultra High Throughput channels */
2770 static struct udma_match_data j721e_mcu_data
= {
2771 .type
= DMA_TYPE_UDMA
,
2772 .psil_base
= 0x6000,
2773 .enable_memcpy_support
= true,
2774 .flags
= UDMA_FLAG_PDMA_ACC32
| UDMA_FLAG_PDMA_BURST
| UDMA_FLAG_TDTYPE
,
2775 .statictr_z_mask
= GENMASK(23, 0),
2777 .udma_rchan
= 0x400,
2780 .level_start_idx
= {
2781 [0] = 2, /* Normal channels */
2782 [1] = 0, /* High Throughput channels */
2786 static struct udma_match_data am64_bcdma_data
= {
2787 .type
= DMA_TYPE_BCDMA
,
2788 .psil_base
= 0x2000, /* for tchan and rchan, not applicable to bchan */
2789 .enable_memcpy_support
= true, /* Supported via bchan */
2790 .flags
= UDMA_FLAG_PDMA_ACC32
| UDMA_FLAG_PDMA_BURST
| UDMA_FLAG_TDTYPE
,
2791 .statictr_z_mask
= GENMASK(23, 0),
2793 .bcdma_bchan_data
= 0x2200,
2794 .bcdma_bchan_ring
= 0x2400,
2795 .bcdma_tchan_data
= 0x2800,
2796 .bcdma_tchan_ring
= 0x2a00,
2797 .bcdma_rchan_data
= 0x2e00,
2798 .bcdma_rchan_ring
= 0x3000,
2800 /* No throughput levels */
2803 static struct udma_match_data am64_pktdma_data
= {
2804 .type
= DMA_TYPE_PKTDMA
,
2805 .psil_base
= 0x1000,
2806 .enable_memcpy_support
= false,
2807 .flags
= UDMA_FLAG_PDMA_ACC32
| UDMA_FLAG_PDMA_BURST
| UDMA_FLAG_TDTYPE
,
2808 .statictr_z_mask
= GENMASK(23, 0),
2810 .pktdma_tchan_flow
= 0x1200,
2811 .pktdma_rchan_flow
= 0x1600,
2813 /* No throughput levels */
2816 static const struct udevice_id udma_ids
[] = {
2818 .compatible
= "ti,am654-navss-main-udmap",
2819 .data
= (ulong
)&am654_main_data
,
2822 .compatible
= "ti,am654-navss-mcu-udmap",
2823 .data
= (ulong
)&am654_mcu_data
,
2825 .compatible
= "ti,j721e-navss-main-udmap",
2826 .data
= (ulong
)&j721e_main_data
,
2828 .compatible
= "ti,j721e-navss-mcu-udmap",
2829 .data
= (ulong
)&j721e_mcu_data
,
2832 .compatible
= "ti,am64-dmss-bcdma",
2833 .data
= (ulong
)&am64_bcdma_data
,
2836 .compatible
= "ti,am64-dmss-pktdma",
2837 .data
= (ulong
)&am64_pktdma_data
,
2842 U_BOOT_DRIVER(ti_edma3
) = {
2845 .of_match
= udma_ids
,
2847 .probe
= udma_probe
,
2848 .priv_auto
= sizeof(struct udma_dev
),