1 // SPDX-License-Identifier: GPL-2.0+
3 * Enhanced Direct Memory Access (EDMA3) Controller
6 * Texas Instruments Incorporated, <www.ti.com>
8 * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
14 #include <dma-uclass.h>
15 #include <asm/omap_common.h>
16 #include <asm/ti-common/ti-edma3.h>
18 #define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
19 #define EDMA3_SL_MAX_NUM 512
20 #define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8)
22 #define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2)
23 #define EDMA3_CHMAP_PARSET_MASK 0x1ff
24 #define EDMA3_CHMAP_PARSET_SHIFT 0x5
25 #define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2
27 #define EDMA3_QEMCR 0x314
28 #define EDMA3_IPR 0x1068
29 #define EDMA3_IPRH 0x106c
30 #define EDMA3_ICR 0x1070
31 #define EDMA3_ICRH 0x1074
32 #define EDMA3_QEECR 0x1088
33 #define EDMA3_QEESR 0x108c
34 #define EDMA3_QSECR 0x1094
36 #define EDMA_FILL_BUFFER_SIZE 512
38 struct ti_edma3_priv
{
42 static u8 edma_fill_buffer
[EDMA_FILL_BUFFER_SIZE
] __aligned(ARCH_DMA_MINALIGN
);
45 * qedma3_start - start qdma on a channel
46 * @base: base address of edma
47 * @cfg: pinter to struct edma3_channel_config where you can set
48 * the slot number to associate with, the chnum, which corresponds
49 * your quick channel number 0-7, complete code - transfer complete code
50 * and trigger slot word - which has to correspond to the word number in
51 * edma3_slot_layout struct for generating event.
54 void qedma3_start(u32 base
, struct edma3_channel_config
*cfg
)
58 /* Clear the pending int bit */
59 if (cfg
->complete_code
< 32)
60 __raw_writel(1 << cfg
->complete_code
, base
+ EDMA3_ICR
);
62 __raw_writel(1 << cfg
->complete_code
, base
+ EDMA3_ICRH
);
64 /* Map parameter set and trigger word 7 to quick channel */
65 qchmap
= ((EDMA3_CHMAP_PARSET_MASK
& cfg
->slot
)
66 << EDMA3_CHMAP_PARSET_SHIFT
) |
67 (cfg
->trigger_slot_word
<< EDMA3_CHMAP_TRIGWORD_SHIFT
);
69 __raw_writel(qchmap
, base
+ EDMA3_QCHMAP(cfg
->chnum
));
71 /* Clear missed event if set*/
72 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QSECR
);
73 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QEMCR
);
75 /* Enable qdma channel event */
76 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QEESR
);
80 * edma3_set_dest - set initial DMA destination address in parameter RAM slot
81 * @base: base address of edma
82 * @slot: parameter RAM slot being configured
83 * @dst: physical address of destination (memory, controller FIFO, etc)
84 * @addressMode: INCR, except in very rare cases
85 * @width: ignored unless @addressMode is FIFO, else specifies the
86 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
88 * Note that the destination address is modified during the DMA transfer
89 * according to edma3_set_dest_index().
91 void edma3_set_dest(u32 base
, int slot
, u32 dst
, enum edma3_address_mode mode
,
92 enum edma3_fifo_width width
)
95 struct edma3_slot_layout
*rg
;
97 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
99 opt
= __raw_readl(&rg
->opt
);
101 opt
= (opt
& EDMA3_SLOPT_FIFO_WIDTH_MASK
) |
102 (EDMA3_SLOPT_DST_ADDR_CONST_MODE
|
103 EDMA3_SLOPT_FIFO_WIDTH_SET(width
));
105 opt
&= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE
;
107 __raw_writel(opt
, &rg
->opt
);
108 __raw_writel(dst
, &rg
->dst
);
112 * edma3_set_dest_index - configure DMA destination address indexing
113 * @base: base address of edma
114 * @slot: parameter RAM slot being configured
115 * @bidx: byte offset between destination arrays in a frame
116 * @cidx: byte offset between destination frames in a block
118 * Offsets are specified to support either contiguous or discontiguous
119 * memory transfers, or repeated access to a hardware register, as needed.
120 * When accessing hardware registers, both offsets are normally zero.
122 void edma3_set_dest_index(u32 base
, unsigned slot
, int bidx
, int cidx
)
126 struct edma3_slot_layout
*rg
;
128 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
130 src_dst_bidx
= __raw_readl(&rg
->src_dst_bidx
);
131 src_dst_cidx
= __raw_readl(&rg
->src_dst_cidx
);
133 __raw_writel((src_dst_bidx
& 0x0000ffff) | (bidx
<< 16),
135 __raw_writel((src_dst_cidx
& 0x0000ffff) | (cidx
<< 16),
140 * edma3_set_dest_addr - set destination address for slot only
142 void edma3_set_dest_addr(u32 base
, int slot
, u32 dst
)
144 struct edma3_slot_layout
*rg
;
146 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
147 __raw_writel(dst
, &rg
->dst
);
151 * edma3_set_src - set initial DMA source address in parameter RAM slot
152 * @base: base address of edma
153 * @slot: parameter RAM slot being configured
154 * @src_port: physical address of source (memory, controller FIFO, etc)
155 * @mode: INCR, except in very rare cases
156 * @width: ignored unless @addressMode is FIFO, else specifies the
157 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
159 * Note that the source address is modified during the DMA transfer
160 * according to edma3_set_src_index().
162 void edma3_set_src(u32 base
, int slot
, u32 src
, enum edma3_address_mode mode
,
163 enum edma3_fifo_width width
)
166 struct edma3_slot_layout
*rg
;
168 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
170 opt
= __raw_readl(&rg
->opt
);
172 opt
= (opt
& EDMA3_SLOPT_FIFO_WIDTH_MASK
) |
173 (EDMA3_SLOPT_DST_ADDR_CONST_MODE
|
174 EDMA3_SLOPT_FIFO_WIDTH_SET(width
));
176 opt
&= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE
;
178 __raw_writel(opt
, &rg
->opt
);
179 __raw_writel(src
, &rg
->src
);
183 * edma3_set_src_index - configure DMA source address indexing
184 * @base: base address of edma
185 * @slot: parameter RAM slot being configured
186 * @bidx: byte offset between source arrays in a frame
187 * @cidx: byte offset between source frames in a block
189 * Offsets are specified to support either contiguous or discontiguous
190 * memory transfers, or repeated access to a hardware register, as needed.
191 * When accessing hardware registers, both offsets are normally zero.
193 void edma3_set_src_index(u32 base
, unsigned slot
, int bidx
, int cidx
)
197 struct edma3_slot_layout
*rg
;
199 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
201 src_dst_bidx
= __raw_readl(&rg
->src_dst_bidx
);
202 src_dst_cidx
= __raw_readl(&rg
->src_dst_cidx
);
204 __raw_writel((src_dst_bidx
& 0xffff0000) | bidx
,
206 __raw_writel((src_dst_cidx
& 0xffff0000) | cidx
,
211 * edma3_set_src_addr - set source address for slot only
213 void edma3_set_src_addr(u32 base
, int slot
, u32 src
)
215 struct edma3_slot_layout
*rg
;
217 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
218 __raw_writel(src
, &rg
->src
);
222 * edma3_set_transfer_params - configure DMA transfer parameters
223 * @base: base address of edma
224 * @slot: parameter RAM slot being configured
225 * @acnt: how many bytes per array (at least one)
226 * @bcnt: how many arrays per frame (at least one)
227 * @ccnt: how many frames per block (at least one)
228 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
229 * the value to reload into bcnt when it decrements to zero
230 * @sync_mode: ASYNC or ABSYNC
232 * See the EDMA3 documentation to understand how to configure and link
233 * transfers using the fields in PaRAM slots. If you are not doing it
234 * all at once with edma3_write_slot(), you will use this routine
235 * plus two calls each for source and destination, setting the initial
236 * address and saying how to index that address.
238 * An example of an A-Synchronized transfer is a serial link using a
239 * single word shift register. In that case, @acnt would be equal to
240 * that word size; the serial controller issues a DMA synchronization
241 * event to transfer each word, and memory access by the DMA transfer
242 * controller will be word-at-a-time.
244 * An example of an AB-Synchronized transfer is a device using a FIFO.
245 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
246 * The controller with the FIFO issues DMA synchronization events when
247 * the FIFO threshold is reached, and the DMA transfer controller will
248 * transfer one frame to (or from) the FIFO. It will probably use
249 * efficient burst modes to access memory.
251 void edma3_set_transfer_params(u32 base
, int slot
, int acnt
,
252 int bcnt
, int ccnt
, u16 bcnt_rld
,
253 enum edma3_sync_dimension sync_mode
)
257 struct edma3_slot_layout
*rg
;
259 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
261 link_bcntrld
= __raw_readl(&rg
->link_bcntrld
);
263 __raw_writel((bcnt_rld
<< 16) | (0x0000ffff & link_bcntrld
),
266 opt
= __raw_readl(&rg
->opt
);
267 if (sync_mode
== ASYNC
)
268 __raw_writel(opt
& ~EDMA3_SLOPT_AB_SYNC
, &rg
->opt
);
270 __raw_writel(opt
| EDMA3_SLOPT_AB_SYNC
, &rg
->opt
);
272 /* Set the acount, bcount, ccount registers */
273 __raw_writel((bcnt
<< 16) | (acnt
& 0xffff), &rg
->a_b_cnt
);
274 __raw_writel(0xffff & ccnt
, &rg
->ccnt
);
278 * edma3_write_slot - write parameter RAM data for slot
279 * @base: base address of edma
280 * @slot: number of parameter RAM slot being modified
281 * @param: data to be written into parameter RAM slot
283 * Use this to assign all parameters of a transfer at once. This
284 * allows more efficient setup of transfers than issuing multiple
285 * calls to set up those parameters in small pieces, and provides
286 * complete control over all transfer options.
288 void edma3_write_slot(u32 base
, int slot
, struct edma3_slot_layout
*param
)
291 u32
*p
= (u32
*)param
;
292 u32
*addr
= (u32
*)(base
+ EDMA3_SL_BASE(slot
));
294 for (i
= 0; i
< sizeof(struct edma3_slot_layout
)/4; i
+= 4)
295 __raw_writel(*p
++, addr
++);
299 * edma3_read_slot - read parameter RAM data from slot
300 * @base: base address of edma
301 * @slot: number of parameter RAM slot being copied
302 * @param: where to store copy of parameter RAM data
304 * Use this to read data from a parameter RAM slot, perhaps to
305 * save them as a template for later reuse.
307 void edma3_read_slot(u32 base
, int slot
, struct edma3_slot_layout
*param
)
310 u32
*p
= (u32
*)param
;
311 u32
*addr
= (u32
*)(base
+ EDMA3_SL_BASE(slot
));
313 for (i
= 0; i
< sizeof(struct edma3_slot_layout
)/4; i
+= 4)
314 *p
++ = __raw_readl(addr
++);
317 void edma3_slot_configure(u32 base
, int slot
, struct edma3_slot_config
*cfg
)
319 struct edma3_slot_layout
*rg
;
321 rg
= (struct edma3_slot_layout
*)(base
+ EDMA3_SL_BASE(slot
));
323 __raw_writel(cfg
->opt
, &rg
->opt
);
324 __raw_writel(cfg
->src
, &rg
->src
);
325 __raw_writel((cfg
->bcnt
<< 16) | (cfg
->acnt
& 0xffff), &rg
->a_b_cnt
);
326 __raw_writel(cfg
->dst
, &rg
->dst
);
327 __raw_writel((cfg
->dst_bidx
<< 16) |
328 (cfg
->src_bidx
& 0xffff), &rg
->src_dst_bidx
);
329 __raw_writel((cfg
->bcntrld
<< 16) |
330 (cfg
->link
& 0xffff), &rg
->link_bcntrld
);
331 __raw_writel((cfg
->dst_cidx
<< 16) |
332 (cfg
->src_cidx
& 0xffff), &rg
->src_dst_cidx
);
333 __raw_writel(0xffff & cfg
->ccnt
, &rg
->ccnt
);
337 * edma3_check_for_transfer - check if transfer coplete by checking
338 * interrupt pending bit. Clear interrupt pending bit if complete.
339 * @base: base address of edma
340 * @cfg: pinter to struct edma3_channel_config which was passed
341 * to qedma3_start when you started qdma channel
343 * Return 0 if complete, 1 if not.
345 int edma3_check_for_transfer(u32 base
, struct edma3_channel_config
*cfg
)
351 if (cfg
->complete_code
< 32) {
352 ipr_base
= base
+ EDMA3_IPR
;
353 icr_base
= base
+ EDMA3_ICR
;
354 inum
= 1 << cfg
->complete_code
;
356 ipr_base
= base
+ EDMA3_IPRH
;
357 icr_base
= base
+ EDMA3_ICRH
;
358 inum
= 1 << (cfg
->complete_code
- 32);
361 /* check complete interrupt */
362 if (!(__raw_readl(ipr_base
) & inum
))
365 /* clean up the pending int bit */
366 __raw_writel(inum
, icr_base
);
372 * qedma3_stop - stops dma on the channel passed
373 * @base: base address of edma
374 * @cfg: pinter to struct edma3_channel_config which was passed
375 * to qedma3_start when you started qdma channel
377 void qedma3_stop(u32 base
, struct edma3_channel_config
*cfg
)
379 /* Disable qdma channel event */
380 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QEECR
);
382 /* clean up the interrupt indication */
383 if (cfg
->complete_code
< 32)
384 __raw_writel(1 << cfg
->complete_code
, base
+ EDMA3_ICR
);
386 __raw_writel(1 << cfg
->complete_code
, base
+ EDMA3_ICRH
);
388 /* Clear missed event if set*/
389 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QSECR
);
390 __raw_writel(1 << cfg
->chnum
, base
+ EDMA3_QEMCR
);
392 /* Clear the channel map */
393 __raw_writel(0, base
+ EDMA3_QCHMAP(cfg
->chnum
));
396 void __edma3_transfer(unsigned long edma3_base_addr
, unsigned int edma_slot_num
,
397 void *dst
, void *src
, size_t len
, size_t s_len
)
399 struct edma3_slot_config slot
;
400 struct edma3_channel_config edma_channel
;
403 int a_cnt_value
= len
;
404 unsigned int addr
= (unsigned int) (dst
);
405 unsigned int max_acnt
= 0x7FFFU
;
408 b_cnt_value
= (len
/ s_len
);
409 rem_bytes
= (len
% s_len
);
411 } else if (len
> max_acnt
) {
412 b_cnt_value
= (len
/ max_acnt
);
413 rem_bytes
= (len
% max_acnt
);
414 a_cnt_value
= max_acnt
;
418 slot
.src
= ((unsigned int) src
);
419 slot
.acnt
= a_cnt_value
;
420 slot
.bcnt
= b_cnt_value
;
423 slot
.src_bidx
= a_cnt_value
;
426 slot
.dst_bidx
= a_cnt_value
;
429 slot
.link
= EDMA3_PARSET_NULL_LINK
;
431 slot
.opt
= EDMA3_SLOPT_TRANS_COMP_INT_ENB
|
432 EDMA3_SLOPT_COMP_CODE(0) |
433 EDMA3_SLOPT_STATIC
| EDMA3_SLOPT_AB_SYNC
;
435 edma3_slot_configure(edma3_base_addr
, edma_slot_num
, &slot
);
436 edma_channel
.slot
= edma_slot_num
;
437 edma_channel
.chnum
= 0;
438 edma_channel
.complete_code
= 0;
439 /* set event trigger to dst update */
440 edma_channel
.trigger_slot_word
= EDMA3_TWORD(dst
);
442 qedma3_start(edma3_base_addr
, &edma_channel
);
443 edma3_set_dest_addr(edma3_base_addr
, edma_channel
.slot
, addr
);
445 while (edma3_check_for_transfer(edma3_base_addr
, &edma_channel
))
447 qedma3_stop(edma3_base_addr
, &edma_channel
);
449 if (rem_bytes
!= 0) {
453 (b_cnt_value
* max_acnt
) + ((unsigned int) src
);
455 slot
.src
= (unsigned int) src
;
456 slot
.acnt
= rem_bytes
;
459 slot
.src_bidx
= rem_bytes
;
460 slot
.dst_bidx
= rem_bytes
;
463 slot
.link
= EDMA3_PARSET_NULL_LINK
;
465 slot
.opt
= EDMA3_SLOPT_TRANS_COMP_INT_ENB
|
466 EDMA3_SLOPT_COMP_CODE(0) |
467 EDMA3_SLOPT_STATIC
| EDMA3_SLOPT_AB_SYNC
;
468 edma3_slot_configure(edma3_base_addr
, edma_slot_num
, &slot
);
469 edma_channel
.slot
= edma_slot_num
;
470 edma_channel
.chnum
= 0;
471 edma_channel
.complete_code
= 0;
472 /* set event trigger to dst update */
473 edma_channel
.trigger_slot_word
= EDMA3_TWORD(dst
);
475 qedma3_start(edma3_base_addr
, &edma_channel
);
476 edma3_set_dest_addr(edma3_base_addr
, edma_channel
.slot
, addr
+
477 (max_acnt
* b_cnt_value
));
478 while (edma3_check_for_transfer(edma3_base_addr
, &edma_channel
))
480 qedma3_stop(edma3_base_addr
, &edma_channel
);
484 void __edma3_fill(unsigned long edma3_base_addr
, unsigned int edma_slot_num
,
485 void *dst
, u8 val
, size_t len
)
488 int max_xfer
= EDMA_FILL_BUFFER_SIZE
* 65535;
490 memset((void *)edma_fill_buffer
, val
, sizeof(edma_fill_buffer
));
494 if (xfer_len
> max_xfer
)
497 __edma3_transfer(edma3_base_addr
, edma_slot_num
, dst
,
498 edma_fill_buffer
, xfer_len
,
499 EDMA_FILL_BUFFER_SIZE
);
507 void edma3_transfer(unsigned long edma3_base_addr
, unsigned int edma_slot_num
,
508 void *dst
, void *src
, size_t len
)
510 __edma3_transfer(edma3_base_addr
, edma_slot_num
, dst
, src
, len
, len
);
513 void edma3_fill(unsigned long edma3_base_addr
, unsigned int edma_slot_num
,
514 void *dst
, u8 val
, size_t len
)
516 __edma3_fill(edma3_base_addr
, edma_slot_num
, dst
, val
, len
);
521 static int ti_edma3_transfer(struct udevice
*dev
, int direction
, void *dst
,
522 void *src
, size_t len
)
524 struct ti_edma3_priv
*priv
= dev_get_priv(dev
);
526 /* enable edma3 clocks */
527 enable_edma3_clocks();
531 __edma3_transfer(priv
->base
, 1, dst
, src
, len
, len
);
534 pr_err("Transfer type not implemented in DMA driver\n");
538 /* disable edma3 clocks */
539 disable_edma3_clocks();
544 static int ti_edma3_ofdata_to_platdata(struct udevice
*dev
)
546 struct ti_edma3_priv
*priv
= dev_get_priv(dev
);
548 priv
->base
= devfdt_get_addr(dev
);
553 static int ti_edma3_probe(struct udevice
*dev
)
555 struct dma_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
557 uc_priv
->supported
= DMA_SUPPORTS_MEM_TO_MEM
;
562 static const struct dma_ops ti_edma3_ops
= {
563 .transfer
= ti_edma3_transfer
,
566 static const struct udevice_id ti_edma3_ids
[] = {
567 { .compatible
= "ti,edma3" },
571 U_BOOT_DRIVER(ti_edma3
) = {
574 .of_match
= ti_edma3_ids
,
575 .ops
= &ti_edma3_ops
,
576 .ofdata_to_platdata
= ti_edma3_ofdata_to_platdata
,
577 .probe
= ti_edma3_probe
,
578 .priv_auto_alloc_size
= sizeof(struct ti_edma3_priv
),
580 #endif /* CONFIG_DMA */