drivers/dma/xilinx/zynqmp_dma.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * DMA driver for Xilinx ZynqMP DMA Engine
   4  *
   5  * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/dmapool.h>
  10 #include <linux/dma/xilinx_dma.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_dma.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/slab.h>
  20 #include <linux/clk.h>
  21 #include <linux/io-64-nonatomic-lo-hi.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include "../dmaengine.h"
  25
  26 /* Register Offsets */
  27 #define ZYNQMP_DMA_ISR                  0x100
  28 #define ZYNQMP_DMA_IMR                  0x104
  29 #define ZYNQMP_DMA_IER                  0x108
  30 #define ZYNQMP_DMA_IDS                  0x10C
  31 #define ZYNQMP_DMA_CTRL0                0x110
  32 #define ZYNQMP_DMA_CTRL1                0x114
  33 #define ZYNQMP_DMA_DATA_ATTR            0x120
  34 #define ZYNQMP_DMA_DSCR_ATTR            0x124
  35 #define ZYNQMP_DMA_SRC_DSCR_WRD0        0x128
  36 #define ZYNQMP_DMA_SRC_DSCR_WRD1        0x12C
  37 #define ZYNQMP_DMA_SRC_DSCR_WRD2        0x130
  38 #define ZYNQMP_DMA_SRC_DSCR_WRD3        0x134
  39 #define ZYNQMP_DMA_DST_DSCR_WRD0        0x138
  40 #define ZYNQMP_DMA_DST_DSCR_WRD1        0x13C
  41 #define ZYNQMP_DMA_DST_DSCR_WRD2        0x140
  42 #define ZYNQMP_DMA_DST_DSCR_WRD3        0x144
  43 #define ZYNQMP_DMA_SRC_START_LSB        0x158
  44 #define ZYNQMP_DMA_SRC_START_MSB        0x15C
  45 #define ZYNQMP_DMA_DST_START_LSB        0x160
  46 #define ZYNQMP_DMA_DST_START_MSB        0x164
  47 #define ZYNQMP_DMA_TOTAL_BYTE           0x188
  48 #define ZYNQMP_DMA_RATE_CTRL            0x18C
  49 #define ZYNQMP_DMA_IRQ_SRC_ACCT         0x190
  50 #define ZYNQMP_DMA_IRQ_DST_ACCT         0x194
  51 #define ZYNQMP_DMA_CTRL2                0x200
  52
  53 /* Interrupt registers bit field definitions */
  54 #define ZYNQMP_DMA_DONE                 BIT(10)
  55 #define ZYNQMP_DMA_AXI_WR_DATA          BIT(9)
  56 #define ZYNQMP_DMA_AXI_RD_DATA          BIT(8)
  57 #define ZYNQMP_DMA_AXI_RD_DST_DSCR      BIT(7)
  58 #define ZYNQMP_DMA_AXI_RD_SRC_DSCR      BIT(6)
  59 #define ZYNQMP_DMA_IRQ_DST_ACCT_ERR     BIT(5)
  60 #define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR     BIT(4)
  61 #define ZYNQMP_DMA_BYTE_CNT_OVRFL       BIT(3)
  62 #define ZYNQMP_DMA_DST_DSCR_DONE        BIT(2)
  63 #define ZYNQMP_DMA_INV_APB              BIT(0)
  64
  65 /* Control 0 register bit field definitions */
  66 #define ZYNQMP_DMA_OVR_FETCH            BIT(7)
  67 #define ZYNQMP_DMA_POINT_TYPE_SG        BIT(6)
  68 #define ZYNQMP_DMA_RATE_CTRL_EN         BIT(3)
  69
  70 /* Control 1 register bit field definitions */
  71 #define ZYNQMP_DMA_SRC_ISSUE            GENMASK(4, 0)
  72
  73 /* Data Attribute register bit field definitions */
  74 #define ZYNQMP_DMA_ARBURST              GENMASK(27, 26)
  75 #define ZYNQMP_DMA_ARCACHE              GENMASK(25, 22)
  76 #define ZYNQMP_DMA_ARCACHE_OFST         22
  77 #define ZYNQMP_DMA_ARQOS                GENMASK(21, 18)
  78 #define ZYNQMP_DMA_ARQOS_OFST           18
  79 #define ZYNQMP_DMA_ARLEN                GENMASK(17, 14)
  80 #define ZYNQMP_DMA_ARLEN_OFST           14
  81 #define ZYNQMP_DMA_AWBURST              GENMASK(13, 12)
  82 #define ZYNQMP_DMA_AWCACHE              GENMASK(11, 8)
  83 #define ZYNQMP_DMA_AWCACHE_OFST         8
  84 #define ZYNQMP_DMA_AWQOS                GENMASK(7, 4)
  85 #define ZYNQMP_DMA_AWQOS_OFST           4
  86 #define ZYNQMP_DMA_AWLEN                GENMASK(3, 0)
  87 #define ZYNQMP_DMA_AWLEN_OFST           0
  88
  89 /* Descriptor Attribute register bit field definitions */
  90 #define ZYNQMP_DMA_AXCOHRNT             BIT(8)
  91 #define ZYNQMP_DMA_AXCACHE              GENMASK(7, 4)
  92 #define ZYNQMP_DMA_AXCACHE_OFST         4
  93 #define ZYNQMP_DMA_AXQOS                GENMASK(3, 0)
  94 #define ZYNQMP_DMA_AXQOS_OFST           0
  95
  96 /* Control register 2 bit field definitions */
  97 #define ZYNQMP_DMA_ENABLE               BIT(0)
  98
  99 /* Buffer Descriptor definitions */
 100 #define ZYNQMP_DMA_DESC_CTRL_STOP       0x10
 101 #define ZYNQMP_DMA_DESC_CTRL_COMP_INT   0x4
 102 #define ZYNQMP_DMA_DESC_CTRL_SIZE_256   0x2
 103 #define ZYNQMP_DMA_DESC_CTRL_COHRNT     0x1
 104
 105 /* Interrupt Mask specific definitions */
 106 #define ZYNQMP_DMA_INT_ERR      (ZYNQMP_DMA_AXI_RD_DATA | \
 107                                 ZYNQMP_DMA_AXI_WR_DATA | \
 108                                 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
 109                                 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
 110                                 ZYNQMP_DMA_INV_APB)
 111 #define ZYNQMP_DMA_INT_OVRFL    (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
 112                                 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
 113                                 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 114 #define ZYNQMP_DMA_INT_DONE     (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
 115 #define ZYNQMP_DMA_INT_EN_DEFAULT_MASK  (ZYNQMP_DMA_INT_DONE | \
 116                                         ZYNQMP_DMA_INT_ERR | \
 117                                         ZYNQMP_DMA_INT_OVRFL | \
 118                                         ZYNQMP_DMA_DST_DSCR_DONE)
 119
 120 /* Max number of descriptors per channel */
 121 #define ZYNQMP_DMA_NUM_DESCS    32
 122
 123 /* Max transfer size per descriptor */
 124 #define ZYNQMP_DMA_MAX_TRANS_LEN        0x40000000
 125
 126 /* Max burst lengths */
 127 #define ZYNQMP_DMA_MAX_DST_BURST_LEN    32768U
 128 #define ZYNQMP_DMA_MAX_SRC_BURST_LEN    32768U
 129
 130 /* Reset values for data attributes */
 131 #define ZYNQMP_DMA_AXCACHE_VAL          0xF
 132
 133 #define ZYNQMP_DMA_SRC_ISSUE_RST_VAL    0x1F
 134
 135 #define ZYNQMP_DMA_IDS_DEFAULT_MASK     0xFFF
 136
 137 /* Bus width in bits */
 138 #define ZYNQMP_DMA_BUS_WIDTH_64         64
 139 #define ZYNQMP_DMA_BUS_WIDTH_128        128
 140
 141 #define ZDMA_PM_TIMEOUT                 100
 142
 143 #define ZYNQMP_DMA_DESC_SIZE(chan)      (chan->desc_size)
 144
 145 #define to_chan(chan)           container_of(chan, struct zynqmp_dma_chan, \
 146                                              common)
 147 #define tx_to_desc(tx)          container_of(tx, struct zynqmp_dma_desc_sw, \
 148                                              async_tx)
 149
 150 /**
 151  * struct zynqmp_dma_desc_ll - Hw linked list descriptor
 152  * @addr: Buffer address
 153  * @size: Size of the buffer
 154  * @ctrl: Control word
 155  * @nxtdscraddr: Next descriptor base address
 156  * @rsvd: Reserved field and for Hw internal use.
 157  */
 158 struct zynqmp_dma_desc_ll {
 159         u64 addr;
 160         u32 size;
 161         u32 ctrl;
 162         u64 nxtdscraddr;
 163         u64 rsvd;
 164 };
 165
 166 /**
 167  * struct zynqmp_dma_desc_sw - Per Transaction structure
 168  * @src: Source address for simple mode dma
 169  * @dst: Destination address for simple mode dma
 170  * @len: Transfer length for simple mode dma
 171  * @node: Node in the channel descriptor list
 172  * @tx_list: List head for the current transfer
 173  * @async_tx: Async transaction descriptor
 174  * @src_v: Virtual address of the src descriptor
 175  * @src_p: Physical address of the src descriptor
 176  * @dst_v: Virtual address of the dst descriptor
 177  * @dst_p: Physical address of the dst descriptor
 178  */
 179 struct zynqmp_dma_desc_sw {
 180         u64 src;
 181         u64 dst;
 182         u32 len;
 183         struct list_head node;
 184         struct list_head tx_list;
 185         struct dma_async_tx_descriptor async_tx;
 186         struct zynqmp_dma_desc_ll *src_v;
 187         dma_addr_t src_p;
 188         struct zynqmp_dma_desc_ll *dst_v;
 189         dma_addr_t dst_p;
 190 };
 191
 192 /**
 193  * struct zynqmp_dma_chan - Driver specific DMA channel structure
 194  * @zdev: Driver specific device structure
 195  * @regs: Control registers offset
 196  * @lock: Descriptor operation lock
 197  * @pending_list: Descriptors waiting
 198  * @free_list: Descriptors free
 199  * @active_list: Descriptors active
 200  * @sw_desc_pool: SW descriptor pool
 201  * @done_list: Complete descriptors
 202  * @common: DMA common channel
 203  * @desc_pool_v: Statically allocated descriptor base
 204  * @desc_pool_p: Physical allocated descriptor base
 205  * @desc_free_cnt: Descriptor available count
 206  * @dev: The dma device
 207  * @irq: Channel IRQ
 208  * @is_dmacoherent: Tells whether dma operations are coherent or not
 209  * @tasklet: Cleanup work after irq
 210  * @idle : Channel status;
 211  * @desc_size: Size of the low level descriptor
 212  * @err: Channel has errors
 213  * @bus_width: Bus width
 214  * @src_burst_len: Source burst length
 215  * @dst_burst_len: Dest burst length
 216  */
 217 struct zynqmp_dma_chan {
 218         struct zynqmp_dma_device *zdev;
 219         void __iomem *regs;
 220         spinlock_t lock;
 221         struct list_head pending_list;
 222         struct list_head free_list;
 223         struct list_head active_list;
 224         struct zynqmp_dma_desc_sw *sw_desc_pool;
 225         struct list_head done_list;
 226         struct dma_chan common;
 227         void *desc_pool_v;
 228         dma_addr_t desc_pool_p;
 229         u32 desc_free_cnt;
 230         struct device *dev;
 231         int irq;
 232         bool is_dmacoherent;
 233         struct tasklet_struct tasklet;
 234         bool idle;
 235         u32 desc_size;
 236         bool err;
 237         u32 bus_width;
 238         u32 src_burst_len;
 239         u32 dst_burst_len;
 240 };
 241
 242 /**
 243  * struct zynqmp_dma_device - DMA device structure
 244  * @dev: Device Structure
 245  * @common: DMA device structure
 246  * @chan: Driver specific DMA channel
 247  * @clk_main: Pointer to main clock
 248  * @clk_apb: Pointer to apb clock
 249  */
 250 struct zynqmp_dma_device {
 251         struct device *dev;
 252         struct dma_device common;
 253         struct zynqmp_dma_chan *chan;
 254         struct clk *clk_main;
 255         struct clk *clk_apb;
 256 };
 257
 258 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
 259                                      u64 value)
 260 {
 261         lo_hi_writeq(value, chan->regs + reg);
 262 }
 263
 264 /**
 265  * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
 266  * @chan: ZynqMP DMA DMA channel pointer
 267  * @desc: Transaction descriptor pointer
 268  */
 269 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
 270                                       struct zynqmp_dma_desc_sw *desc)
 271 {
 272         dma_addr_t addr;
 273
 274         addr = desc->src_p;
 275         zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
 276         addr = desc->dst_p;
 277         zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
 278 }
 279
 280 /**
 281  * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
 282  * @chan: ZynqMP DMA channel pointer
 283  * @desc: Hw descriptor pointer
 284  */
 285 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
 286                                        void *desc)
 287 {
 288         struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
 289
 290         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
 291         hw++;
 292         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
 293 }
 294
 295 /**
 296  * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
 297  * @chan: ZynqMP DMA channel pointer
 298  * @sdesc: Hw descriptor pointer
 299  * @src: Source buffer address
 300  * @dst: Destination buffer address
 301  * @len: Transfer length
 302  * @prev: Previous hw descriptor pointer
 303  */
 304 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
 305                                    struct zynqmp_dma_desc_ll *sdesc,
 306                                    dma_addr_t src, dma_addr_t dst, size_t len,
 307                                    struct zynqmp_dma_desc_ll *prev)
 308 {
 309         struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
 310
 311         sdesc->size = ddesc->size = len;
 312         sdesc->addr = src;
 313         ddesc->addr = dst;
 314
 315         sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
 316         if (chan->is_dmacoherent) {
 317                 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 318                 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 319         }
 320
 321         if (prev) {
 322                 dma_addr_t addr = chan->desc_pool_p +
 323                             ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
 324                 ddesc = prev + 1;
 325                 prev->nxtdscraddr = addr;
 326                 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
 327         }
 328 }
 329
 330 /**
 331  * zynqmp_dma_init - Initialize the channel
 332  * @chan: ZynqMP DMA channel pointer
 333  */
 334 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
 335 {
 336         u32 val;
 337
 338         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 339         val = readl(chan->regs + ZYNQMP_DMA_ISR);
 340         writel(val, chan->regs + ZYNQMP_DMA_ISR);
 341
 342         if (chan->is_dmacoherent) {
 343                 val = ZYNQMP_DMA_AXCOHRNT;
 344                 val = (val & ~ZYNQMP_DMA_AXCACHE) |
 345                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
 346                 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
 347         }
 348
 349         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 350         if (chan->is_dmacoherent) {
 351                 val = (val & ~ZYNQMP_DMA_ARCACHE) |
 352                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
 353                 val = (val & ~ZYNQMP_DMA_AWCACHE) |
 354                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
 355         }
 356         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 357
 358         /* Clearing the interrupt account rgisters */
 359         val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 360         val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 361
 362         chan->idle = true;
 363 }
 364
 365 /**
 366  * zynqmp_dma_tx_submit - Submit DMA transaction
 367  * @tx: Async transaction descriptor pointer
 368  *
 369  * Return: cookie value
 370  */
 371 static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 372 {
 373         struct zynqmp_dma_chan *chan = to_chan(tx->chan);
 374         struct zynqmp_dma_desc_sw *desc, *new;
 375         dma_cookie_t cookie;
 376         unsigned long irqflags;
 377
 378         new = tx_to_desc(tx);
 379         spin_lock_irqsave(&chan->lock, irqflags);
 380         cookie = dma_cookie_assign(tx);
 381
 382         if (!list_empty(&chan->pending_list)) {
 383                 desc = list_last_entry(&chan->pending_list,
 384                                      struct zynqmp_dma_desc_sw, node);
 385                 if (!list_empty(&desc->tx_list))
 386                         desc = list_last_entry(&desc->tx_list,
 387                                                struct zynqmp_dma_desc_sw, node);
 388                 desc->src_v->nxtdscraddr = new->src_p;
 389                 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 390                 desc->dst_v->nxtdscraddr = new->dst_p;
 391                 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 392         }
 393
 394         list_add_tail(&new->node, &chan->pending_list);
 395         spin_unlock_irqrestore(&chan->lock, irqflags);
 396
 397         return cookie;
 398 }
 399
 400 /**
 401  * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
 402  * @chan: ZynqMP DMA channel pointer
 403  *
 404  * Return: The sw descriptor
 405  */
 406 static struct zynqmp_dma_desc_sw *
 407 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
 408 {
 409         struct zynqmp_dma_desc_sw *desc;
 410         unsigned long irqflags;
 411
 412         spin_lock_irqsave(&chan->lock, irqflags);
 413         desc = list_first_entry(&chan->free_list,
 414                                 struct zynqmp_dma_desc_sw, node);
 415         list_del(&desc->node);
 416         spin_unlock_irqrestore(&chan->lock, irqflags);
 417
 418         INIT_LIST_HEAD(&desc->tx_list);
 419         /* Clear the src and dst descriptor memory */
 420         memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 421         memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 422
 423         return desc;
 424 }
 425
 426 /**
 427  * zynqmp_dma_free_descriptor - Issue pending transactions
 428  * @chan: ZynqMP DMA channel pointer
 429  * @sdesc: Transaction descriptor pointer
 430  */
 431 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
 432                                  struct zynqmp_dma_desc_sw *sdesc)
 433 {
 434         struct zynqmp_dma_desc_sw *child, *next;
 435
 436         chan->desc_free_cnt++;
 437         list_add_tail(&sdesc->node, &chan->free_list);
 438         list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
 439                 chan->desc_free_cnt++;
 440                 list_move_tail(&child->node, &chan->free_list);
 441         }
 442 }
 443
 444 /**
 445  * zynqmp_dma_free_desc_list - Free descriptors list
 446  * @chan: ZynqMP DMA channel pointer
 447  * @list: List to parse and delete the descriptor
 448  */
 449 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
 450                                       struct list_head *list)
 451 {
 452         struct zynqmp_dma_desc_sw *desc, *next;
 453
 454         list_for_each_entry_safe(desc, next, list, node)
 455                 zynqmp_dma_free_descriptor(chan, desc);
 456 }
 457
 458 /**
 459  * zynqmp_dma_alloc_chan_resources - Allocate channel resources
 460  * @dchan: DMA channel
 461  *
 462  * Return: Number of descriptors on success and failure value on error
 463  */
 464 static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
 465 {
 466         struct zynqmp_dma_chan *chan = to_chan(dchan);
 467         struct zynqmp_dma_desc_sw *desc;
 468         int i, ret;
 469
 470         ret = pm_runtime_get_sync(chan->dev);
 471         if (ret < 0)
 472                 return ret;
 473
 474         chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
 475                                      GFP_KERNEL);
 476         if (!chan->sw_desc_pool)
 477                 return -ENOMEM;
 478
 479         chan->idle = true;
 480         chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
 481
 482         INIT_LIST_HEAD(&chan->free_list);
 483
 484         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 485                 desc = chan->sw_desc_pool + i;
 486                 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
 487                 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
 488                 list_add_tail(&desc->node, &chan->free_list);
 489         }
 490
 491         chan->desc_pool_v = dma_alloc_coherent(chan->dev,
 492                                                (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS),
 493                                                &chan->desc_pool_p, GFP_KERNEL);
 494         if (!chan->desc_pool_v)
 495                 return -ENOMEM;
 496
 497         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 498                 desc = chan->sw_desc_pool + i;
 499                 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
 500                                         (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
 501                 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
 502                 desc->src_p = chan->desc_pool_p +
 503                                 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
 504                 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
 505         }
 506
 507         return ZYNQMP_DMA_NUM_DESCS;
 508 }
 509
 510 /**
 511  * zynqmp_dma_start - Start DMA channel
 512  * @chan: ZynqMP DMA channel pointer
 513  */
 514 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
 515 {
 516         writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
 517         writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 518         chan->idle = false;
 519         writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
 520 }
 521
 522 /**
 523  * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
 524  * @chan: ZynqMP DMA channel pointer
 525  * @status: Interrupt status value
 526  */
 527 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
 528 {
 529         if (status & ZYNQMP_DMA_BYTE_CNT_OVRFL)
 530                 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
 531         if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 532                 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 533         if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
 534                 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 535 }
 536
 537 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
 538 {
 539         u32 val, burst_val;
 540
 541         val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
 542         val |= ZYNQMP_DMA_POINT_TYPE_SG;
 543         writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
 544
 545         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 546         burst_val = __ilog2_u32(chan->src_burst_len);
 547         val = (val & ~ZYNQMP_DMA_ARLEN) |
 548                 ((burst_val << ZYNQMP_DMA_ARLEN_OFST) & ZYNQMP_DMA_ARLEN);
 549         burst_val = __ilog2_u32(chan->dst_burst_len);
 550         val = (val & ~ZYNQMP_DMA_AWLEN) |
 551                 ((burst_val << ZYNQMP_DMA_AWLEN_OFST) & ZYNQMP_DMA_AWLEN);
 552         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 553 }
 554
 555 /**
 556  * zynqmp_dma_device_config - Zynqmp dma device configuration
 557  * @dchan: DMA channel
 558  * @config: DMA device config
 559  *
 560  * Return: 0 always
 561  */
 562 static int zynqmp_dma_device_config(struct dma_chan *dchan,
 563                                     struct dma_slave_config *config)
 564 {
 565         struct zynqmp_dma_chan *chan = to_chan(dchan);
 566
 567         chan->src_burst_len = clamp(config->src_maxburst, 1U,
 568                 ZYNQMP_DMA_MAX_SRC_BURST_LEN);
 569         chan->dst_burst_len = clamp(config->dst_maxburst, 1U,
 570                 ZYNQMP_DMA_MAX_DST_BURST_LEN);
 571
 572         return 0;
 573 }
 574
 575 /**
 576  * zynqmp_dma_start_transfer - Initiate the new transfer
 577  * @chan: ZynqMP DMA channel pointer
 578  */
 579 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
 580 {
 581         struct zynqmp_dma_desc_sw *desc;
 582
 583         if (!chan->idle)
 584                 return;
 585
 586         zynqmp_dma_config(chan);
 587
 588         desc = list_first_entry_or_null(&chan->pending_list,
 589                                         struct zynqmp_dma_desc_sw, node);
 590         if (!desc)
 591                 return;
 592
 593         list_splice_tail_init(&chan->pending_list, &chan->active_list);
 594         zynqmp_dma_update_desc_to_ctrlr(chan, desc);
 595         zynqmp_dma_start(chan);
 596 }
 597
 598
 599 /**
 600  * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
 601  * @chan: ZynqMP DMA channel
 602  */
 603 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
 604 {
 605         struct zynqmp_dma_desc_sw *desc, *next;
 606
 607         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
 608                 dma_async_tx_callback callback;
 609                 void *callback_param;
 610
 611                 list_del(&desc->node);
 612
 613                 callback = desc->async_tx.callback;
 614                 callback_param = desc->async_tx.callback_param;
 615                 if (callback) {
 616                         spin_unlock(&chan->lock);
 617                         callback(callback_param);
 618                         spin_lock(&chan->lock);
 619                 }
 620
 621                 /* Run any dependencies, then free the descriptor */
 622                 zynqmp_dma_free_descriptor(chan, desc);
 623         }
 624 }
 625
 626 /**
 627  * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
 628  * @chan: ZynqMP DMA channel pointer
 629  */
 630 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
 631 {
 632         struct zynqmp_dma_desc_sw *desc;
 633
 634         desc = list_first_entry_or_null(&chan->active_list,
 635                                         struct zynqmp_dma_desc_sw, node);
 636         if (!desc)
 637                 return;
 638         list_del(&desc->node);
 639         dma_cookie_complete(&desc->async_tx);
 640         list_add_tail(&desc->node, &chan->done_list);
 641 }
 642
 643 /**
 644  * zynqmp_dma_issue_pending - Issue pending transactions
 645  * @dchan: DMA channel pointer
 646  */
 647 static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
 648 {
 649         struct zynqmp_dma_chan *chan = to_chan(dchan);
 650         unsigned long irqflags;
 651
 652         spin_lock_irqsave(&chan->lock, irqflags);
 653         zynqmp_dma_start_transfer(chan);
 654         spin_unlock_irqrestore(&chan->lock, irqflags);
 655 }
 656
 657 /**
 658  * zynqmp_dma_free_descriptors - Free channel descriptors
 659  * @chan: ZynqMP DMA channel pointer
 660  */
 661 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
 662 {
 663         zynqmp_dma_free_desc_list(chan, &chan->active_list);
 664         zynqmp_dma_free_desc_list(chan, &chan->pending_list);
 665         zynqmp_dma_free_desc_list(chan, &chan->done_list);
 666 }
 667
 668 /**
 669  * zynqmp_dma_free_chan_resources - Free channel resources
 670  * @dchan: DMA channel pointer
 671  */
 672 static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
 673 {
 674         struct zynqmp_dma_chan *chan = to_chan(dchan);
 675         unsigned long irqflags;
 676
 677         spin_lock_irqsave(&chan->lock, irqflags);
 678         zynqmp_dma_free_descriptors(chan);
 679         spin_unlock_irqrestore(&chan->lock, irqflags);
 680         dma_free_coherent(chan->dev,
 681                 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
 682                 chan->desc_pool_v, chan->desc_pool_p);
 683         kfree(chan->sw_desc_pool);
 684         pm_runtime_mark_last_busy(chan->dev);
 685         pm_runtime_put_autosuspend(chan->dev);
 686 }
 687
 688 /**
 689  * zynqmp_dma_reset - Reset the channel
 690  * @chan: ZynqMP DMA channel pointer
 691  */
 692 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
 693 {
 694         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 695
 696         zynqmp_dma_complete_descriptor(chan);
 697         zynqmp_dma_chan_desc_cleanup(chan);
 698         zynqmp_dma_free_descriptors(chan);
 699         zynqmp_dma_init(chan);
 700 }
 701
 702 /**
 703  * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
 704  * @irq: IRQ number
 705  * @data: Pointer to the ZynqMP DMA channel structure
 706  *
 707  * Return: IRQ_HANDLED/IRQ_NONE
 708  */
 709 static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
 710 {
 711         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 712         u32 isr, imr, status;
 713         irqreturn_t ret = IRQ_NONE;
 714
 715         isr = readl(chan->regs + ZYNQMP_DMA_ISR);
 716         imr = readl(chan->regs + ZYNQMP_DMA_IMR);
 717         status = isr & ~imr;
 718
 719         writel(isr, chan->regs + ZYNQMP_DMA_ISR);
 720         if (status & ZYNQMP_DMA_INT_DONE) {
 721                 tasklet_schedule(&chan->tasklet);
 722                 ret = IRQ_HANDLED;
 723         }
 724
 725         if (status & ZYNQMP_DMA_DONE)
 726                 chan->idle = true;
 727
 728         if (status & ZYNQMP_DMA_INT_ERR) {
 729                 chan->err = true;
 730                 tasklet_schedule(&chan->tasklet);
 731                 dev_err(chan->dev, "Channel %p has errors\n", chan);
 732                 ret = IRQ_HANDLED;
 733         }
 734
 735         if (status & ZYNQMP_DMA_INT_OVRFL) {
 736                 zynqmp_dma_handle_ovfl_int(chan, status);
 737                 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
 738                 ret = IRQ_HANDLED;
 739         }
 740
 741         return ret;
 742 }
 743
 744 /**
 745  * zynqmp_dma_do_tasklet - Schedule completion tasklet
 746  * @data: Pointer to the ZynqMP DMA channel structure
 747  */
 748 static void zynqmp_dma_do_tasklet(unsigned long data)
 749 {
 750         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 751         u32 count;
 752         unsigned long irqflags;
 753
 754         spin_lock_irqsave(&chan->lock, irqflags);
 755
 756         if (chan->err) {
 757                 zynqmp_dma_reset(chan);
 758                 chan->err = false;
 759                 goto unlock;
 760         }
 761
 762         count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 763
 764         while (count) {
 765                 zynqmp_dma_complete_descriptor(chan);
 766                 zynqmp_dma_chan_desc_cleanup(chan);
 767                 count--;
 768         }
 769
 770         if (chan->idle)
 771                 zynqmp_dma_start_transfer(chan);
 772
 773 unlock:
 774         spin_unlock_irqrestore(&chan->lock, irqflags);
 775 }
 776
 777 /**
 778  * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
 779  * @dchan: DMA channel pointer
 780  *
 781  * Return: Always '0'
 782  */
 783 static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
 784 {
 785         struct zynqmp_dma_chan *chan = to_chan(dchan);
 786         unsigned long irqflags;
 787
 788         spin_lock_irqsave(&chan->lock, irqflags);
 789         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 790         zynqmp_dma_free_descriptors(chan);
 791         spin_unlock_irqrestore(&chan->lock, irqflags);
 792
 793         return 0;
 794 }
 795
 796 /**
 797  * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
 798  * @dchan: DMA channel
 799  * @dma_dst: Destination buffer address
 800  * @dma_src: Source buffer address
 801  * @len: Transfer length
 802  * @flags: transfer ack flags
 803  *
 804  * Return: Async transaction descriptor on success and NULL on failure
 805  */
 806 static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
 807                                 struct dma_chan *dchan, dma_addr_t dma_dst,
 808                                 dma_addr_t dma_src, size_t len, ulong flags)
 809 {
 810         struct zynqmp_dma_chan *chan;
 811         struct zynqmp_dma_desc_sw *new, *first = NULL;
 812         void *desc = NULL, *prev = NULL;
 813         size_t copy;
 814         u32 desc_cnt;
 815         unsigned long irqflags;
 816
 817         chan = to_chan(dchan);
 818
 819         desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
 820
 821         spin_lock_irqsave(&chan->lock, irqflags);
 822         if (desc_cnt > chan->desc_free_cnt) {
 823                 spin_unlock_irqrestore(&chan->lock, irqflags);
 824                 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
 825                 return NULL;
 826         }
 827         chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
 828         spin_unlock_irqrestore(&chan->lock, irqflags);
 829
 830         do {
 831                 /* Allocate and populate the descriptor */
 832                 new = zynqmp_dma_get_descriptor(chan);
 833
 834                 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
 835                 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
 836                 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
 837                                              dma_dst, copy, prev);
 838                 prev = desc;
 839                 len -= copy;
 840                 dma_src += copy;
 841                 dma_dst += copy;
 842                 if (!first)
 843                         first = new;
 844                 else
 845                         list_add_tail(&new->node, &first->tx_list);
 846         } while (len);
 847
 848         zynqmp_dma_desc_config_eod(chan, desc);
 849         async_tx_ack(&first->async_tx);
 850         first->async_tx.flags = flags;
 851         return &first->async_tx;
 852 }
 853
 854 /**
 855  * zynqmp_dma_chan_remove - Channel remove function
 856  * @chan: ZynqMP DMA channel pointer
 857  */
 858 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
 859 {
 860         if (!chan)
 861                 return;
 862
 863         if (chan->irq)
 864                 devm_free_irq(chan->zdev->dev, chan->irq, chan);
 865         tasklet_kill(&chan->tasklet);
 866         list_del(&chan->common.device_node);
 867 }
 868
 869 /**
 870  * zynqmp_dma_chan_probe - Per Channel Probing
 871  * @zdev: Driver specific device structure
 872  * @pdev: Pointer to the platform_device structure
 873  *
 874  * Return: '0' on success and failure value on error
 875  */
 876 static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
 877                            struct platform_device *pdev)
 878 {
 879         struct zynqmp_dma_chan *chan;
 880         struct resource *res;
 881         struct device_node *node = pdev->dev.of_node;
 882         int err;
 883
 884         chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
 885         if (!chan)
 886                 return -ENOMEM;
 887         chan->dev = zdev->dev;
 888         chan->zdev = zdev;
 889
 890         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 891         chan->regs = devm_ioremap_resource(&pdev->dev, res);
 892         if (IS_ERR(chan->regs))
 893                 return PTR_ERR(chan->regs);
 894
 895         chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
 896         chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN;
 897         chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN;
 898         err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
 899         if (err < 0) {
 900                 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
 901                 return err;
 902         }
 903
 904         if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
 905             chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
 906                 dev_err(zdev->dev, "invalid bus-width value");
 907                 return -EINVAL;
 908         }
 909
 910         chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
 911         zdev->chan = chan;
 912         tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
 913         spin_lock_init(&chan->lock);
 914         INIT_LIST_HEAD(&chan->active_list);
 915         INIT_LIST_HEAD(&chan->pending_list);
 916         INIT_LIST_HEAD(&chan->done_list);
 917         INIT_LIST_HEAD(&chan->free_list);
 918
 919         dma_cookie_init(&chan->common);
 920         chan->common.device = &zdev->common;
 921         list_add_tail(&chan->common.device_node, &zdev->common.channels);
 922
 923         zynqmp_dma_init(chan);
 924         chan->irq = platform_get_irq(pdev, 0);
 925         if (chan->irq < 0)
 926                 return -ENXIO;
 927         err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
 928                                "zynqmp-dma", chan);
 929         if (err)
 930                 return err;
 931
 932         chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
 933         chan->idle = true;
 934         return 0;
 935 }
 936
 937 /**
 938  * of_zynqmp_dma_xlate - Translation function
 939  * @dma_spec: Pointer to DMA specifier as found in the device tree
 940  * @ofdma: Pointer to DMA controller data
 941  *
 942  * Return: DMA channel pointer on success and NULL on error
 943  */
 944 static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
 945                                             struct of_dma *ofdma)
 946 {
 947         struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
 948
 949         return dma_get_slave_channel(&zdev->chan->common);
 950 }
 951
 952 /**
 953  * zynqmp_dma_suspend - Suspend method for the driver
 954  * @dev:        Address of the device structure
 955  *
 956  * Put the driver into low power mode.
 957  * Return: 0 on success and failure value on error
 958  */
 959 static int __maybe_unused zynqmp_dma_suspend(struct device *dev)
 960 {
 961         if (!device_may_wakeup(dev))
 962                 return pm_runtime_force_suspend(dev);
 963
 964         return 0;
 965 }
 966
 967 /**
 968  * zynqmp_dma_resume - Resume from suspend
 969  * @dev:        Address of the device structure
 970  *
 971  * Resume operation after suspend.
 972  * Return: 0 on success and failure value on error
 973  */
 974 static int __maybe_unused zynqmp_dma_resume(struct device *dev)
 975 {
 976         if (!device_may_wakeup(dev))
 977                 return pm_runtime_force_resume(dev);
 978
 979         return 0;
 980 }
 981
 982 /**
 983  * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
 984  * @dev:        Address of the device structure
 985  *
 986  * Put the driver into low power mode.
 987  * Return: 0 always
 988  */
 989 static int __maybe_unused zynqmp_dma_runtime_suspend(struct device *dev)
 990 {
 991         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
 992
 993         clk_disable_unprepare(zdev->clk_main);
 994         clk_disable_unprepare(zdev->clk_apb);
 995
 996         return 0;
 997 }
 998
 999 /**
1000  * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
1001  * @dev:        Address of the device structure
1002  *
1003  * Put the driver into low power mode.
1004  * Return: 0 always
1005  */
1006 static int __maybe_unused zynqmp_dma_runtime_resume(struct device *dev)
1007 {
1008         struct zynqmp_dma_device *zdev = dev_get_drvdata(dev);
1009         int err;
1010
1011         err = clk_prepare_enable(zdev->clk_main);
1012         if (err) {
1013                 dev_err(dev, "Unable to enable main clock.\n");
1014                 return err;
1015         }
1016
1017         err = clk_prepare_enable(zdev->clk_apb);
1018         if (err) {
1019                 dev_err(dev, "Unable to enable apb clock.\n");
1020                 clk_disable_unprepare(zdev->clk_main);
1021                 return err;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static const struct dev_pm_ops zynqmp_dma_dev_pm_ops = {
1028         SET_SYSTEM_SLEEP_PM_OPS(zynqmp_dma_suspend, zynqmp_dma_resume)
1029         SET_RUNTIME_PM_OPS(zynqmp_dma_runtime_suspend,
1030                            zynqmp_dma_runtime_resume, NULL)
1031 };
1032
1033 /**
1034  * zynqmp_dma_probe - Driver probe function
1035  * @pdev: Pointer to the platform_device structure
1036  *
1037  * Return: '0' on success and failure value on error
1038  */
1039 static int zynqmp_dma_probe(struct platform_device *pdev)
1040 {
1041         struct zynqmp_dma_device *zdev;
1042         struct dma_device *p;
1043         int ret;
1044
1045         zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1046         if (!zdev)
1047                 return -ENOMEM;
1048
1049         zdev->dev = &pdev->dev;
1050         INIT_LIST_HEAD(&zdev->common.channels);
1051
1052         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1053         dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1054
1055         p = &zdev->common;
1056         p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1057         p->device_terminate_all = zynqmp_dma_device_terminate_all;
1058         p->device_issue_pending = zynqmp_dma_issue_pending;
1059         p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1060         p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1061         p->device_tx_status = dma_cookie_status;
1062         p->device_config = zynqmp_dma_device_config;
1063         p->dev = &pdev->dev;
1064
1065         zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1066         if (IS_ERR(zdev->clk_main)) {
1067                 dev_err(&pdev->dev, "main clock not found.\n");
1068                 return PTR_ERR(zdev->clk_main);
1069         }
1070
1071         zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1072         if (IS_ERR(zdev->clk_apb)) {
1073                 dev_err(&pdev->dev, "apb clock not found.\n");
1074                 return PTR_ERR(zdev->clk_apb);
1075         }
1076
1077         platform_set_drvdata(pdev, zdev);
1078         pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT);
1079         pm_runtime_use_autosuspend(zdev->dev);
1080         pm_runtime_enable(zdev->dev);
1081         pm_runtime_get_sync(zdev->dev);
1082         if (!pm_runtime_enabled(zdev->dev)) {
1083                 ret = zynqmp_dma_runtime_resume(zdev->dev);
1084                 if (ret)
1085                         return ret;
1086         }
1087
1088         ret = zynqmp_dma_chan_probe(zdev, pdev);
1089         if (ret) {
1090                 dev_err(&pdev->dev, "Probing channel failed\n");
1091                 goto err_disable_pm;
1092         }
1093
1094         p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1095         p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1096
1097         dma_async_device_register(&zdev->common);
1098
1099         ret = of_dma_controller_register(pdev->dev.of_node,
1100                                          of_zynqmp_dma_xlate, zdev);
1101         if (ret) {
1102                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
1103                 dma_async_device_unregister(&zdev->common);
1104                 goto free_chan_resources;
1105         }
1106
1107         pm_runtime_mark_last_busy(zdev->dev);
1108         pm_runtime_put_sync_autosuspend(zdev->dev);
1109
1110         dev_info(&pdev->dev, "ZynqMP DMA driver Probe success\n");
1111
1112         return 0;
1113
1114 free_chan_resources:
1115         zynqmp_dma_chan_remove(zdev->chan);
1116 err_disable_pm:
1117         if (!pm_runtime_enabled(zdev->dev))
1118                 zynqmp_dma_runtime_suspend(zdev->dev);
1119         pm_runtime_disable(zdev->dev);
1120         return ret;
1121 }
1122
1123 /**
1124  * zynqmp_dma_remove - Driver remove function
1125  * @pdev: Pointer to the platform_device structure
1126  *
1127  * Return: Always '0'
1128  */
1129 static int zynqmp_dma_remove(struct platform_device *pdev)
1130 {
1131         struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1132
1133         of_dma_controller_free(pdev->dev.of_node);
1134         dma_async_device_unregister(&zdev->common);
1135
1136         zynqmp_dma_chan_remove(zdev->chan);
1137         pm_runtime_disable(zdev->dev);
1138         if (!pm_runtime_enabled(zdev->dev))
1139                 zynqmp_dma_runtime_suspend(zdev->dev);
1140
1141         return 0;
1142 }
1143
1144 static const struct of_device_id zynqmp_dma_of_match[] = {
1145         { .compatible = "xlnx,zynqmp-dma-1.0", },
1146         {}
1147 };
1148 MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1149
1150 static struct platform_driver zynqmp_dma_driver = {
1151         .driver = {
1152                 .name = "xilinx-zynqmp-dma",
1153                 .of_match_table = zynqmp_dma_of_match,
1154                 .pm = &zynqmp_dma_dev_pm_ops,
1155         },
1156         .probe = zynqmp_dma_probe,
1157         .remove = zynqmp_dma_remove,
1158 };
1159
1160 module_platform_driver(zynqmp_dma_driver);
1161
1162 MODULE_LICENSE("GPL");
1163 MODULE_AUTHOR("Xilinx, Inc.");
1164 MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");