drivers/edac/Kconfig

   1 #
   2 #       EDAC Kconfig
   3 #       Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
   4 #       Licensed and distributed under the GPL
   5
   6 config EDAC_ATOMIC_SCRUB
   7         bool
   8
   9 config EDAC_SUPPORT
  10         bool
  11
  12 menuconfig EDAC
  13         tristate "EDAC (Error Detection And Correction) reporting"
  14         depends on HAS_IOMEM && EDAC_SUPPORT && RAS
  15         help
  16           EDAC is a subsystem along with hardware-specific drivers designed to
  17           report hardware errors. These are low-level errors that are reported
  18           in the CPU or supporting chipset or other subsystems:
  19           memory errors, cache errors, PCI errors, thermal throttling, etc..
  20           If unsure, select 'Y'.
  21
  22           The mailing list for the EDAC project is linux-edac@vger.kernel.org.
  23
  24 if EDAC
  25
  26 config EDAC_LEGACY_SYSFS
  27         bool "EDAC legacy sysfs"
  28         default y
  29         help
  30           Enable the compatibility sysfs nodes.
  31           Use 'Y' if your edac utilities aren't ported to work with the newer
  32           structures.
  33
  34 config EDAC_DEBUG
  35         bool "Debugging"
  36         select DEBUG_FS
  37         help
  38           This turns on debugging information for the entire EDAC subsystem.
  39           You do so by inserting edac_module with "edac_debug_level=x." Valid
  40           levels are 0-4 (from low to high) and by default it is set to 2.
  41           Usually you should select 'N' here.
  42
  43 config EDAC_DECODE_MCE
  44         tristate "Decode MCEs in human-readable form (only on AMD for now)"
  45         depends on CPU_SUP_AMD && X86_MCE_AMD
  46         default y
  47         ---help---
  48           Enable this option if you want to decode Machine Check Exceptions
  49           occurring on your machine in human-readable form.
  50
  51           You should definitely say Y here in case you want to decode MCEs
  52           which occur really early upon boot, before the module infrastructure
  53           has been initialized.
  54
  55 config EDAC_GHES
  56         bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
  57         depends on ACPI_APEI_GHES && (EDAC=y)
  58         help
  59           Not all machines support hardware-driven error report. Some of those
  60           provide a BIOS-driven error report mechanism via ACPI, using the
  61           APEI/GHES driver. By enabling this option, the error reports provided
  62           by GHES are sent to userspace via the EDAC API.
  63
  64           When this option is enabled, it will disable the hardware-driven
  65           mechanisms, if a GHES BIOS is detected, entering into the
  66           "Firmware First" mode.
  67
  68           It should be noticed that keeping both GHES and a hardware-driven
  69           error mechanism won't work well, as BIOS will race with OS, while
  70           reading the error registers. So, if you want to not use "Firmware
  71           first" GHES error mechanism, you should disable GHES either at
  72           compilation time or by passing "ghes.disable=1" Kernel parameter
  73           at boot time.
  74
  75           In doubt, say 'Y'.
  76
  77 config EDAC_AMD64
  78         tristate "AMD64 (Opteron, Athlon64)"
  79         depends on AMD_NB && EDAC_DECODE_MCE
  80         help
  81           Support for error detection and correction of DRAM ECC errors on
  82           the AMD64 families (>= K8) of memory controllers.
  83
  84 config EDAC_AMD64_ERROR_INJECTION
  85         bool "Sysfs HW Error injection facilities"
  86         depends on EDAC_AMD64
  87         help
  88           Recent Opterons (Family 10h and later) provide for Memory Error
  89           Injection into the ECC detection circuits. The amd64_edac module
  90           allows the operator/user to inject Uncorrectable and Correctable
  91           errors into DRAM.
  92
  93           When enabled, in each of the respective memory controller directories
  94           (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  95
  96           - inject_section (0..3, 16-byte section of 64-byte cacheline),
  97           - inject_word (0..8, 16-bit word of 16-byte section),
  98           - inject_ecc_vector (hex ecc vector: select bits of inject word)
  99
 100           In addition, there are two control files, inject_read and inject_write,
 101           which trigger the DRAM ECC Read and Write respectively.
 102
 103 config EDAC_AMD76X
 104         tristate "AMD 76x (760, 762, 768)"
 105         depends on PCI && X86_32
 106         help
 107           Support for error detection and correction on the AMD 76x
 108           series of chipsets used with the Athlon processor.
 109
 110 config EDAC_E7XXX
 111         tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
 112         depends on PCI && X86_32
 113         help
 114           Support for error detection and correction on the Intel
 115           E7205, E7500, E7501 and E7505 server chipsets.
 116
 117 config EDAC_E752X
 118         tristate "Intel e752x (e7520, e7525, e7320) and 3100"
 119         depends on PCI && X86
 120         help
 121           Support for error detection and correction on the Intel
 122           E7520, E7525, E7320 server chipsets.
 123
 124 config EDAC_I82443BXGX
 125         tristate "Intel 82443BX/GX (440BX/GX)"
 126         depends on PCI && X86_32
 127         depends on BROKEN
 128         help
 129           Support for error detection and correction on the Intel
 130           82443BX/GX memory controllers (440BX/GX chipsets).
 131
 132 config EDAC_I82875P
 133         tristate "Intel 82875p (D82875P, E7210)"
 134         depends on PCI && X86_32
 135         help
 136           Support for error detection and correction on the Intel
 137           DP82785P and E7210 server chipsets.
 138
 139 config EDAC_I82975X
 140         tristate "Intel 82975x (D82975x)"
 141         depends on PCI && X86
 142         help
 143           Support for error detection and correction on the Intel
 144           DP82975x server chipsets.
 145
 146 config EDAC_I3000
 147         tristate "Intel 3000/3010"
 148         depends on PCI && X86
 149         help
 150           Support for error detection and correction on the Intel
 151           3000 and 3010 server chipsets.
 152
 153 config EDAC_I3200
 154         tristate "Intel 3200"
 155         depends on PCI && X86
 156         help
 157           Support for error detection and correction on the Intel
 158           3200 and 3210 server chipsets.
 159
 160 config EDAC_IE31200
 161         tristate "Intel e312xx"
 162         depends on PCI && X86
 163         help
 164           Support for error detection and correction on the Intel
 165           E3-1200 based DRAM controllers.
 166
 167 config EDAC_X38
 168         tristate "Intel X38"
 169         depends on PCI && X86
 170         help
 171           Support for error detection and correction on the Intel
 172           X38 server chipsets.
 173
 174 config EDAC_I5400
 175         tristate "Intel 5400 (Seaburg) chipsets"
 176         depends on PCI && X86
 177         help
 178           Support for error detection and correction the Intel
 179           i5400 MCH chipset (Seaburg).
 180
 181 config EDAC_I7CORE
 182         tristate "Intel i7 Core (Nehalem) processors"
 183         depends on PCI && X86 && X86_MCE_INTEL
 184         help
 185           Support for error detection and correction the Intel
 186           i7 Core (Nehalem) Integrated Memory Controller that exists on
 187           newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
 188           and Xeon 55xx processors.
 189
 190 config EDAC_I82860
 191         tristate "Intel 82860"
 192         depends on PCI && X86_32
 193         help
 194           Support for error detection and correction on the Intel
 195           82860 chipset.
 196
 197 config EDAC_R82600
 198         tristate "Radisys 82600 embedded chipset"
 199         depends on PCI && X86_32
 200         help
 201           Support for error detection and correction on the Radisys
 202           82600 embedded chipset.
 203
 204 config EDAC_I5000
 205         tristate "Intel Greencreek/Blackford chipset"
 206         depends on X86 && PCI
 207         help
 208           Support for error detection and correction the Intel
 209           Greekcreek/Blackford chipsets.
 210
 211 config EDAC_I5100
 212         tristate "Intel San Clemente MCH"
 213         depends on X86 && PCI
 214         help
 215           Support for error detection and correction the Intel
 216           San Clemente MCH.
 217
 218 config EDAC_I7300
 219         tristate "Intel Clarksboro MCH"
 220         depends on X86 && PCI
 221         help
 222           Support for error detection and correction the Intel
 223           Clarksboro MCH (Intel 7300 chipset).
 224
 225 config EDAC_SBRIDGE
 226         tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
 227         depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
 228         help
 229           Support for error detection and correction the Intel
 230           Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
 231
 232 config EDAC_SKX
 233         tristate "Intel Skylake server Integrated MC"
 234         depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
 235         depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
 236         select DMI
 237         select ACPI_ADXL
 238         help
 239           Support for error detection and correction the Intel
 240           Skylake server Integrated Memory Controllers. If your
 241           system has non-volatile DIMMs you should also manually
 242           select CONFIG_ACPI_NFIT.
 243
 244 config EDAC_I10NM
 245         tristate "Intel 10nm server Integrated MC"
 246         depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
 247         depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
 248         select DMI
 249         select ACPI_ADXL
 250         help
 251           Support for error detection and correction the Intel
 252           10nm server Integrated Memory Controllers. If your
 253           system has non-volatile DIMMs you should also manually
 254           select CONFIG_ACPI_NFIT.
 255
 256 config EDAC_PND2
 257         tristate "Intel Pondicherry2"
 258         depends on PCI && X86_64 && X86_MCE_INTEL
 259         help
 260           Support for error detection and correction on the Intel
 261           Pondicherry2 Integrated Memory Controller. This SoC IP is
 262           first used on the Apollo Lake platform and Denverton
 263           micro-server but may appear on others in the future.
 264
 265 config EDAC_MPC85XX
 266         tristate "Freescale MPC83xx / MPC85xx"
 267         depends on FSL_SOC
 268         help
 269           Support for error detection and correction on the Freescale
 270           MPC8349, MPC8560, MPC8540, MPC8548, T4240
 271
 272 config EDAC_LAYERSCAPE
 273         tristate "Freescale Layerscape DDR"
 274         depends on ARCH_LAYERSCAPE || SOC_LS1021A
 275         help
 276           Support for error detection and correction on Freescale memory
 277           controllers on Layerscape SoCs.
 278
 279 config EDAC_MV64X60
 280         tristate "Marvell MV64x60"
 281         depends on MV64X60
 282         help
 283           Support for error detection and correction on the Marvell
 284           MV64360 and MV64460 chipsets.
 285
 286 config EDAC_PASEMI
 287         tristate "PA Semi PWRficient"
 288         depends on PPC_PASEMI && PCI
 289         help
 290           Support for error detection and correction on PA Semi
 291           PWRficient.
 292
 293 config EDAC_CELL
 294         tristate "Cell Broadband Engine memory controller"
 295         depends on PPC_CELL_COMMON
 296         help
 297           Support for error detection and correction on the
 298           Cell Broadband Engine internal memory controller
 299           on platform without a hypervisor
 300
 301 config EDAC_PPC4XX
 302         tristate "PPC4xx IBM DDR2 Memory Controller"
 303         depends on 4xx
 304         help
 305           This enables support for EDAC on the ECC memory used
 306           with the IBM DDR2 memory controller found in various
 307           PowerPC 4xx embedded processors such as the 405EX[r],
 308           440SP, 440SPe, 460EX, 460GT and 460SX.
 309
 310 config EDAC_AMD8131
 311         tristate "AMD8131 HyperTransport PCI-X Tunnel"
 312         depends on PCI && PPC_MAPLE
 313         help
 314           Support for error detection and correction on the
 315           AMD8131 HyperTransport PCI-X Tunnel chip.
 316           Note, add more Kconfig dependency if it's adopted
 317           on some machine other than Maple.
 318
 319 config EDAC_AMD8111
 320         tristate "AMD8111 HyperTransport I/O Hub"
 321         depends on PCI && PPC_MAPLE
 322         help
 323           Support for error detection and correction on the
 324           AMD8111 HyperTransport I/O Hub chip.
 325           Note, add more Kconfig dependency if it's adopted
 326           on some machine other than Maple.
 327
 328 config EDAC_CPC925
 329         tristate "IBM CPC925 Memory Controller (PPC970FX)"
 330         depends on PPC64
 331         help
 332           Support for error detection and correction on the
 333           IBM CPC925 Bridge and Memory Controller, which is
 334           a companion chip to the PowerPC 970 family of
 335           processors.
 336
 337 config EDAC_HIGHBANK_MC
 338         tristate "Highbank Memory Controller"
 339         depends on ARCH_HIGHBANK
 340         help
 341           Support for error detection and correction on the
 342           Calxeda Highbank memory controller.
 343
 344 config EDAC_HIGHBANK_L2
 345         tristate "Highbank L2 Cache"
 346         depends on ARCH_HIGHBANK
 347         help
 348           Support for error detection and correction on the
 349           Calxeda Highbank memory controller.
 350
 351 config EDAC_OCTEON_PC
 352         tristate "Cavium Octeon Primary Caches"
 353         depends on CPU_CAVIUM_OCTEON
 354         help
 355           Support for error detection and correction on the primary caches of
 356           the cnMIPS cores of Cavium Octeon family SOCs.
 357
 358 config EDAC_OCTEON_L2C
 359         tristate "Cavium Octeon Secondary Caches (L2C)"
 360         depends on CAVIUM_OCTEON_SOC
 361         help
 362           Support for error detection and correction on the
 363           Cavium Octeon family of SOCs.
 364
 365 config EDAC_OCTEON_LMC
 366         tristate "Cavium Octeon DRAM Memory Controller (LMC)"
 367         depends on CAVIUM_OCTEON_SOC
 368         help
 369           Support for error detection and correction on the
 370           Cavium Octeon family of SOCs.
 371
 372 config EDAC_OCTEON_PCI
 373         tristate "Cavium Octeon PCI Controller"
 374         depends on PCI && CAVIUM_OCTEON_SOC
 375         help
 376           Support for error detection and correction on the
 377           Cavium Octeon family of SOCs.
 378
 379 config EDAC_THUNDERX
 380         tristate "Cavium ThunderX EDAC"
 381         depends on ARM64
 382         depends on PCI
 383         help
 384           Support for error detection and correction on the
 385           Cavium ThunderX memory controllers (LMC), Cache
 386           Coherent Processor Interconnect (CCPI) and L2 cache
 387           blocks (TAD, CBC, MCI).
 388
 389 config EDAC_ALTERA
 390         bool "Altera SOCFPGA ECC"
 391         depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
 392         help
 393           Support for error detection and correction on the
 394           Altera SOCs. This is the global enable for the
 395           various Altera peripherals.
 396
 397 config EDAC_ALTERA_SDRAM
 398         bool "Altera SDRAM ECC"
 399         depends on EDAC_ALTERA=y
 400         help
 401           Support for error detection and correction on the
 402           Altera SDRAM Memory for Altera SoCs. Note that the
 403           preloader must initialize the SDRAM before loading
 404           the kernel.
 405
 406 config EDAC_ALTERA_L2C
 407         bool "Altera L2 Cache ECC"
 408         depends on EDAC_ALTERA=y && CACHE_L2X0
 409         help
 410           Support for error detection and correction on the
 411           Altera L2 cache Memory for Altera SoCs. This option
 412           requires L2 cache.
 413
 414 config EDAC_ALTERA_OCRAM
 415         bool "Altera On-Chip RAM ECC"
 416         depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
 417         help
 418           Support for error detection and correction on the
 419           Altera On-Chip RAM Memory for Altera SoCs.
 420
 421 config EDAC_ALTERA_ETHERNET
 422         bool "Altera Ethernet FIFO ECC"
 423         depends on EDAC_ALTERA=y
 424         help
 425           Support for error detection and correction on the
 426           Altera Ethernet FIFO Memory for Altera SoCs.
 427
 428 config EDAC_ALTERA_NAND
 429         bool "Altera NAND FIFO ECC"
 430         depends on EDAC_ALTERA=y && MTD_NAND_DENALI
 431         help
 432           Support for error detection and correction on the
 433           Altera NAND FIFO Memory for Altera SoCs.
 434
 435 config EDAC_ALTERA_DMA
 436         bool "Altera DMA FIFO ECC"
 437         depends on EDAC_ALTERA=y && PL330_DMA=y
 438         help
 439           Support for error detection and correction on the
 440           Altera DMA FIFO Memory for Altera SoCs.
 441
 442 config EDAC_ALTERA_USB
 443         bool "Altera USB FIFO ECC"
 444         depends on EDAC_ALTERA=y && USB_DWC2
 445         help
 446           Support for error detection and correction on the
 447           Altera USB FIFO Memory for Altera SoCs.
 448
 449 config EDAC_ALTERA_QSPI
 450         bool "Altera QSPI FIFO ECC"
 451         depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
 452         help
 453           Support for error detection and correction on the
 454           Altera QSPI FIFO Memory for Altera SoCs.
 455
 456 config EDAC_ALTERA_SDMMC
 457         bool "Altera SDMMC FIFO ECC"
 458         depends on EDAC_ALTERA=y && MMC_DW
 459         help
 460           Support for error detection and correction on the
 461           Altera SDMMC FIFO Memory for Altera SoCs.
 462
 463 config EDAC_SYNOPSYS
 464         tristate "Synopsys DDR Memory Controller"
 465         depends on ARCH_ZYNQ || ARCH_ZYNQMP
 466         help
 467           Support for error detection and correction on the Synopsys DDR
 468           memory controller.
 469
 470 config EDAC_XGENE
 471         tristate "APM X-Gene SoC"
 472         depends on (ARM64 || COMPILE_TEST)
 473         help
 474           Support for error detection and correction on the
 475           APM X-Gene family of SOCs.
 476
 477 config EDAC_TI
 478         tristate "Texas Instruments DDR3 ECC Controller"
 479         depends on ARCH_KEYSTONE || SOC_DRA7XX
 480         help
 481           Support for error detection and correction on the
 482           TI SoCs.
 483
 484 config EDAC_QCOM
 485         tristate "QCOM EDAC Controller"
 486         depends on ARCH_QCOM && QCOM_LLCC
 487         help
 488           Support for error detection and correction on the
 489           Qualcomm Technologies, Inc. SoCs.
 490
 491           This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
 492           As of now, it supports error reporting for Last Level Cache Controller (LLCC)
 493           of Tag RAM and Data RAM.
 494
 495           For debugging issues having to do with stability and overall system
 496           health, you should probably say 'Y' here.
 497
 498 config EDAC_ASPEED
 499         tristate "Aspeed AST 2500 SoC"
 500         depends on MACH_ASPEED_G5
 501         help
 502           Support for error detection and correction on the Aspeed AST 2500 SoC.
 503
 504           First, ECC must be configured in the bootloader. Then, this driver
 505           will expose error counters via the EDAC kernel framework.
 506
 507 endif # EDAC