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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[people/ms/linux.git] / drivers / firewire / ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
61 #define DESCRIPTOR_OUTPUT_MORE 0
62 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63 #define DESCRIPTOR_INPUT_MORE (2 << 12)
64 #define DESCRIPTOR_INPUT_LAST (3 << 12)
65 #define DESCRIPTOR_STATUS (1 << 11)
66 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67 #define DESCRIPTOR_PING (1 << 7)
68 #define DESCRIPTOR_YY (1 << 6)
69 #define DESCRIPTOR_NO_IRQ (0 << 4)
70 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
71 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73 #define DESCRIPTOR_WAIT (3 << 0)
74
75 #define DESCRIPTOR_CMD (0xf << 12)
76
77 struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84 } __attribute__((aligned(16)));
85
86 #define CONTROL_SET(regs) (regs)
87 #define CONTROL_CLEAR(regs) ((regs) + 4)
88 #define COMMAND_PTR(regs) ((regs) + 12)
89 #define CONTEXT_MATCH(regs) ((regs) + 16)
90
91 #define AR_BUFFER_SIZE (32*1024)
92 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93 /* we need at least two pages for proper list management */
94 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96 #define MAX_ASYNC_PAYLOAD 4096
97 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
99
100 struct ar_context {
101 struct fw_ohci *ohci;
102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
106 void *pointer;
107 unsigned int last_buffer_index;
108 u32 regs;
109 struct tasklet_struct tasklet;
110 };
111
112 struct context;
113
114 typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
117
118 /*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122 struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128 };
129
130 struct context {
131 struct fw_ohci *ohci;
132 u32 regs;
133 int total_allocation;
134 u32 current_bus;
135 bool running;
136 bool flushing;
137
138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
158 * The last descriptor block in the DMA program. It contains the branch
159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
162 int prev_z;
163
164 descriptor_callback_t callback;
165
166 struct tasklet_struct tasklet;
167 };
168
169 #define IT_HEADER_SY(v) ((v) << 0)
170 #define IT_HEADER_TCODE(v) ((v) << 4)
171 #define IT_HEADER_CHANNEL(v) ((v) << 8)
172 #define IT_HEADER_TAG(v) ((v) << 14)
173 #define IT_HEADER_SPEED(v) ((v) << 16)
174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
175
176 struct iso_context {
177 struct fw_iso_context base;
178 struct context context;
179 void *header;
180 size_t header_length;
181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
184 u16 last_timestamp;
185 u8 sync;
186 u8 tags;
187 };
188
189 #define CONFIG_ROM_SIZE 1024
190
191 struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
195 int node_id;
196 int generation;
197 int request_generation; /* for timestamping incoming requests */
198 unsigned quirks;
199 unsigned int pri_req_max;
200 u32 bus_time;
201 bool bus_time_running;
202 bool is_root;
203 bool csr_state_setclear_abdicate;
204 int n_ir;
205 int n_it;
206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
210 spinlock_t lock;
211
212 struct mutex phy_reg_mutex;
213
214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
219 struct context at_request_ctx;
220 struct context at_response_ctx;
221
222 u32 it_context_support;
223 u32 it_context_mask; /* unoccupied IT contexts */
224 struct iso_context *it_context_list;
225 u64 ir_context_channels; /* unoccupied channels */
226 u32 ir_context_support;
227 u32 ir_context_mask; /* unoccupied IR contexts */
228 struct iso_context *ir_context_list;
229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
238 __le32 *self_id;
239 dma_addr_t self_id_bus;
240 struct work_struct bus_reset_work;
241
242 u32 self_id_buffer[512];
243 };
244
245 static struct workqueue_struct *selfid_workqueue;
246
247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
248 {
249 return container_of(card, struct fw_ohci, card);
250 }
251
252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253 #define IR_CONTEXT_BUFFER_FILL 0x80000000
254 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
258
259 #define CONTEXT_RUN 0x8000
260 #define CONTEXT_WAKE 0x1000
261 #define CONTEXT_DEAD 0x0800
262 #define CONTEXT_ACTIVE 0x0400
263
264 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
265 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
268 #define OHCI1394_REGISTER_SIZE 0x800
269 #define OHCI1394_PCI_HCI_Control 0x40
270 #define SELF_ID_BUF_SIZE 0x800
271 #define OHCI_TCODE_PHY_PACKET 0x0e
272 #define OHCI_VERSION_1_1 0x010010
273
274 static char ohci_driver_name[] = KBUILD_MODNAME;
275
276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
277 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
278 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
280 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
281 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
283 #define PCI_DEVICE_ID_VIA_VT630X 0x3044
284 #define PCI_REV_ID_VIA_VT6306 0x46
285 #define PCI_DEVICE_ID_VIA_VT6315 0x3403
286
287 #define QUIRK_CYCLE_TIMER 0x1
288 #define QUIRK_RESET_PACKET 0x2
289 #define QUIRK_BE_HEADERS 0x4
290 #define QUIRK_NO_1394A 0x8
291 #define QUIRK_NO_MSI 0x10
292 #define QUIRK_TI_SLLZ059 0x20
293 #define QUIRK_IR_WAKE 0x40
294
295 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
296 static const struct {
297 unsigned short vendor, device, revision, flags;
298 } ohci_quirks[] = {
299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
306 QUIRK_NO_MSI},
307
308 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
309 QUIRK_RESET_PACKET},
310
311 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
312 QUIRK_NO_MSI},
313
314 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_CYCLE_TIMER},
316
317 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_NO_MSI},
319
320 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
321 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
324 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
332 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
333 QUIRK_RESET_PACKET},
334
335 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
336 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
337
338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
339 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
340
341 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
342 QUIRK_NO_MSI},
343
344 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
345 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
346 };
347
348 /* This overrides anything that was found in ohci_quirks[]. */
349 static int param_quirks;
350 module_param_named(quirks, param_quirks, int, 0644);
351 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
352 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
353 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
354 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
355 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
356 ", disable MSI = " __stringify(QUIRK_NO_MSI)
357 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
358 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
359 ")");
360
361 #define OHCI_PARAM_DEBUG_AT_AR 1
362 #define OHCI_PARAM_DEBUG_SELFIDS 2
363 #define OHCI_PARAM_DEBUG_IRQS 4
364 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
365
366 static int param_debug;
367 module_param_named(debug, param_debug, int, 0644);
368 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
369 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
370 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
371 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
372 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
373 ", or a combination, or all = -1)");
374
375 static bool param_remote_dma;
376 module_param_named(remote_dma, param_remote_dma, bool, 0444);
377 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
378
379 static void log_irqs(struct fw_ohci *ohci, u32 evt)
380 {
381 if (likely(!(param_debug &
382 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
383 return;
384
385 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
386 !(evt & OHCI1394_busReset))
387 return;
388
389 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
390 evt & OHCI1394_selfIDComplete ? " selfID" : "",
391 evt & OHCI1394_RQPkt ? " AR_req" : "",
392 evt & OHCI1394_RSPkt ? " AR_resp" : "",
393 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
394 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
395 evt & OHCI1394_isochRx ? " IR" : "",
396 evt & OHCI1394_isochTx ? " IT" : "",
397 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
398 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
399 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
400 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
401 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
402 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
403 evt & OHCI1394_busReset ? " busReset" : "",
404 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
405 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
406 OHCI1394_respTxComplete | OHCI1394_isochRx |
407 OHCI1394_isochTx | OHCI1394_postedWriteErr |
408 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
409 OHCI1394_cycleInconsistent |
410 OHCI1394_regAccessFail | OHCI1394_busReset)
411 ? " ?" : "");
412 }
413
414 static const char *speed[] = {
415 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
416 };
417 static const char *power[] = {
418 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
419 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
420 };
421 static const char port[] = { '.', '-', 'p', 'c', };
422
423 static char _p(u32 *s, int shift)
424 {
425 return port[*s >> shift & 3];
426 }
427
428 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
429 {
430 u32 *s;
431
432 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
433 return;
434
435 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
436 self_id_count, generation, ohci->node_id);
437
438 for (s = ohci->self_id_buffer; self_id_count--; ++s)
439 if ((*s & 1 << 23) == 0)
440 ohci_notice(ohci,
441 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
442 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
443 speed[*s >> 14 & 3], *s >> 16 & 63,
444 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
445 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
446 else
447 ohci_notice(ohci,
448 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
449 *s, *s >> 24 & 63,
450 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
451 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
452 }
453
454 static const char *evts[] = {
455 [0x00] = "evt_no_status", [0x01] = "-reserved-",
456 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
457 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
458 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
459 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
460 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
461 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
462 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
463 [0x10] = "-reserved-", [0x11] = "ack_complete",
464 [0x12] = "ack_pending ", [0x13] = "-reserved-",
465 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
466 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
467 [0x18] = "-reserved-", [0x19] = "-reserved-",
468 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
469 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
470 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
471 [0x20] = "pending/cancelled",
472 };
473 static const char *tcodes[] = {
474 [0x0] = "QW req", [0x1] = "BW req",
475 [0x2] = "W resp", [0x3] = "-reserved-",
476 [0x4] = "QR req", [0x5] = "BR req",
477 [0x6] = "QR resp", [0x7] = "BR resp",
478 [0x8] = "cycle start", [0x9] = "Lk req",
479 [0xa] = "async stream packet", [0xb] = "Lk resp",
480 [0xc] = "-reserved-", [0xd] = "-reserved-",
481 [0xe] = "link internal", [0xf] = "-reserved-",
482 };
483
484 static void log_ar_at_event(struct fw_ohci *ohci,
485 char dir, int speed, u32 *header, int evt)
486 {
487 int tcode = header[0] >> 4 & 0xf;
488 char specific[12];
489
490 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
491 return;
492
493 if (unlikely(evt >= ARRAY_SIZE(evts)))
494 evt = 0x1f;
495
496 if (evt == OHCI1394_evt_bus_reset) {
497 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
498 dir, (header[2] >> 16) & 0xff);
499 return;
500 }
501
502 switch (tcode) {
503 case 0x0: case 0x6: case 0x8:
504 snprintf(specific, sizeof(specific), " = %08x",
505 be32_to_cpu((__force __be32)header[3]));
506 break;
507 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
508 snprintf(specific, sizeof(specific), " %x,%x",
509 header[3] >> 16, header[3] & 0xffff);
510 break;
511 default:
512 specific[0] = '\0';
513 }
514
515 switch (tcode) {
516 case 0xa:
517 ohci_notice(ohci, "A%c %s, %s\n",
518 dir, evts[evt], tcodes[tcode]);
519 break;
520 case 0xe:
521 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
522 dir, evts[evt], header[1], header[2]);
523 break;
524 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
525 ohci_notice(ohci,
526 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
527 dir, speed, header[0] >> 10 & 0x3f,
528 header[1] >> 16, header[0] >> 16, evts[evt],
529 tcodes[tcode], header[1] & 0xffff, header[2], specific);
530 break;
531 default:
532 ohci_notice(ohci,
533 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
534 dir, speed, header[0] >> 10 & 0x3f,
535 header[1] >> 16, header[0] >> 16, evts[evt],
536 tcodes[tcode], specific);
537 }
538 }
539
540 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
541 {
542 writel(data, ohci->registers + offset);
543 }
544
545 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
546 {
547 return readl(ohci->registers + offset);
548 }
549
550 static inline void flush_writes(const struct fw_ohci *ohci)
551 {
552 /* Do a dummy read to flush writes. */
553 reg_read(ohci, OHCI1394_Version);
554 }
555
556 /*
557 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
558 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
559 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
560 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
561 */
562 static int read_phy_reg(struct fw_ohci *ohci, int addr)
563 {
564 u32 val;
565 int i;
566
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
568 for (i = 0; i < 3 + 100; i++) {
569 val = reg_read(ohci, OHCI1394_PhyControl);
570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
573 if (val & OHCI1394_PhyControl_ReadDone)
574 return OHCI1394_PhyControl_ReadData(val);
575
576 /*
577 * Try a few times without waiting. Sleeping is necessary
578 * only when the link/PHY interface is busy.
579 */
580 if (i >= 3)
581 msleep(1);
582 }
583 ohci_err(ohci, "failed to read phy reg %d\n", addr);
584 dump_stack();
585
586 return -EBUSY;
587 }
588
589 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
590 {
591 int i;
592
593 reg_write(ohci, OHCI1394_PhyControl,
594 OHCI1394_PhyControl_Write(addr, val));
595 for (i = 0; i < 3 + 100; i++) {
596 val = reg_read(ohci, OHCI1394_PhyControl);
597 if (!~val)
598 return -ENODEV; /* Card was ejected. */
599
600 if (!(val & OHCI1394_PhyControl_WritePending))
601 return 0;
602
603 if (i >= 3)
604 msleep(1);
605 }
606 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
607 dump_stack();
608
609 return -EBUSY;
610 }
611
612 static int update_phy_reg(struct fw_ohci *ohci, int addr,
613 int clear_bits, int set_bits)
614 {
615 int ret = read_phy_reg(ohci, addr);
616 if (ret < 0)
617 return ret;
618
619 /*
620 * The interrupt status bits are cleared by writing a one bit.
621 * Avoid clearing them unless explicitly requested in set_bits.
622 */
623 if (addr == 5)
624 clear_bits |= PHY_INT_STATUS_BITS;
625
626 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
627 }
628
629 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
630 {
631 int ret;
632
633 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
634 if (ret < 0)
635 return ret;
636
637 return read_phy_reg(ohci, addr);
638 }
639
640 static int ohci_read_phy_reg(struct fw_card *card, int addr)
641 {
642 struct fw_ohci *ohci = fw_ohci(card);
643 int ret;
644
645 mutex_lock(&ohci->phy_reg_mutex);
646 ret = read_phy_reg(ohci, addr);
647 mutex_unlock(&ohci->phy_reg_mutex);
648
649 return ret;
650 }
651
652 static int ohci_update_phy_reg(struct fw_card *card, int addr,
653 int clear_bits, int set_bits)
654 {
655 struct fw_ohci *ohci = fw_ohci(card);
656 int ret;
657
658 mutex_lock(&ohci->phy_reg_mutex);
659 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
660 mutex_unlock(&ohci->phy_reg_mutex);
661
662 return ret;
663 }
664
665 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
666 {
667 return page_private(ctx->pages[i]);
668 }
669
670 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
671 {
672 struct descriptor *d;
673
674 d = &ctx->descriptors[index];
675 d->branch_address &= cpu_to_le32(~0xf);
676 d->res_count = cpu_to_le16(PAGE_SIZE);
677 d->transfer_status = 0;
678
679 wmb(); /* finish init of new descriptors before branch_address update */
680 d = &ctx->descriptors[ctx->last_buffer_index];
681 d->branch_address |= cpu_to_le32(1);
682
683 ctx->last_buffer_index = index;
684
685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
686 }
687
688 static void ar_context_release(struct ar_context *ctx)
689 {
690 unsigned int i;
691
692 vunmap(ctx->buffer);
693
694 for (i = 0; i < AR_BUFFERS; i++)
695 if (ctx->pages[i]) {
696 dma_unmap_page(ctx->ohci->card.device,
697 ar_buffer_bus(ctx, i),
698 PAGE_SIZE, DMA_FROM_DEVICE);
699 __free_page(ctx->pages[i]);
700 }
701 }
702
703 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
704 {
705 struct fw_ohci *ohci = ctx->ohci;
706
707 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
708 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
709 flush_writes(ohci);
710
711 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
712 }
713 /* FIXME: restart? */
714 }
715
716 static inline unsigned int ar_next_buffer_index(unsigned int index)
717 {
718 return (index + 1) % AR_BUFFERS;
719 }
720
721 static inline unsigned int ar_prev_buffer_index(unsigned int index)
722 {
723 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
724 }
725
726 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
727 {
728 return ar_next_buffer_index(ctx->last_buffer_index);
729 }
730
731 /*
732 * We search for the buffer that contains the last AR packet DMA data written
733 * by the controller.
734 */
735 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
736 unsigned int *buffer_offset)
737 {
738 unsigned int i, next_i, last = ctx->last_buffer_index;
739 __le16 res_count, next_res_count;
740
741 i = ar_first_buffer_index(ctx);
742 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
743
744 /* A buffer that is not yet completely filled must be the last one. */
745 while (i != last && res_count == 0) {
746
747 /* Peek at the next descriptor. */
748 next_i = ar_next_buffer_index(i);
749 rmb(); /* read descriptors in order */
750 next_res_count = ACCESS_ONCE(
751 ctx->descriptors[next_i].res_count);
752 /*
753 * If the next descriptor is still empty, we must stop at this
754 * descriptor.
755 */
756 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
757 /*
758 * The exception is when the DMA data for one packet is
759 * split over three buffers; in this case, the middle
760 * buffer's descriptor might be never updated by the
761 * controller and look still empty, and we have to peek
762 * at the third one.
763 */
764 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
765 next_i = ar_next_buffer_index(next_i);
766 rmb();
767 next_res_count = ACCESS_ONCE(
768 ctx->descriptors[next_i].res_count);
769 if (next_res_count != cpu_to_le16(PAGE_SIZE))
770 goto next_buffer_is_active;
771 }
772
773 break;
774 }
775
776 next_buffer_is_active:
777 i = next_i;
778 res_count = next_res_count;
779 }
780
781 rmb(); /* read res_count before the DMA data */
782
783 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
784 if (*buffer_offset > PAGE_SIZE) {
785 *buffer_offset = 0;
786 ar_context_abort(ctx, "corrupted descriptor");
787 }
788
789 return i;
790 }
791
792 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
793 unsigned int end_buffer_index,
794 unsigned int end_buffer_offset)
795 {
796 unsigned int i;
797
798 i = ar_first_buffer_index(ctx);
799 while (i != end_buffer_index) {
800 dma_sync_single_for_cpu(ctx->ohci->card.device,
801 ar_buffer_bus(ctx, i),
802 PAGE_SIZE, DMA_FROM_DEVICE);
803 i = ar_next_buffer_index(i);
804 }
805 if (end_buffer_offset > 0)
806 dma_sync_single_for_cpu(ctx->ohci->card.device,
807 ar_buffer_bus(ctx, i),
808 end_buffer_offset, DMA_FROM_DEVICE);
809 }
810
811 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
812 #define cond_le32_to_cpu(v) \
813 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
814 #else
815 #define cond_le32_to_cpu(v) le32_to_cpu(v)
816 #endif
817
818 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
819 {
820 struct fw_ohci *ohci = ctx->ohci;
821 struct fw_packet p;
822 u32 status, length, tcode;
823 int evt;
824
825 p.header[0] = cond_le32_to_cpu(buffer[0]);
826 p.header[1] = cond_le32_to_cpu(buffer[1]);
827 p.header[2] = cond_le32_to_cpu(buffer[2]);
828
829 tcode = (p.header[0] >> 4) & 0x0f;
830 switch (tcode) {
831 case TCODE_WRITE_QUADLET_REQUEST:
832 case TCODE_READ_QUADLET_RESPONSE:
833 p.header[3] = (__force __u32) buffer[3];
834 p.header_length = 16;
835 p.payload_length = 0;
836 break;
837
838 case TCODE_READ_BLOCK_REQUEST :
839 p.header[3] = cond_le32_to_cpu(buffer[3]);
840 p.header_length = 16;
841 p.payload_length = 0;
842 break;
843
844 case TCODE_WRITE_BLOCK_REQUEST:
845 case TCODE_READ_BLOCK_RESPONSE:
846 case TCODE_LOCK_REQUEST:
847 case TCODE_LOCK_RESPONSE:
848 p.header[3] = cond_le32_to_cpu(buffer[3]);
849 p.header_length = 16;
850 p.payload_length = p.header[3] >> 16;
851 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
852 ar_context_abort(ctx, "invalid packet length");
853 return NULL;
854 }
855 break;
856
857 case TCODE_WRITE_RESPONSE:
858 case TCODE_READ_QUADLET_REQUEST:
859 case OHCI_TCODE_PHY_PACKET:
860 p.header_length = 12;
861 p.payload_length = 0;
862 break;
863
864 default:
865 ar_context_abort(ctx, "invalid tcode");
866 return NULL;
867 }
868
869 p.payload = (void *) buffer + p.header_length;
870
871 /* FIXME: What to do about evt_* errors? */
872 length = (p.header_length + p.payload_length + 3) / 4;
873 status = cond_le32_to_cpu(buffer[length]);
874 evt = (status >> 16) & 0x1f;
875
876 p.ack = evt - 16;
877 p.speed = (status >> 21) & 0x7;
878 p.timestamp = status & 0xffff;
879 p.generation = ohci->request_generation;
880
881 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
882
883 /*
884 * Several controllers, notably from NEC and VIA, forget to
885 * write ack_complete status at PHY packet reception.
886 */
887 if (evt == OHCI1394_evt_no_status &&
888 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
889 p.ack = ACK_COMPLETE;
890
891 /*
892 * The OHCI bus reset handler synthesizes a PHY packet with
893 * the new generation number when a bus reset happens (see
894 * section 8.4.2.3). This helps us determine when a request
895 * was received and make sure we send the response in the same
896 * generation. We only need this for requests; for responses
897 * we use the unique tlabel for finding the matching
898 * request.
899 *
900 * Alas some chips sometimes emit bus reset packets with a
901 * wrong generation. We set the correct generation for these
902 * at a slightly incorrect time (in bus_reset_work).
903 */
904 if (evt == OHCI1394_evt_bus_reset) {
905 if (!(ohci->quirks & QUIRK_RESET_PACKET))
906 ohci->request_generation = (p.header[2] >> 16) & 0xff;
907 } else if (ctx == &ohci->ar_request_ctx) {
908 fw_core_handle_request(&ohci->card, &p);
909 } else {
910 fw_core_handle_response(&ohci->card, &p);
911 }
912
913 return buffer + length + 1;
914 }
915
916 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
917 {
918 void *next;
919
920 while (p < end) {
921 next = handle_ar_packet(ctx, p);
922 if (!next)
923 return p;
924 p = next;
925 }
926
927 return p;
928 }
929
930 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
931 {
932 unsigned int i;
933
934 i = ar_first_buffer_index(ctx);
935 while (i != end_buffer) {
936 dma_sync_single_for_device(ctx->ohci->card.device,
937 ar_buffer_bus(ctx, i),
938 PAGE_SIZE, DMA_FROM_DEVICE);
939 ar_context_link_page(ctx, i);
940 i = ar_next_buffer_index(i);
941 }
942 }
943
944 static void ar_context_tasklet(unsigned long data)
945 {
946 struct ar_context *ctx = (struct ar_context *)data;
947 unsigned int end_buffer_index, end_buffer_offset;
948 void *p, *end;
949
950 p = ctx->pointer;
951 if (!p)
952 return;
953
954 end_buffer_index = ar_search_last_active_buffer(ctx,
955 &end_buffer_offset);
956 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
957 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
958
959 if (end_buffer_index < ar_first_buffer_index(ctx)) {
960 /*
961 * The filled part of the overall buffer wraps around; handle
962 * all packets up to the buffer end here. If the last packet
963 * wraps around, its tail will be visible after the buffer end
964 * because the buffer start pages are mapped there again.
965 */
966 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
967 p = handle_ar_packets(ctx, p, buffer_end);
968 if (p < buffer_end)
969 goto error;
970 /* adjust p to point back into the actual buffer */
971 p -= AR_BUFFERS * PAGE_SIZE;
972 }
973
974 p = handle_ar_packets(ctx, p, end);
975 if (p != end) {
976 if (p > end)
977 ar_context_abort(ctx, "inconsistent descriptor");
978 goto error;
979 }
980
981 ctx->pointer = p;
982 ar_recycle_buffers(ctx, end_buffer_index);
983
984 return;
985
986 error:
987 ctx->pointer = NULL;
988 }
989
990 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
991 unsigned int descriptors_offset, u32 regs)
992 {
993 unsigned int i;
994 dma_addr_t dma_addr;
995 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
996 struct descriptor *d;
997
998 ctx->regs = regs;
999 ctx->ohci = ohci;
1000 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
1001
1002 for (i = 0; i < AR_BUFFERS; i++) {
1003 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
1004 if (!ctx->pages[i])
1005 goto out_of_memory;
1006 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1007 0, PAGE_SIZE, DMA_FROM_DEVICE);
1008 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1009 __free_page(ctx->pages[i]);
1010 ctx->pages[i] = NULL;
1011 goto out_of_memory;
1012 }
1013 set_page_private(ctx->pages[i], dma_addr);
1014 }
1015
1016 for (i = 0; i < AR_BUFFERS; i++)
1017 pages[i] = ctx->pages[i];
1018 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1019 pages[AR_BUFFERS + i] = ctx->pages[i];
1020 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1021 if (!ctx->buffer)
1022 goto out_of_memory;
1023
1024 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1025 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1026
1027 for (i = 0; i < AR_BUFFERS; i++) {
1028 d = &ctx->descriptors[i];
1029 d->req_count = cpu_to_le16(PAGE_SIZE);
1030 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1031 DESCRIPTOR_STATUS |
1032 DESCRIPTOR_BRANCH_ALWAYS);
1033 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1034 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1035 ar_next_buffer_index(i) * sizeof(struct descriptor));
1036 }
1037
1038 return 0;
1039
1040 out_of_memory:
1041 ar_context_release(ctx);
1042
1043 return -ENOMEM;
1044 }
1045
1046 static void ar_context_run(struct ar_context *ctx)
1047 {
1048 unsigned int i;
1049
1050 for (i = 0; i < AR_BUFFERS; i++)
1051 ar_context_link_page(ctx, i);
1052
1053 ctx->pointer = ctx->buffer;
1054
1055 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1056 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1057 }
1058
1059 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1060 {
1061 __le16 branch;
1062
1063 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1064
1065 /* figure out which descriptor the branch address goes in */
1066 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1067 return d;
1068 else
1069 return d + z - 1;
1070 }
1071
1072 static void context_tasklet(unsigned long data)
1073 {
1074 struct context *ctx = (struct context *) data;
1075 struct descriptor *d, *last;
1076 u32 address;
1077 int z;
1078 struct descriptor_buffer *desc;
1079
1080 desc = list_entry(ctx->buffer_list.next,
1081 struct descriptor_buffer, list);
1082 last = ctx->last;
1083 while (last->branch_address != 0) {
1084 struct descriptor_buffer *old_desc = desc;
1085 address = le32_to_cpu(last->branch_address);
1086 z = address & 0xf;
1087 address &= ~0xf;
1088 ctx->current_bus = address;
1089
1090 /* If the branch address points to a buffer outside of the
1091 * current buffer, advance to the next buffer. */
1092 if (address < desc->buffer_bus ||
1093 address >= desc->buffer_bus + desc->used)
1094 desc = list_entry(desc->list.next,
1095 struct descriptor_buffer, list);
1096 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1097 last = find_branch_descriptor(d, z);
1098
1099 if (!ctx->callback(ctx, d, last))
1100 break;
1101
1102 if (old_desc != desc) {
1103 /* If we've advanced to the next buffer, move the
1104 * previous buffer to the free list. */
1105 unsigned long flags;
1106 old_desc->used = 0;
1107 spin_lock_irqsave(&ctx->ohci->lock, flags);
1108 list_move_tail(&old_desc->list, &ctx->buffer_list);
1109 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1110 }
1111 ctx->last = last;
1112 }
1113 }
1114
1115 /*
1116 * Allocate a new buffer and add it to the list of free buffers for this
1117 * context. Must be called with ohci->lock held.
1118 */
1119 static int context_add_buffer(struct context *ctx)
1120 {
1121 struct descriptor_buffer *desc;
1122 dma_addr_t uninitialized_var(bus_addr);
1123 int offset;
1124
1125 /*
1126 * 16MB of descriptors should be far more than enough for any DMA
1127 * program. This will catch run-away userspace or DoS attacks.
1128 */
1129 if (ctx->total_allocation >= 16*1024*1024)
1130 return -ENOMEM;
1131
1132 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1133 &bus_addr, GFP_ATOMIC);
1134 if (!desc)
1135 return -ENOMEM;
1136
1137 offset = (void *)&desc->buffer - (void *)desc;
1138 desc->buffer_size = PAGE_SIZE - offset;
1139 desc->buffer_bus = bus_addr + offset;
1140 desc->used = 0;
1141
1142 list_add_tail(&desc->list, &ctx->buffer_list);
1143 ctx->total_allocation += PAGE_SIZE;
1144
1145 return 0;
1146 }
1147
1148 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1149 u32 regs, descriptor_callback_t callback)
1150 {
1151 ctx->ohci = ohci;
1152 ctx->regs = regs;
1153 ctx->total_allocation = 0;
1154
1155 INIT_LIST_HEAD(&ctx->buffer_list);
1156 if (context_add_buffer(ctx) < 0)
1157 return -ENOMEM;
1158
1159 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1160 struct descriptor_buffer, list);
1161
1162 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1163 ctx->callback = callback;
1164
1165 /*
1166 * We put a dummy descriptor in the buffer that has a NULL
1167 * branch address and looks like it's been sent. That way we
1168 * have a descriptor to append DMA programs to.
1169 */
1170 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1171 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1172 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1173 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1174 ctx->last = ctx->buffer_tail->buffer;
1175 ctx->prev = ctx->buffer_tail->buffer;
1176 ctx->prev_z = 1;
1177
1178 return 0;
1179 }
1180
1181 static void context_release(struct context *ctx)
1182 {
1183 struct fw_card *card = &ctx->ohci->card;
1184 struct descriptor_buffer *desc, *tmp;
1185
1186 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1187 dma_free_coherent(card->device, PAGE_SIZE, desc,
1188 desc->buffer_bus -
1189 ((void *)&desc->buffer - (void *)desc));
1190 }
1191
1192 /* Must be called with ohci->lock held */
1193 static struct descriptor *context_get_descriptors(struct context *ctx,
1194 int z, dma_addr_t *d_bus)
1195 {
1196 struct descriptor *d = NULL;
1197 struct descriptor_buffer *desc = ctx->buffer_tail;
1198
1199 if (z * sizeof(*d) > desc->buffer_size)
1200 return NULL;
1201
1202 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1203 /* No room for the descriptor in this buffer, so advance to the
1204 * next one. */
1205
1206 if (desc->list.next == &ctx->buffer_list) {
1207 /* If there is no free buffer next in the list,
1208 * allocate one. */
1209 if (context_add_buffer(ctx) < 0)
1210 return NULL;
1211 }
1212 desc = list_entry(desc->list.next,
1213 struct descriptor_buffer, list);
1214 ctx->buffer_tail = desc;
1215 }
1216
1217 d = desc->buffer + desc->used / sizeof(*d);
1218 memset(d, 0, z * sizeof(*d));
1219 *d_bus = desc->buffer_bus + desc->used;
1220
1221 return d;
1222 }
1223
1224 static void context_run(struct context *ctx, u32 extra)
1225 {
1226 struct fw_ohci *ohci = ctx->ohci;
1227
1228 reg_write(ohci, COMMAND_PTR(ctx->regs),
1229 le32_to_cpu(ctx->last->branch_address));
1230 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1231 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1232 ctx->running = true;
1233 flush_writes(ohci);
1234 }
1235
1236 static void context_append(struct context *ctx,
1237 struct descriptor *d, int z, int extra)
1238 {
1239 dma_addr_t d_bus;
1240 struct descriptor_buffer *desc = ctx->buffer_tail;
1241 struct descriptor *d_branch;
1242
1243 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1244
1245 desc->used += (z + extra) * sizeof(*d);
1246
1247 wmb(); /* finish init of new descriptors before branch_address update */
1248
1249 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1250 d_branch->branch_address = cpu_to_le32(d_bus | z);
1251
1252 /*
1253 * VT6306 incorrectly checks only the single descriptor at the
1254 * CommandPtr when the wake bit is written, so if it's a
1255 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1256 * the branch address in the first descriptor.
1257 *
1258 * Not doing this for transmit contexts since not sure how it interacts
1259 * with skip addresses.
1260 */
1261 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1262 d_branch != ctx->prev &&
1263 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1264 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1265 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1266 }
1267
1268 ctx->prev = d;
1269 ctx->prev_z = z;
1270 }
1271
1272 static void context_stop(struct context *ctx)
1273 {
1274 struct fw_ohci *ohci = ctx->ohci;
1275 u32 reg;
1276 int i;
1277
1278 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1279 ctx->running = false;
1280
1281 for (i = 0; i < 1000; i++) {
1282 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1283 if ((reg & CONTEXT_ACTIVE) == 0)
1284 return;
1285
1286 if (i)
1287 udelay(10);
1288 }
1289 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1290 }
1291
1292 struct driver_data {
1293 u8 inline_data[8];
1294 struct fw_packet *packet;
1295 };
1296
1297 /*
1298 * This function apppends a packet to the DMA queue for transmission.
1299 * Must always be called with the ochi->lock held to ensure proper
1300 * generation handling and locking around packet queue manipulation.
1301 */
1302 static int at_context_queue_packet(struct context *ctx,
1303 struct fw_packet *packet)
1304 {
1305 struct fw_ohci *ohci = ctx->ohci;
1306 dma_addr_t d_bus, uninitialized_var(payload_bus);
1307 struct driver_data *driver_data;
1308 struct descriptor *d, *last;
1309 __le32 *header;
1310 int z, tcode;
1311
1312 d = context_get_descriptors(ctx, 4, &d_bus);
1313 if (d == NULL) {
1314 packet->ack = RCODE_SEND_ERROR;
1315 return -1;
1316 }
1317
1318 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1319 d[0].res_count = cpu_to_le16(packet->timestamp);
1320
1321 /*
1322 * The DMA format for asynchronous link packets is different
1323 * from the IEEE1394 layout, so shift the fields around
1324 * accordingly.
1325 */
1326
1327 tcode = (packet->header[0] >> 4) & 0x0f;
1328 header = (__le32 *) &d[1];
1329 switch (tcode) {
1330 case TCODE_WRITE_QUADLET_REQUEST:
1331 case TCODE_WRITE_BLOCK_REQUEST:
1332 case TCODE_WRITE_RESPONSE:
1333 case TCODE_READ_QUADLET_REQUEST:
1334 case TCODE_READ_BLOCK_REQUEST:
1335 case TCODE_READ_QUADLET_RESPONSE:
1336 case TCODE_READ_BLOCK_RESPONSE:
1337 case TCODE_LOCK_REQUEST:
1338 case TCODE_LOCK_RESPONSE:
1339 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1340 (packet->speed << 16));
1341 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1342 (packet->header[0] & 0xffff0000));
1343 header[2] = cpu_to_le32(packet->header[2]);
1344
1345 if (TCODE_IS_BLOCK_PACKET(tcode))
1346 header[3] = cpu_to_le32(packet->header[3]);
1347 else
1348 header[3] = (__force __le32) packet->header[3];
1349
1350 d[0].req_count = cpu_to_le16(packet->header_length);
1351 break;
1352
1353 case TCODE_LINK_INTERNAL:
1354 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1355 (packet->speed << 16));
1356 header[1] = cpu_to_le32(packet->header[1]);
1357 header[2] = cpu_to_le32(packet->header[2]);
1358 d[0].req_count = cpu_to_le16(12);
1359
1360 if (is_ping_packet(&packet->header[1]))
1361 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1362 break;
1363
1364 case TCODE_STREAM_DATA:
1365 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1366 (packet->speed << 16));
1367 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1368 d[0].req_count = cpu_to_le16(8);
1369 break;
1370
1371 default:
1372 /* BUG(); */
1373 packet->ack = RCODE_SEND_ERROR;
1374 return -1;
1375 }
1376
1377 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1378 driver_data = (struct driver_data *) &d[3];
1379 driver_data->packet = packet;
1380 packet->driver_data = driver_data;
1381
1382 if (packet->payload_length > 0) {
1383 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1384 payload_bus = dma_map_single(ohci->card.device,
1385 packet->payload,
1386 packet->payload_length,
1387 DMA_TO_DEVICE);
1388 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1389 packet->ack = RCODE_SEND_ERROR;
1390 return -1;
1391 }
1392 packet->payload_bus = payload_bus;
1393 packet->payload_mapped = true;
1394 } else {
1395 memcpy(driver_data->inline_data, packet->payload,
1396 packet->payload_length);
1397 payload_bus = d_bus + 3 * sizeof(*d);
1398 }
1399
1400 d[2].req_count = cpu_to_le16(packet->payload_length);
1401 d[2].data_address = cpu_to_le32(payload_bus);
1402 last = &d[2];
1403 z = 3;
1404 } else {
1405 last = &d[0];
1406 z = 2;
1407 }
1408
1409 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1410 DESCRIPTOR_IRQ_ALWAYS |
1411 DESCRIPTOR_BRANCH_ALWAYS);
1412
1413 /* FIXME: Document how the locking works. */
1414 if (ohci->generation != packet->generation) {
1415 if (packet->payload_mapped)
1416 dma_unmap_single(ohci->card.device, payload_bus,
1417 packet->payload_length, DMA_TO_DEVICE);
1418 packet->ack = RCODE_GENERATION;
1419 return -1;
1420 }
1421
1422 context_append(ctx, d, z, 4 - z);
1423
1424 if (ctx->running)
1425 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1426 else
1427 context_run(ctx, 0);
1428
1429 return 0;
1430 }
1431
1432 static void at_context_flush(struct context *ctx)
1433 {
1434 tasklet_disable(&ctx->tasklet);
1435
1436 ctx->flushing = true;
1437 context_tasklet((unsigned long)ctx);
1438 ctx->flushing = false;
1439
1440 tasklet_enable(&ctx->tasklet);
1441 }
1442
1443 static int handle_at_packet(struct context *context,
1444 struct descriptor *d,
1445 struct descriptor *last)
1446 {
1447 struct driver_data *driver_data;
1448 struct fw_packet *packet;
1449 struct fw_ohci *ohci = context->ohci;
1450 int evt;
1451
1452 if (last->transfer_status == 0 && !context->flushing)
1453 /* This descriptor isn't done yet, stop iteration. */
1454 return 0;
1455
1456 driver_data = (struct driver_data *) &d[3];
1457 packet = driver_data->packet;
1458 if (packet == NULL)
1459 /* This packet was cancelled, just continue. */
1460 return 1;
1461
1462 if (packet->payload_mapped)
1463 dma_unmap_single(ohci->card.device, packet->payload_bus,
1464 packet->payload_length, DMA_TO_DEVICE);
1465
1466 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1467 packet->timestamp = le16_to_cpu(last->res_count);
1468
1469 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1470
1471 switch (evt) {
1472 case OHCI1394_evt_timeout:
1473 /* Async response transmit timed out. */
1474 packet->ack = RCODE_CANCELLED;
1475 break;
1476
1477 case OHCI1394_evt_flushed:
1478 /*
1479 * The packet was flushed should give same error as
1480 * when we try to use a stale generation count.
1481 */
1482 packet->ack = RCODE_GENERATION;
1483 break;
1484
1485 case OHCI1394_evt_missing_ack:
1486 if (context->flushing)
1487 packet->ack = RCODE_GENERATION;
1488 else {
1489 /*
1490 * Using a valid (current) generation count, but the
1491 * node is not on the bus or not sending acks.
1492 */
1493 packet->ack = RCODE_NO_ACK;
1494 }
1495 break;
1496
1497 case ACK_COMPLETE + 0x10:
1498 case ACK_PENDING + 0x10:
1499 case ACK_BUSY_X + 0x10:
1500 case ACK_BUSY_A + 0x10:
1501 case ACK_BUSY_B + 0x10:
1502 case ACK_DATA_ERROR + 0x10:
1503 case ACK_TYPE_ERROR + 0x10:
1504 packet->ack = evt - 0x10;
1505 break;
1506
1507 case OHCI1394_evt_no_status:
1508 if (context->flushing) {
1509 packet->ack = RCODE_GENERATION;
1510 break;
1511 }
1512 /* fall through */
1513
1514 default:
1515 packet->ack = RCODE_SEND_ERROR;
1516 break;
1517 }
1518
1519 packet->callback(packet, &ohci->card, packet->ack);
1520
1521 return 1;
1522 }
1523
1524 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1525 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1526 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1527 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1528 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1529
1530 static void handle_local_rom(struct fw_ohci *ohci,
1531 struct fw_packet *packet, u32 csr)
1532 {
1533 struct fw_packet response;
1534 int tcode, length, i;
1535
1536 tcode = HEADER_GET_TCODE(packet->header[0]);
1537 if (TCODE_IS_BLOCK_PACKET(tcode))
1538 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1539 else
1540 length = 4;
1541
1542 i = csr - CSR_CONFIG_ROM;
1543 if (i + length > CONFIG_ROM_SIZE) {
1544 fw_fill_response(&response, packet->header,
1545 RCODE_ADDRESS_ERROR, NULL, 0);
1546 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1547 fw_fill_response(&response, packet->header,
1548 RCODE_TYPE_ERROR, NULL, 0);
1549 } else {
1550 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1551 (void *) ohci->config_rom + i, length);
1552 }
1553
1554 fw_core_handle_response(&ohci->card, &response);
1555 }
1556
1557 static void handle_local_lock(struct fw_ohci *ohci,
1558 struct fw_packet *packet, u32 csr)
1559 {
1560 struct fw_packet response;
1561 int tcode, length, ext_tcode, sel, try;
1562 __be32 *payload, lock_old;
1563 u32 lock_arg, lock_data;
1564
1565 tcode = HEADER_GET_TCODE(packet->header[0]);
1566 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1567 payload = packet->payload;
1568 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1569
1570 if (tcode == TCODE_LOCK_REQUEST &&
1571 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1572 lock_arg = be32_to_cpu(payload[0]);
1573 lock_data = be32_to_cpu(payload[1]);
1574 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1575 lock_arg = 0;
1576 lock_data = 0;
1577 } else {
1578 fw_fill_response(&response, packet->header,
1579 RCODE_TYPE_ERROR, NULL, 0);
1580 goto out;
1581 }
1582
1583 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1584 reg_write(ohci, OHCI1394_CSRData, lock_data);
1585 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1586 reg_write(ohci, OHCI1394_CSRControl, sel);
1587
1588 for (try = 0; try < 20; try++)
1589 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1590 lock_old = cpu_to_be32(reg_read(ohci,
1591 OHCI1394_CSRData));
1592 fw_fill_response(&response, packet->header,
1593 RCODE_COMPLETE,
1594 &lock_old, sizeof(lock_old));
1595 goto out;
1596 }
1597
1598 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1599 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1600
1601 out:
1602 fw_core_handle_response(&ohci->card, &response);
1603 }
1604
1605 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1606 {
1607 u64 offset, csr;
1608
1609 if (ctx == &ctx->ohci->at_request_ctx) {
1610 packet->ack = ACK_PENDING;
1611 packet->callback(packet, &ctx->ohci->card, packet->ack);
1612 }
1613
1614 offset =
1615 ((unsigned long long)
1616 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1617 packet->header[2];
1618 csr = offset - CSR_REGISTER_BASE;
1619
1620 /* Handle config rom reads. */
1621 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1622 handle_local_rom(ctx->ohci, packet, csr);
1623 else switch (csr) {
1624 case CSR_BUS_MANAGER_ID:
1625 case CSR_BANDWIDTH_AVAILABLE:
1626 case CSR_CHANNELS_AVAILABLE_HI:
1627 case CSR_CHANNELS_AVAILABLE_LO:
1628 handle_local_lock(ctx->ohci, packet, csr);
1629 break;
1630 default:
1631 if (ctx == &ctx->ohci->at_request_ctx)
1632 fw_core_handle_request(&ctx->ohci->card, packet);
1633 else
1634 fw_core_handle_response(&ctx->ohci->card, packet);
1635 break;
1636 }
1637
1638 if (ctx == &ctx->ohci->at_response_ctx) {
1639 packet->ack = ACK_COMPLETE;
1640 packet->callback(packet, &ctx->ohci->card, packet->ack);
1641 }
1642 }
1643
1644 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1645 {
1646 unsigned long flags;
1647 int ret;
1648
1649 spin_lock_irqsave(&ctx->ohci->lock, flags);
1650
1651 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1652 ctx->ohci->generation == packet->generation) {
1653 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1654 handle_local_request(ctx, packet);
1655 return;
1656 }
1657
1658 ret = at_context_queue_packet(ctx, packet);
1659 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1660
1661 if (ret < 0)
1662 packet->callback(packet, &ctx->ohci->card, packet->ack);
1663
1664 }
1665
1666 static void detect_dead_context(struct fw_ohci *ohci,
1667 const char *name, unsigned int regs)
1668 {
1669 u32 ctl;
1670
1671 ctl = reg_read(ohci, CONTROL_SET(regs));
1672 if (ctl & CONTEXT_DEAD)
1673 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1674 name, evts[ctl & 0x1f]);
1675 }
1676
1677 static void handle_dead_contexts(struct fw_ohci *ohci)
1678 {
1679 unsigned int i;
1680 char name[8];
1681
1682 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1683 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1684 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1685 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1686 for (i = 0; i < 32; ++i) {
1687 if (!(ohci->it_context_support & (1 << i)))
1688 continue;
1689 sprintf(name, "IT%u", i);
1690 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1691 }
1692 for (i = 0; i < 32; ++i) {
1693 if (!(ohci->ir_context_support & (1 << i)))
1694 continue;
1695 sprintf(name, "IR%u", i);
1696 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1697 }
1698 /* TODO: maybe try to flush and restart the dead contexts */
1699 }
1700
1701 static u32 cycle_timer_ticks(u32 cycle_timer)
1702 {
1703 u32 ticks;
1704
1705 ticks = cycle_timer & 0xfff;
1706 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1707 ticks += (3072 * 8000) * (cycle_timer >> 25);
1708
1709 return ticks;
1710 }
1711
1712 /*
1713 * Some controllers exhibit one or more of the following bugs when updating the
1714 * iso cycle timer register:
1715 * - When the lowest six bits are wrapping around to zero, a read that happens
1716 * at the same time will return garbage in the lowest ten bits.
1717 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1718 * not incremented for about 60 ns.
1719 * - Occasionally, the entire register reads zero.
1720 *
1721 * To catch these, we read the register three times and ensure that the
1722 * difference between each two consecutive reads is approximately the same, i.e.
1723 * less than twice the other. Furthermore, any negative difference indicates an
1724 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1725 * execute, so we have enough precision to compute the ratio of the differences.)
1726 */
1727 static u32 get_cycle_time(struct fw_ohci *ohci)
1728 {
1729 u32 c0, c1, c2;
1730 u32 t0, t1, t2;
1731 s32 diff01, diff12;
1732 int i;
1733
1734 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1735
1736 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1737 i = 0;
1738 c1 = c2;
1739 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1740 do {
1741 c0 = c1;
1742 c1 = c2;
1743 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1744 t0 = cycle_timer_ticks(c0);
1745 t1 = cycle_timer_ticks(c1);
1746 t2 = cycle_timer_ticks(c2);
1747 diff01 = t1 - t0;
1748 diff12 = t2 - t1;
1749 } while ((diff01 <= 0 || diff12 <= 0 ||
1750 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1751 && i++ < 20);
1752 }
1753
1754 return c2;
1755 }
1756
1757 /*
1758 * This function has to be called at least every 64 seconds. The bus_time
1759 * field stores not only the upper 25 bits of the BUS_TIME register but also
1760 * the most significant bit of the cycle timer in bit 6 so that we can detect
1761 * changes in this bit.
1762 */
1763 static u32 update_bus_time(struct fw_ohci *ohci)
1764 {
1765 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1766
1767 if (unlikely(!ohci->bus_time_running)) {
1768 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1769 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1770 (cycle_time_seconds & 0x40);
1771 ohci->bus_time_running = true;
1772 }
1773
1774 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1775 ohci->bus_time += 0x40;
1776
1777 return ohci->bus_time | cycle_time_seconds;
1778 }
1779
1780 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1781 {
1782 int reg;
1783
1784 mutex_lock(&ohci->phy_reg_mutex);
1785 reg = write_phy_reg(ohci, 7, port_index);
1786 if (reg >= 0)
1787 reg = read_phy_reg(ohci, 8);
1788 mutex_unlock(&ohci->phy_reg_mutex);
1789 if (reg < 0)
1790 return reg;
1791
1792 switch (reg & 0x0f) {
1793 case 0x06:
1794 return 2; /* is child node (connected to parent node) */
1795 case 0x0e:
1796 return 3; /* is parent node (connected to child node) */
1797 }
1798 return 1; /* not connected */
1799 }
1800
1801 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1802 int self_id_count)
1803 {
1804 int i;
1805 u32 entry;
1806
1807 for (i = 0; i < self_id_count; i++) {
1808 entry = ohci->self_id_buffer[i];
1809 if ((self_id & 0xff000000) == (entry & 0xff000000))
1810 return -1;
1811 if ((self_id & 0xff000000) < (entry & 0xff000000))
1812 return i;
1813 }
1814 return i;
1815 }
1816
1817 static int initiated_reset(struct fw_ohci *ohci)
1818 {
1819 int reg;
1820 int ret = 0;
1821
1822 mutex_lock(&ohci->phy_reg_mutex);
1823 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1824 if (reg >= 0) {
1825 reg = read_phy_reg(ohci, 8);
1826 reg |= 0x40;
1827 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1828 if (reg >= 0) {
1829 reg = read_phy_reg(ohci, 12); /* read register 12 */
1830 if (reg >= 0) {
1831 if ((reg & 0x08) == 0x08) {
1832 /* bit 3 indicates "initiated reset" */
1833 ret = 0x2;
1834 }
1835 }
1836 }
1837 }
1838 mutex_unlock(&ohci->phy_reg_mutex);
1839 return ret;
1840 }
1841
1842 /*
1843 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1844 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1845 * Construct the selfID from phy register contents.
1846 */
1847 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1848 {
1849 int reg, i, pos, status;
1850 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1851 u32 self_id = 0x8040c800;
1852
1853 reg = reg_read(ohci, OHCI1394_NodeID);
1854 if (!(reg & OHCI1394_NodeID_idValid)) {
1855 ohci_notice(ohci,
1856 "node ID not valid, new bus reset in progress\n");
1857 return -EBUSY;
1858 }
1859 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1860
1861 reg = ohci_read_phy_reg(&ohci->card, 4);
1862 if (reg < 0)
1863 return reg;
1864 self_id |= ((reg & 0x07) << 8); /* power class */
1865
1866 reg = ohci_read_phy_reg(&ohci->card, 1);
1867 if (reg < 0)
1868 return reg;
1869 self_id |= ((reg & 0x3f) << 16); /* gap count */
1870
1871 for (i = 0; i < 3; i++) {
1872 status = get_status_for_port(ohci, i);
1873 if (status < 0)
1874 return status;
1875 self_id |= ((status & 0x3) << (6 - (i * 2)));
1876 }
1877
1878 self_id |= initiated_reset(ohci);
1879
1880 pos = get_self_id_pos(ohci, self_id, self_id_count);
1881 if (pos >= 0) {
1882 memmove(&(ohci->self_id_buffer[pos+1]),
1883 &(ohci->self_id_buffer[pos]),
1884 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1885 ohci->self_id_buffer[pos] = self_id;
1886 self_id_count++;
1887 }
1888 return self_id_count;
1889 }
1890
1891 static void bus_reset_work(struct work_struct *work)
1892 {
1893 struct fw_ohci *ohci =
1894 container_of(work, struct fw_ohci, bus_reset_work);
1895 int self_id_count, generation, new_generation, i, j;
1896 u32 reg;
1897 void *free_rom = NULL;
1898 dma_addr_t free_rom_bus = 0;
1899 bool is_new_root;
1900
1901 reg = reg_read(ohci, OHCI1394_NodeID);
1902 if (!(reg & OHCI1394_NodeID_idValid)) {
1903 ohci_notice(ohci,
1904 "node ID not valid, new bus reset in progress\n");
1905 return;
1906 }
1907 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1908 ohci_notice(ohci, "malconfigured bus\n");
1909 return;
1910 }
1911 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1912 OHCI1394_NodeID_nodeNumber);
1913
1914 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1915 if (!(ohci->is_root && is_new_root))
1916 reg_write(ohci, OHCI1394_LinkControlSet,
1917 OHCI1394_LinkControl_cycleMaster);
1918 ohci->is_root = is_new_root;
1919
1920 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1921 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1922 ohci_notice(ohci, "self ID receive error\n");
1923 return;
1924 }
1925 /*
1926 * The count in the SelfIDCount register is the number of
1927 * bytes in the self ID receive buffer. Since we also receive
1928 * the inverted quadlets and a header quadlet, we shift one
1929 * bit extra to get the actual number of self IDs.
1930 */
1931 self_id_count = (reg >> 3) & 0xff;
1932
1933 if (self_id_count > 252) {
1934 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1935 return;
1936 }
1937
1938 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1939 rmb();
1940
1941 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1942 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1943 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1944
1945 if (id != ~id2) {
1946 /*
1947 * If the invalid data looks like a cycle start packet,
1948 * it's likely to be the result of the cycle master
1949 * having a wrong gap count. In this case, the self IDs
1950 * so far are valid and should be processed so that the
1951 * bus manager can then correct the gap count.
1952 */
1953 if (id == 0xffff008f) {
1954 ohci_notice(ohci, "ignoring spurious self IDs\n");
1955 self_id_count = j;
1956 break;
1957 }
1958
1959 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1960 j, self_id_count, id, id2);
1961 return;
1962 }
1963 ohci->self_id_buffer[j] = id;
1964 }
1965
1966 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1967 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1968 if (self_id_count < 0) {
1969 ohci_notice(ohci,
1970 "could not construct local self ID\n");
1971 return;
1972 }
1973 }
1974
1975 if (self_id_count == 0) {
1976 ohci_notice(ohci, "no self IDs\n");
1977 return;
1978 }
1979 rmb();
1980
1981 /*
1982 * Check the consistency of the self IDs we just read. The
1983 * problem we face is that a new bus reset can start while we
1984 * read out the self IDs from the DMA buffer. If this happens,
1985 * the DMA buffer will be overwritten with new self IDs and we
1986 * will read out inconsistent data. The OHCI specification
1987 * (section 11.2) recommends a technique similar to
1988 * linux/seqlock.h, where we remember the generation of the
1989 * self IDs in the buffer before reading them out and compare
1990 * it to the current generation after reading them out. If
1991 * the two generations match we know we have a consistent set
1992 * of self IDs.
1993 */
1994
1995 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1996 if (new_generation != generation) {
1997 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1998 return;
1999 }
2000
2001 /* FIXME: Document how the locking works. */
2002 spin_lock_irq(&ohci->lock);
2003
2004 ohci->generation = -1; /* prevent AT packet queueing */
2005 context_stop(&ohci->at_request_ctx);
2006 context_stop(&ohci->at_response_ctx);
2007
2008 spin_unlock_irq(&ohci->lock);
2009
2010 /*
2011 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2012 * packets in the AT queues and software needs to drain them.
2013 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2014 */
2015 at_context_flush(&ohci->at_request_ctx);
2016 at_context_flush(&ohci->at_response_ctx);
2017
2018 spin_lock_irq(&ohci->lock);
2019
2020 ohci->generation = generation;
2021 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2022
2023 if (ohci->quirks & QUIRK_RESET_PACKET)
2024 ohci->request_generation = generation;
2025
2026 /*
2027 * This next bit is unrelated to the AT context stuff but we
2028 * have to do it under the spinlock also. If a new config rom
2029 * was set up before this reset, the old one is now no longer
2030 * in use and we can free it. Update the config rom pointers
2031 * to point to the current config rom and clear the
2032 * next_config_rom pointer so a new update can take place.
2033 */
2034
2035 if (ohci->next_config_rom != NULL) {
2036 if (ohci->next_config_rom != ohci->config_rom) {
2037 free_rom = ohci->config_rom;
2038 free_rom_bus = ohci->config_rom_bus;
2039 }
2040 ohci->config_rom = ohci->next_config_rom;
2041 ohci->config_rom_bus = ohci->next_config_rom_bus;
2042 ohci->next_config_rom = NULL;
2043
2044 /*
2045 * Restore config_rom image and manually update
2046 * config_rom registers. Writing the header quadlet
2047 * will indicate that the config rom is ready, so we
2048 * do that last.
2049 */
2050 reg_write(ohci, OHCI1394_BusOptions,
2051 be32_to_cpu(ohci->config_rom[2]));
2052 ohci->config_rom[0] = ohci->next_header;
2053 reg_write(ohci, OHCI1394_ConfigROMhdr,
2054 be32_to_cpu(ohci->next_header));
2055 }
2056
2057 if (param_remote_dma) {
2058 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2059 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2060 }
2061
2062 spin_unlock_irq(&ohci->lock);
2063
2064 if (free_rom)
2065 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2066 free_rom, free_rom_bus);
2067
2068 log_selfids(ohci, generation, self_id_count);
2069
2070 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2071 self_id_count, ohci->self_id_buffer,
2072 ohci->csr_state_setclear_abdicate);
2073 ohci->csr_state_setclear_abdicate = false;
2074 }
2075
2076 static irqreturn_t irq_handler(int irq, void *data)
2077 {
2078 struct fw_ohci *ohci = data;
2079 u32 event, iso_event;
2080 int i;
2081
2082 event = reg_read(ohci, OHCI1394_IntEventClear);
2083
2084 if (!event || !~event)
2085 return IRQ_NONE;
2086
2087 /*
2088 * busReset and postedWriteErr must not be cleared yet
2089 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2090 */
2091 reg_write(ohci, OHCI1394_IntEventClear,
2092 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2093 log_irqs(ohci, event);
2094
2095 if (event & OHCI1394_selfIDComplete)
2096 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2097
2098 if (event & OHCI1394_RQPkt)
2099 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2100
2101 if (event & OHCI1394_RSPkt)
2102 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2103
2104 if (event & OHCI1394_reqTxComplete)
2105 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2106
2107 if (event & OHCI1394_respTxComplete)
2108 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2109
2110 if (event & OHCI1394_isochRx) {
2111 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2112 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2113
2114 while (iso_event) {
2115 i = ffs(iso_event) - 1;
2116 tasklet_schedule(
2117 &ohci->ir_context_list[i].context.tasklet);
2118 iso_event &= ~(1 << i);
2119 }
2120 }
2121
2122 if (event & OHCI1394_isochTx) {
2123 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2124 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2125
2126 while (iso_event) {
2127 i = ffs(iso_event) - 1;
2128 tasklet_schedule(
2129 &ohci->it_context_list[i].context.tasklet);
2130 iso_event &= ~(1 << i);
2131 }
2132 }
2133
2134 if (unlikely(event & OHCI1394_regAccessFail))
2135 ohci_err(ohci, "register access failure\n");
2136
2137 if (unlikely(event & OHCI1394_postedWriteErr)) {
2138 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2139 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2140 reg_write(ohci, OHCI1394_IntEventClear,
2141 OHCI1394_postedWriteErr);
2142 if (printk_ratelimit())
2143 ohci_err(ohci, "PCI posted write error\n");
2144 }
2145
2146 if (unlikely(event & OHCI1394_cycleTooLong)) {
2147 if (printk_ratelimit())
2148 ohci_notice(ohci, "isochronous cycle too long\n");
2149 reg_write(ohci, OHCI1394_LinkControlSet,
2150 OHCI1394_LinkControl_cycleMaster);
2151 }
2152
2153 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2154 /*
2155 * We need to clear this event bit in order to make
2156 * cycleMatch isochronous I/O work. In theory we should
2157 * stop active cycleMatch iso contexts now and restart
2158 * them at least two cycles later. (FIXME?)
2159 */
2160 if (printk_ratelimit())
2161 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2162 }
2163
2164 if (unlikely(event & OHCI1394_unrecoverableError))
2165 handle_dead_contexts(ohci);
2166
2167 if (event & OHCI1394_cycle64Seconds) {
2168 spin_lock(&ohci->lock);
2169 update_bus_time(ohci);
2170 spin_unlock(&ohci->lock);
2171 } else
2172 flush_writes(ohci);
2173
2174 return IRQ_HANDLED;
2175 }
2176
2177 static int software_reset(struct fw_ohci *ohci)
2178 {
2179 u32 val;
2180 int i;
2181
2182 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2183 for (i = 0; i < 500; i++) {
2184 val = reg_read(ohci, OHCI1394_HCControlSet);
2185 if (!~val)
2186 return -ENODEV; /* Card was ejected. */
2187
2188 if (!(val & OHCI1394_HCControl_softReset))
2189 return 0;
2190
2191 msleep(1);
2192 }
2193
2194 return -EBUSY;
2195 }
2196
2197 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2198 {
2199 size_t size = length * 4;
2200
2201 memcpy(dest, src, size);
2202 if (size < CONFIG_ROM_SIZE)
2203 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2204 }
2205
2206 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2207 {
2208 bool enable_1394a;
2209 int ret, clear, set, offset;
2210
2211 /* Check if the driver should configure link and PHY. */
2212 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2213 OHCI1394_HCControl_programPhyEnable))
2214 return 0;
2215
2216 /* Paranoia: check whether the PHY supports 1394a, too. */
2217 enable_1394a = false;
2218 ret = read_phy_reg(ohci, 2);
2219 if (ret < 0)
2220 return ret;
2221 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2222 ret = read_paged_phy_reg(ohci, 1, 8);
2223 if (ret < 0)
2224 return ret;
2225 if (ret >= 1)
2226 enable_1394a = true;
2227 }
2228
2229 if (ohci->quirks & QUIRK_NO_1394A)
2230 enable_1394a = false;
2231
2232 /* Configure PHY and link consistently. */
2233 if (enable_1394a) {
2234 clear = 0;
2235 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2236 } else {
2237 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2238 set = 0;
2239 }
2240 ret = update_phy_reg(ohci, 5, clear, set);
2241 if (ret < 0)
2242 return ret;
2243
2244 if (enable_1394a)
2245 offset = OHCI1394_HCControlSet;
2246 else
2247 offset = OHCI1394_HCControlClear;
2248 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2249
2250 /* Clean up: configuration has been taken care of. */
2251 reg_write(ohci, OHCI1394_HCControlClear,
2252 OHCI1394_HCControl_programPhyEnable);
2253
2254 return 0;
2255 }
2256
2257 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2258 {
2259 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2260 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2261 int reg, i;
2262
2263 reg = read_phy_reg(ohci, 2);
2264 if (reg < 0)
2265 return reg;
2266 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2267 return 0;
2268
2269 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2270 reg = read_paged_phy_reg(ohci, 1, i + 10);
2271 if (reg < 0)
2272 return reg;
2273 if (reg != id[i])
2274 return 0;
2275 }
2276 return 1;
2277 }
2278
2279 static int ohci_enable(struct fw_card *card,
2280 const __be32 *config_rom, size_t length)
2281 {
2282 struct fw_ohci *ohci = fw_ohci(card);
2283 u32 lps, version, irqs;
2284 int i, ret;
2285
2286 if (software_reset(ohci)) {
2287 ohci_err(ohci, "failed to reset ohci card\n");
2288 return -EBUSY;
2289 }
2290
2291 /*
2292 * Now enable LPS, which we need in order to start accessing
2293 * most of the registers. In fact, on some cards (ALI M5251),
2294 * accessing registers in the SClk domain without LPS enabled
2295 * will lock up the machine. Wait 50msec to make sure we have
2296 * full link enabled. However, with some cards (well, at least
2297 * a JMicron PCIe card), we have to try again sometimes.
2298 *
2299 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2300 * cannot actually use the phy at that time. These need tens of
2301 * millisecods pause between LPS write and first phy access too.
2302 */
2303
2304 reg_write(ohci, OHCI1394_HCControlSet,
2305 OHCI1394_HCControl_LPS |
2306 OHCI1394_HCControl_postedWriteEnable);
2307 flush_writes(ohci);
2308
2309 for (lps = 0, i = 0; !lps && i < 3; i++) {
2310 msleep(50);
2311 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2312 OHCI1394_HCControl_LPS;
2313 }
2314
2315 if (!lps) {
2316 ohci_err(ohci, "failed to set Link Power Status\n");
2317 return -EIO;
2318 }
2319
2320 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2321 ret = probe_tsb41ba3d(ohci);
2322 if (ret < 0)
2323 return ret;
2324 if (ret)
2325 ohci_notice(ohci, "local TSB41BA3D phy\n");
2326 else
2327 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2328 }
2329
2330 reg_write(ohci, OHCI1394_HCControlClear,
2331 OHCI1394_HCControl_noByteSwapData);
2332
2333 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2334 reg_write(ohci, OHCI1394_LinkControlSet,
2335 OHCI1394_LinkControl_cycleTimerEnable |
2336 OHCI1394_LinkControl_cycleMaster);
2337
2338 reg_write(ohci, OHCI1394_ATRetries,
2339 OHCI1394_MAX_AT_REQ_RETRIES |
2340 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2341 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2342 (200 << 16));
2343
2344 ohci->bus_time_running = false;
2345
2346 for (i = 0; i < 32; i++)
2347 if (ohci->ir_context_support & (1 << i))
2348 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2349 IR_CONTEXT_MULTI_CHANNEL_MODE);
2350
2351 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2352 if (version >= OHCI_VERSION_1_1) {
2353 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2354 0xfffffffe);
2355 card->broadcast_channel_auto_allocated = true;
2356 }
2357
2358 /* Get implemented bits of the priority arbitration request counter. */
2359 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2360 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2361 reg_write(ohci, OHCI1394_FairnessControl, 0);
2362 card->priority_budget_implemented = ohci->pri_req_max != 0;
2363
2364 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2365 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2366 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2367
2368 ret = configure_1394a_enhancements(ohci);
2369 if (ret < 0)
2370 return ret;
2371
2372 /* Activate link_on bit and contender bit in our self ID packets.*/
2373 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2374 if (ret < 0)
2375 return ret;
2376
2377 /*
2378 * When the link is not yet enabled, the atomic config rom
2379 * update mechanism described below in ohci_set_config_rom()
2380 * is not active. We have to update ConfigRomHeader and
2381 * BusOptions manually, and the write to ConfigROMmap takes
2382 * effect immediately. We tie this to the enabling of the
2383 * link, so we have a valid config rom before enabling - the
2384 * OHCI requires that ConfigROMhdr and BusOptions have valid
2385 * values before enabling.
2386 *
2387 * However, when the ConfigROMmap is written, some controllers
2388 * always read back quadlets 0 and 2 from the config rom to
2389 * the ConfigRomHeader and BusOptions registers on bus reset.
2390 * They shouldn't do that in this initial case where the link
2391 * isn't enabled. This means we have to use the same
2392 * workaround here, setting the bus header to 0 and then write
2393 * the right values in the bus reset tasklet.
2394 */
2395
2396 if (config_rom) {
2397 ohci->next_config_rom =
2398 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2399 &ohci->next_config_rom_bus,
2400 GFP_KERNEL);
2401 if (ohci->next_config_rom == NULL)
2402 return -ENOMEM;
2403
2404 copy_config_rom(ohci->next_config_rom, config_rom, length);
2405 } else {
2406 /*
2407 * In the suspend case, config_rom is NULL, which
2408 * means that we just reuse the old config rom.
2409 */
2410 ohci->next_config_rom = ohci->config_rom;
2411 ohci->next_config_rom_bus = ohci->config_rom_bus;
2412 }
2413
2414 ohci->next_header = ohci->next_config_rom[0];
2415 ohci->next_config_rom[0] = 0;
2416 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2417 reg_write(ohci, OHCI1394_BusOptions,
2418 be32_to_cpu(ohci->next_config_rom[2]));
2419 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2420
2421 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2422
2423 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2424 OHCI1394_RQPkt | OHCI1394_RSPkt |
2425 OHCI1394_isochTx | OHCI1394_isochRx |
2426 OHCI1394_postedWriteErr |
2427 OHCI1394_selfIDComplete |
2428 OHCI1394_regAccessFail |
2429 OHCI1394_cycleInconsistent |
2430 OHCI1394_unrecoverableError |
2431 OHCI1394_cycleTooLong |
2432 OHCI1394_masterIntEnable;
2433 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2434 irqs |= OHCI1394_busReset;
2435 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2436
2437 reg_write(ohci, OHCI1394_HCControlSet,
2438 OHCI1394_HCControl_linkEnable |
2439 OHCI1394_HCControl_BIBimageValid);
2440
2441 reg_write(ohci, OHCI1394_LinkControlSet,
2442 OHCI1394_LinkControl_rcvSelfID |
2443 OHCI1394_LinkControl_rcvPhyPkt);
2444
2445 ar_context_run(&ohci->ar_request_ctx);
2446 ar_context_run(&ohci->ar_response_ctx);
2447
2448 flush_writes(ohci);
2449
2450 /* We are ready to go, reset bus to finish initialization. */
2451 fw_schedule_bus_reset(&ohci->card, false, true);
2452
2453 return 0;
2454 }
2455
2456 static int ohci_set_config_rom(struct fw_card *card,
2457 const __be32 *config_rom, size_t length)
2458 {
2459 struct fw_ohci *ohci;
2460 __be32 *next_config_rom;
2461 dma_addr_t uninitialized_var(next_config_rom_bus);
2462
2463 ohci = fw_ohci(card);
2464
2465 /*
2466 * When the OHCI controller is enabled, the config rom update
2467 * mechanism is a bit tricky, but easy enough to use. See
2468 * section 5.5.6 in the OHCI specification.
2469 *
2470 * The OHCI controller caches the new config rom address in a
2471 * shadow register (ConfigROMmapNext) and needs a bus reset
2472 * for the changes to take place. When the bus reset is
2473 * detected, the controller loads the new values for the
2474 * ConfigRomHeader and BusOptions registers from the specified
2475 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2476 * shadow register. All automatically and atomically.
2477 *
2478 * Now, there's a twist to this story. The automatic load of
2479 * ConfigRomHeader and BusOptions doesn't honor the
2480 * noByteSwapData bit, so with a be32 config rom, the
2481 * controller will load be32 values in to these registers
2482 * during the atomic update, even on litte endian
2483 * architectures. The workaround we use is to put a 0 in the
2484 * header quadlet; 0 is endian agnostic and means that the
2485 * config rom isn't ready yet. In the bus reset tasklet we
2486 * then set up the real values for the two registers.
2487 *
2488 * We use ohci->lock to avoid racing with the code that sets
2489 * ohci->next_config_rom to NULL (see bus_reset_work).
2490 */
2491
2492 next_config_rom =
2493 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2494 &next_config_rom_bus, GFP_KERNEL);
2495 if (next_config_rom == NULL)
2496 return -ENOMEM;
2497
2498 spin_lock_irq(&ohci->lock);
2499
2500 /*
2501 * If there is not an already pending config_rom update,
2502 * push our new allocation into the ohci->next_config_rom
2503 * and then mark the local variable as null so that we
2504 * won't deallocate the new buffer.
2505 *
2506 * OTOH, if there is a pending config_rom update, just
2507 * use that buffer with the new config_rom data, and
2508 * let this routine free the unused DMA allocation.
2509 */
2510
2511 if (ohci->next_config_rom == NULL) {
2512 ohci->next_config_rom = next_config_rom;
2513 ohci->next_config_rom_bus = next_config_rom_bus;
2514 next_config_rom = NULL;
2515 }
2516
2517 copy_config_rom(ohci->next_config_rom, config_rom, length);
2518
2519 ohci->next_header = config_rom[0];
2520 ohci->next_config_rom[0] = 0;
2521
2522 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2523
2524 spin_unlock_irq(&ohci->lock);
2525
2526 /* If we didn't use the DMA allocation, delete it. */
2527 if (next_config_rom != NULL)
2528 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2529 next_config_rom, next_config_rom_bus);
2530
2531 /*
2532 * Now initiate a bus reset to have the changes take
2533 * effect. We clean up the old config rom memory and DMA
2534 * mappings in the bus reset tasklet, since the OHCI
2535 * controller could need to access it before the bus reset
2536 * takes effect.
2537 */
2538
2539 fw_schedule_bus_reset(&ohci->card, true, true);
2540
2541 return 0;
2542 }
2543
2544 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2545 {
2546 struct fw_ohci *ohci = fw_ohci(card);
2547
2548 at_context_transmit(&ohci->at_request_ctx, packet);
2549 }
2550
2551 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2552 {
2553 struct fw_ohci *ohci = fw_ohci(card);
2554
2555 at_context_transmit(&ohci->at_response_ctx, packet);
2556 }
2557
2558 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2559 {
2560 struct fw_ohci *ohci = fw_ohci(card);
2561 struct context *ctx = &ohci->at_request_ctx;
2562 struct driver_data *driver_data = packet->driver_data;
2563 int ret = -ENOENT;
2564
2565 tasklet_disable(&ctx->tasklet);
2566
2567 if (packet->ack != 0)
2568 goto out;
2569
2570 if (packet->payload_mapped)
2571 dma_unmap_single(ohci->card.device, packet->payload_bus,
2572 packet->payload_length, DMA_TO_DEVICE);
2573
2574 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2575 driver_data->packet = NULL;
2576 packet->ack = RCODE_CANCELLED;
2577 packet->callback(packet, &ohci->card, packet->ack);
2578 ret = 0;
2579 out:
2580 tasklet_enable(&ctx->tasklet);
2581
2582 return ret;
2583 }
2584
2585 static int ohci_enable_phys_dma(struct fw_card *card,
2586 int node_id, int generation)
2587 {
2588 struct fw_ohci *ohci = fw_ohci(card);
2589 unsigned long flags;
2590 int n, ret = 0;
2591
2592 if (param_remote_dma)
2593 return 0;
2594
2595 /*
2596 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2597 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2598 */
2599
2600 spin_lock_irqsave(&ohci->lock, flags);
2601
2602 if (ohci->generation != generation) {
2603 ret = -ESTALE;
2604 goto out;
2605 }
2606
2607 /*
2608 * Note, if the node ID contains a non-local bus ID, physical DMA is
2609 * enabled for _all_ nodes on remote buses.
2610 */
2611
2612 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2613 if (n < 32)
2614 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2615 else
2616 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2617
2618 flush_writes(ohci);
2619 out:
2620 spin_unlock_irqrestore(&ohci->lock, flags);
2621
2622 return ret;
2623 }
2624
2625 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2626 {
2627 struct fw_ohci *ohci = fw_ohci(card);
2628 unsigned long flags;
2629 u32 value;
2630
2631 switch (csr_offset) {
2632 case CSR_STATE_CLEAR:
2633 case CSR_STATE_SET:
2634 if (ohci->is_root &&
2635 (reg_read(ohci, OHCI1394_LinkControlSet) &
2636 OHCI1394_LinkControl_cycleMaster))
2637 value = CSR_STATE_BIT_CMSTR;
2638 else
2639 value = 0;
2640 if (ohci->csr_state_setclear_abdicate)
2641 value |= CSR_STATE_BIT_ABDICATE;
2642
2643 return value;
2644
2645 case CSR_NODE_IDS:
2646 return reg_read(ohci, OHCI1394_NodeID) << 16;
2647
2648 case CSR_CYCLE_TIME:
2649 return get_cycle_time(ohci);
2650
2651 case CSR_BUS_TIME:
2652 /*
2653 * We might be called just after the cycle timer has wrapped
2654 * around but just before the cycle64Seconds handler, so we
2655 * better check here, too, if the bus time needs to be updated.
2656 */
2657 spin_lock_irqsave(&ohci->lock, flags);
2658 value = update_bus_time(ohci);
2659 spin_unlock_irqrestore(&ohci->lock, flags);
2660 return value;
2661
2662 case CSR_BUSY_TIMEOUT:
2663 value = reg_read(ohci, OHCI1394_ATRetries);
2664 return (value >> 4) & 0x0ffff00f;
2665
2666 case CSR_PRIORITY_BUDGET:
2667 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2668 (ohci->pri_req_max << 8);
2669
2670 default:
2671 WARN_ON(1);
2672 return 0;
2673 }
2674 }
2675
2676 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2677 {
2678 struct fw_ohci *ohci = fw_ohci(card);
2679 unsigned long flags;
2680
2681 switch (csr_offset) {
2682 case CSR_STATE_CLEAR:
2683 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2684 reg_write(ohci, OHCI1394_LinkControlClear,
2685 OHCI1394_LinkControl_cycleMaster);
2686 flush_writes(ohci);
2687 }
2688 if (value & CSR_STATE_BIT_ABDICATE)
2689 ohci->csr_state_setclear_abdicate = false;
2690 break;
2691
2692 case CSR_STATE_SET:
2693 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2694 reg_write(ohci, OHCI1394_LinkControlSet,
2695 OHCI1394_LinkControl_cycleMaster);
2696 flush_writes(ohci);
2697 }
2698 if (value & CSR_STATE_BIT_ABDICATE)
2699 ohci->csr_state_setclear_abdicate = true;
2700 break;
2701
2702 case CSR_NODE_IDS:
2703 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2704 flush_writes(ohci);
2705 break;
2706
2707 case CSR_CYCLE_TIME:
2708 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2709 reg_write(ohci, OHCI1394_IntEventSet,
2710 OHCI1394_cycleInconsistent);
2711 flush_writes(ohci);
2712 break;
2713
2714 case CSR_BUS_TIME:
2715 spin_lock_irqsave(&ohci->lock, flags);
2716 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2717 (value & ~0x7f);
2718 spin_unlock_irqrestore(&ohci->lock, flags);
2719 break;
2720
2721 case CSR_BUSY_TIMEOUT:
2722 value = (value & 0xf) | ((value & 0xf) << 4) |
2723 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2724 reg_write(ohci, OHCI1394_ATRetries, value);
2725 flush_writes(ohci);
2726 break;
2727
2728 case CSR_PRIORITY_BUDGET:
2729 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2730 flush_writes(ohci);
2731 break;
2732
2733 default:
2734 WARN_ON(1);
2735 break;
2736 }
2737 }
2738
2739 static void flush_iso_completions(struct iso_context *ctx)
2740 {
2741 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2742 ctx->header_length, ctx->header,
2743 ctx->base.callback_data);
2744 ctx->header_length = 0;
2745 }
2746
2747 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2748 {
2749 u32 *ctx_hdr;
2750
2751 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2752 if (ctx->base.drop_overflow_headers)
2753 return;
2754 flush_iso_completions(ctx);
2755 }
2756
2757 ctx_hdr = ctx->header + ctx->header_length;
2758 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2759
2760 /*
2761 * The two iso header quadlets are byteswapped to little
2762 * endian by the controller, but we want to present them
2763 * as big endian for consistency with the bus endianness.
2764 */
2765 if (ctx->base.header_size > 0)
2766 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2767 if (ctx->base.header_size > 4)
2768 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2769 if (ctx->base.header_size > 8)
2770 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2771 ctx->header_length += ctx->base.header_size;
2772 }
2773
2774 static int handle_ir_packet_per_buffer(struct context *context,
2775 struct descriptor *d,
2776 struct descriptor *last)
2777 {
2778 struct iso_context *ctx =
2779 container_of(context, struct iso_context, context);
2780 struct descriptor *pd;
2781 u32 buffer_dma;
2782
2783 for (pd = d; pd <= last; pd++)
2784 if (pd->transfer_status)
2785 break;
2786 if (pd > last)
2787 /* Descriptor(s) not done yet, stop iteration */
2788 return 0;
2789
2790 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2791 d++;
2792 buffer_dma = le32_to_cpu(d->data_address);
2793 dma_sync_single_range_for_cpu(context->ohci->card.device,
2794 buffer_dma & PAGE_MASK,
2795 buffer_dma & ~PAGE_MASK,
2796 le16_to_cpu(d->req_count),
2797 DMA_FROM_DEVICE);
2798 }
2799
2800 copy_iso_headers(ctx, (u32 *) (last + 1));
2801
2802 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2803 flush_iso_completions(ctx);
2804
2805 return 1;
2806 }
2807
2808 /* d == last because each descriptor block is only a single descriptor. */
2809 static int handle_ir_buffer_fill(struct context *context,
2810 struct descriptor *d,
2811 struct descriptor *last)
2812 {
2813 struct iso_context *ctx =
2814 container_of(context, struct iso_context, context);
2815 unsigned int req_count, res_count, completed;
2816 u32 buffer_dma;
2817
2818 req_count = le16_to_cpu(last->req_count);
2819 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2820 completed = req_count - res_count;
2821 buffer_dma = le32_to_cpu(last->data_address);
2822
2823 if (completed > 0) {
2824 ctx->mc_buffer_bus = buffer_dma;
2825 ctx->mc_completed = completed;
2826 }
2827
2828 if (res_count != 0)
2829 /* Descriptor(s) not done yet, stop iteration */
2830 return 0;
2831
2832 dma_sync_single_range_for_cpu(context->ohci->card.device,
2833 buffer_dma & PAGE_MASK,
2834 buffer_dma & ~PAGE_MASK,
2835 completed, DMA_FROM_DEVICE);
2836
2837 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2838 ctx->base.callback.mc(&ctx->base,
2839 buffer_dma + completed,
2840 ctx->base.callback_data);
2841 ctx->mc_completed = 0;
2842 }
2843
2844 return 1;
2845 }
2846
2847 static void flush_ir_buffer_fill(struct iso_context *ctx)
2848 {
2849 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2850 ctx->mc_buffer_bus & PAGE_MASK,
2851 ctx->mc_buffer_bus & ~PAGE_MASK,
2852 ctx->mc_completed, DMA_FROM_DEVICE);
2853
2854 ctx->base.callback.mc(&ctx->base,
2855 ctx->mc_buffer_bus + ctx->mc_completed,
2856 ctx->base.callback_data);
2857 ctx->mc_completed = 0;
2858 }
2859
2860 static inline void sync_it_packet_for_cpu(struct context *context,
2861 struct descriptor *pd)
2862 {
2863 __le16 control;
2864 u32 buffer_dma;
2865
2866 /* only packets beginning with OUTPUT_MORE* have data buffers */
2867 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2868 return;
2869
2870 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2871 pd += 2;
2872
2873 /*
2874 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2875 * data buffer is in the context program's coherent page and must not
2876 * be synced.
2877 */
2878 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2879 (context->current_bus & PAGE_MASK)) {
2880 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2881 return;
2882 pd++;
2883 }
2884
2885 do {
2886 buffer_dma = le32_to_cpu(pd->data_address);
2887 dma_sync_single_range_for_cpu(context->ohci->card.device,
2888 buffer_dma & PAGE_MASK,
2889 buffer_dma & ~PAGE_MASK,
2890 le16_to_cpu(pd->req_count),
2891 DMA_TO_DEVICE);
2892 control = pd->control;
2893 pd++;
2894 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2895 }
2896
2897 static int handle_it_packet(struct context *context,
2898 struct descriptor *d,
2899 struct descriptor *last)
2900 {
2901 struct iso_context *ctx =
2902 container_of(context, struct iso_context, context);
2903 struct descriptor *pd;
2904 __be32 *ctx_hdr;
2905
2906 for (pd = d; pd <= last; pd++)
2907 if (pd->transfer_status)
2908 break;
2909 if (pd > last)
2910 /* Descriptor(s) not done yet, stop iteration */
2911 return 0;
2912
2913 sync_it_packet_for_cpu(context, d);
2914
2915 if (ctx->header_length + 4 > PAGE_SIZE) {
2916 if (ctx->base.drop_overflow_headers)
2917 return 1;
2918 flush_iso_completions(ctx);
2919 }
2920
2921 ctx_hdr = ctx->header + ctx->header_length;
2922 ctx->last_timestamp = le16_to_cpu(last->res_count);
2923 /* Present this value as big-endian to match the receive code */
2924 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2925 le16_to_cpu(pd->res_count));
2926 ctx->header_length += 4;
2927
2928 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2929 flush_iso_completions(ctx);
2930
2931 return 1;
2932 }
2933
2934 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2935 {
2936 u32 hi = channels >> 32, lo = channels;
2937
2938 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2939 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2940 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2941 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2942 mmiowb();
2943 ohci->mc_channels = channels;
2944 }
2945
2946 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2947 int type, int channel, size_t header_size)
2948 {
2949 struct fw_ohci *ohci = fw_ohci(card);
2950 struct iso_context *uninitialized_var(ctx);
2951 descriptor_callback_t uninitialized_var(callback);
2952 u64 *uninitialized_var(channels);
2953 u32 *uninitialized_var(mask), uninitialized_var(regs);
2954 int index, ret = -EBUSY;
2955
2956 spin_lock_irq(&ohci->lock);
2957
2958 switch (type) {
2959 case FW_ISO_CONTEXT_TRANSMIT:
2960 mask = &ohci->it_context_mask;
2961 callback = handle_it_packet;
2962 index = ffs(*mask) - 1;
2963 if (index >= 0) {
2964 *mask &= ~(1 << index);
2965 regs = OHCI1394_IsoXmitContextBase(index);
2966 ctx = &ohci->it_context_list[index];
2967 }
2968 break;
2969
2970 case FW_ISO_CONTEXT_RECEIVE:
2971 channels = &ohci->ir_context_channels;
2972 mask = &ohci->ir_context_mask;
2973 callback = handle_ir_packet_per_buffer;
2974 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2975 if (index >= 0) {
2976 *channels &= ~(1ULL << channel);
2977 *mask &= ~(1 << index);
2978 regs = OHCI1394_IsoRcvContextBase(index);
2979 ctx = &ohci->ir_context_list[index];
2980 }
2981 break;
2982
2983 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2984 mask = &ohci->ir_context_mask;
2985 callback = handle_ir_buffer_fill;
2986 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2987 if (index >= 0) {
2988 ohci->mc_allocated = true;
2989 *mask &= ~(1 << index);
2990 regs = OHCI1394_IsoRcvContextBase(index);
2991 ctx = &ohci->ir_context_list[index];
2992 }
2993 break;
2994
2995 default:
2996 index = -1;
2997 ret = -ENOSYS;
2998 }
2999
3000 spin_unlock_irq(&ohci->lock);
3001
3002 if (index < 0)
3003 return ERR_PTR(ret);
3004
3005 memset(ctx, 0, sizeof(*ctx));
3006 ctx->header_length = 0;
3007 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3008 if (ctx->header == NULL) {
3009 ret = -ENOMEM;
3010 goto out;
3011 }
3012 ret = context_init(&ctx->context, ohci, regs, callback);
3013 if (ret < 0)
3014 goto out_with_header;
3015
3016 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3017 set_multichannel_mask(ohci, 0);
3018 ctx->mc_completed = 0;
3019 }
3020
3021 return &ctx->base;
3022
3023 out_with_header:
3024 free_page((unsigned long)ctx->header);
3025 out:
3026 spin_lock_irq(&ohci->lock);
3027
3028 switch (type) {
3029 case FW_ISO_CONTEXT_RECEIVE:
3030 *channels |= 1ULL << channel;
3031 break;
3032
3033 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3034 ohci->mc_allocated = false;
3035 break;
3036 }
3037 *mask |= 1 << index;
3038
3039 spin_unlock_irq(&ohci->lock);
3040
3041 return ERR_PTR(ret);
3042 }
3043
3044 static int ohci_start_iso(struct fw_iso_context *base,
3045 s32 cycle, u32 sync, u32 tags)
3046 {
3047 struct iso_context *ctx = container_of(base, struct iso_context, base);
3048 struct fw_ohci *ohci = ctx->context.ohci;
3049 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3050 int index;
3051
3052 /* the controller cannot start without any queued packets */
3053 if (ctx->context.last->branch_address == 0)
3054 return -ENODATA;
3055
3056 switch (ctx->base.type) {
3057 case FW_ISO_CONTEXT_TRANSMIT:
3058 index = ctx - ohci->it_context_list;
3059 match = 0;
3060 if (cycle >= 0)
3061 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3062 (cycle & 0x7fff) << 16;
3063
3064 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3065 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3066 context_run(&ctx->context, match);
3067 break;
3068
3069 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3070 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3071 /* fall through */
3072 case FW_ISO_CONTEXT_RECEIVE:
3073 index = ctx - ohci->ir_context_list;
3074 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3075 if (cycle >= 0) {
3076 match |= (cycle & 0x07fff) << 12;
3077 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3078 }
3079
3080 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3081 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3082 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3083 context_run(&ctx->context, control);
3084
3085 ctx->sync = sync;
3086 ctx->tags = tags;
3087
3088 break;
3089 }
3090
3091 return 0;
3092 }
3093
3094 static int ohci_stop_iso(struct fw_iso_context *base)
3095 {
3096 struct fw_ohci *ohci = fw_ohci(base->card);
3097 struct iso_context *ctx = container_of(base, struct iso_context, base);
3098 int index;
3099
3100 switch (ctx->base.type) {
3101 case FW_ISO_CONTEXT_TRANSMIT:
3102 index = ctx - ohci->it_context_list;
3103 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3104 break;
3105
3106 case FW_ISO_CONTEXT_RECEIVE:
3107 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3108 index = ctx - ohci->ir_context_list;
3109 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3110 break;
3111 }
3112 flush_writes(ohci);
3113 context_stop(&ctx->context);
3114 tasklet_kill(&ctx->context.tasklet);
3115
3116 return 0;
3117 }
3118
3119 static void ohci_free_iso_context(struct fw_iso_context *base)
3120 {
3121 struct fw_ohci *ohci = fw_ohci(base->card);
3122 struct iso_context *ctx = container_of(base, struct iso_context, base);
3123 unsigned long flags;
3124 int index;
3125
3126 ohci_stop_iso(base);
3127 context_release(&ctx->context);
3128 free_page((unsigned long)ctx->header);
3129
3130 spin_lock_irqsave(&ohci->lock, flags);
3131
3132 switch (base->type) {
3133 case FW_ISO_CONTEXT_TRANSMIT:
3134 index = ctx - ohci->it_context_list;
3135 ohci->it_context_mask |= 1 << index;
3136 break;
3137
3138 case FW_ISO_CONTEXT_RECEIVE:
3139 index = ctx - ohci->ir_context_list;
3140 ohci->ir_context_mask |= 1 << index;
3141 ohci->ir_context_channels |= 1ULL << base->channel;
3142 break;
3143
3144 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3145 index = ctx - ohci->ir_context_list;
3146 ohci->ir_context_mask |= 1 << index;
3147 ohci->ir_context_channels |= ohci->mc_channels;
3148 ohci->mc_channels = 0;
3149 ohci->mc_allocated = false;
3150 break;
3151 }
3152
3153 spin_unlock_irqrestore(&ohci->lock, flags);
3154 }
3155
3156 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3157 {
3158 struct fw_ohci *ohci = fw_ohci(base->card);
3159 unsigned long flags;
3160 int ret;
3161
3162 switch (base->type) {
3163 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3164
3165 spin_lock_irqsave(&ohci->lock, flags);
3166
3167 /* Don't allow multichannel to grab other contexts' channels. */
3168 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3169 *channels = ohci->ir_context_channels;
3170 ret = -EBUSY;
3171 } else {
3172 set_multichannel_mask(ohci, *channels);
3173 ret = 0;
3174 }
3175
3176 spin_unlock_irqrestore(&ohci->lock, flags);
3177
3178 break;
3179 default:
3180 ret = -EINVAL;
3181 }
3182
3183 return ret;
3184 }
3185
3186 #ifdef CONFIG_PM
3187 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3188 {
3189 int i;
3190 struct iso_context *ctx;
3191
3192 for (i = 0 ; i < ohci->n_ir ; i++) {
3193 ctx = &ohci->ir_context_list[i];
3194 if (ctx->context.running)
3195 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3196 }
3197
3198 for (i = 0 ; i < ohci->n_it ; i++) {
3199 ctx = &ohci->it_context_list[i];
3200 if (ctx->context.running)
3201 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3202 }
3203 }
3204 #endif
3205
3206 static int queue_iso_transmit(struct iso_context *ctx,
3207 struct fw_iso_packet *packet,
3208 struct fw_iso_buffer *buffer,
3209 unsigned long payload)
3210 {
3211 struct descriptor *d, *last, *pd;
3212 struct fw_iso_packet *p;
3213 __le32 *header;
3214 dma_addr_t d_bus, page_bus;
3215 u32 z, header_z, payload_z, irq;
3216 u32 payload_index, payload_end_index, next_page_index;
3217 int page, end_page, i, length, offset;
3218
3219 p = packet;
3220 payload_index = payload;
3221
3222 if (p->skip)
3223 z = 1;
3224 else
3225 z = 2;
3226 if (p->header_length > 0)
3227 z++;
3228
3229 /* Determine the first page the payload isn't contained in. */
3230 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3231 if (p->payload_length > 0)
3232 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3233 else
3234 payload_z = 0;
3235
3236 z += payload_z;
3237
3238 /* Get header size in number of descriptors. */
3239 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3240
3241 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3242 if (d == NULL)
3243 return -ENOMEM;
3244
3245 if (!p->skip) {
3246 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3247 d[0].req_count = cpu_to_le16(8);
3248 /*
3249 * Link the skip address to this descriptor itself. This causes
3250 * a context to skip a cycle whenever lost cycles or FIFO
3251 * overruns occur, without dropping the data. The application
3252 * should then decide whether this is an error condition or not.
3253 * FIXME: Make the context's cycle-lost behaviour configurable?
3254 */
3255 d[0].branch_address = cpu_to_le32(d_bus | z);
3256
3257 header = (__le32 *) &d[1];
3258 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3259 IT_HEADER_TAG(p->tag) |
3260 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3261 IT_HEADER_CHANNEL(ctx->base.channel) |
3262 IT_HEADER_SPEED(ctx->base.speed));
3263 header[1] =
3264 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3265 p->payload_length));
3266 }
3267
3268 if (p->header_length > 0) {
3269 d[2].req_count = cpu_to_le16(p->header_length);
3270 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3271 memcpy(&d[z], p->header, p->header_length);
3272 }
3273
3274 pd = d + z - payload_z;
3275 payload_end_index = payload_index + p->payload_length;
3276 for (i = 0; i < payload_z; i++) {
3277 page = payload_index >> PAGE_SHIFT;
3278 offset = payload_index & ~PAGE_MASK;
3279 next_page_index = (page + 1) << PAGE_SHIFT;
3280 length =
3281 min(next_page_index, payload_end_index) - payload_index;
3282 pd[i].req_count = cpu_to_le16(length);
3283
3284 page_bus = page_private(buffer->pages[page]);
3285 pd[i].data_address = cpu_to_le32(page_bus + offset);
3286
3287 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3288 page_bus, offset, length,
3289 DMA_TO_DEVICE);
3290
3291 payload_index += length;
3292 }
3293
3294 if (p->interrupt)
3295 irq = DESCRIPTOR_IRQ_ALWAYS;
3296 else
3297 irq = DESCRIPTOR_NO_IRQ;
3298
3299 last = z == 2 ? d : d + z - 1;
3300 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3301 DESCRIPTOR_STATUS |
3302 DESCRIPTOR_BRANCH_ALWAYS |
3303 irq);
3304
3305 context_append(&ctx->context, d, z, header_z);
3306
3307 return 0;
3308 }
3309
3310 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3311 struct fw_iso_packet *packet,
3312 struct fw_iso_buffer *buffer,
3313 unsigned long payload)
3314 {
3315 struct device *device = ctx->context.ohci->card.device;
3316 struct descriptor *d, *pd;
3317 dma_addr_t d_bus, page_bus;
3318 u32 z, header_z, rest;
3319 int i, j, length;
3320 int page, offset, packet_count, header_size, payload_per_buffer;
3321
3322 /*
3323 * The OHCI controller puts the isochronous header and trailer in the
3324 * buffer, so we need at least 8 bytes.
3325 */
3326 packet_count = packet->header_length / ctx->base.header_size;
3327 header_size = max(ctx->base.header_size, (size_t)8);
3328
3329 /* Get header size in number of descriptors. */
3330 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3331 page = payload >> PAGE_SHIFT;
3332 offset = payload & ~PAGE_MASK;
3333 payload_per_buffer = packet->payload_length / packet_count;
3334
3335 for (i = 0; i < packet_count; i++) {
3336 /* d points to the header descriptor */
3337 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3338 d = context_get_descriptors(&ctx->context,
3339 z + header_z, &d_bus);
3340 if (d == NULL)
3341 return -ENOMEM;
3342
3343 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3344 DESCRIPTOR_INPUT_MORE);
3345 if (packet->skip && i == 0)
3346 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3347 d->req_count = cpu_to_le16(header_size);
3348 d->res_count = d->req_count;
3349 d->transfer_status = 0;
3350 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3351
3352 rest = payload_per_buffer;
3353 pd = d;
3354 for (j = 1; j < z; j++) {
3355 pd++;
3356 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3357 DESCRIPTOR_INPUT_MORE);
3358
3359 if (offset + rest < PAGE_SIZE)
3360 length = rest;
3361 else
3362 length = PAGE_SIZE - offset;
3363 pd->req_count = cpu_to_le16(length);
3364 pd->res_count = pd->req_count;
3365 pd->transfer_status = 0;
3366
3367 page_bus = page_private(buffer->pages[page]);
3368 pd->data_address = cpu_to_le32(page_bus + offset);
3369
3370 dma_sync_single_range_for_device(device, page_bus,
3371 offset, length,
3372 DMA_FROM_DEVICE);
3373
3374 offset = (offset + length) & ~PAGE_MASK;
3375 rest -= length;
3376 if (offset == 0)
3377 page++;
3378 }
3379 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3380 DESCRIPTOR_INPUT_LAST |
3381 DESCRIPTOR_BRANCH_ALWAYS);
3382 if (packet->interrupt && i == packet_count - 1)
3383 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3384
3385 context_append(&ctx->context, d, z, header_z);
3386 }
3387
3388 return 0;
3389 }
3390
3391 static int queue_iso_buffer_fill(struct iso_context *ctx,
3392 struct fw_iso_packet *packet,
3393 struct fw_iso_buffer *buffer,
3394 unsigned long payload)
3395 {
3396 struct descriptor *d;
3397 dma_addr_t d_bus, page_bus;
3398 int page, offset, rest, z, i, length;
3399
3400 page = payload >> PAGE_SHIFT;
3401 offset = payload & ~PAGE_MASK;
3402 rest = packet->payload_length;
3403
3404 /* We need one descriptor for each page in the buffer. */
3405 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3406
3407 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3408 return -EFAULT;
3409
3410 for (i = 0; i < z; i++) {
3411 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3412 if (d == NULL)
3413 return -ENOMEM;
3414
3415 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3416 DESCRIPTOR_BRANCH_ALWAYS);
3417 if (packet->skip && i == 0)
3418 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3419 if (packet->interrupt && i == z - 1)
3420 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3421
3422 if (offset + rest < PAGE_SIZE)
3423 length = rest;
3424 else
3425 length = PAGE_SIZE - offset;
3426 d->req_count = cpu_to_le16(length);
3427 d->res_count = d->req_count;
3428 d->transfer_status = 0;
3429
3430 page_bus = page_private(buffer->pages[page]);
3431 d->data_address = cpu_to_le32(page_bus + offset);
3432
3433 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3434 page_bus, offset, length,
3435 DMA_FROM_DEVICE);
3436
3437 rest -= length;
3438 offset = 0;
3439 page++;
3440
3441 context_append(&ctx->context, d, 1, 0);
3442 }
3443
3444 return 0;
3445 }
3446
3447 static int ohci_queue_iso(struct fw_iso_context *base,
3448 struct fw_iso_packet *packet,
3449 struct fw_iso_buffer *buffer,
3450 unsigned long payload)
3451 {
3452 struct iso_context *ctx = container_of(base, struct iso_context, base);
3453 unsigned long flags;
3454 int ret = -ENOSYS;
3455
3456 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3457 switch (base->type) {
3458 case FW_ISO_CONTEXT_TRANSMIT:
3459 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3460 break;
3461 case FW_ISO_CONTEXT_RECEIVE:
3462 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3463 break;
3464 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3465 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3466 break;
3467 }
3468 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3469
3470 return ret;
3471 }
3472
3473 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3474 {
3475 struct context *ctx =
3476 &container_of(base, struct iso_context, base)->context;
3477
3478 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3479 }
3480
3481 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3482 {
3483 struct iso_context *ctx = container_of(base, struct iso_context, base);
3484 int ret = 0;
3485
3486 tasklet_disable(&ctx->context.tasklet);
3487
3488 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3489 context_tasklet((unsigned long)&ctx->context);
3490
3491 switch (base->type) {
3492 case FW_ISO_CONTEXT_TRANSMIT:
3493 case FW_ISO_CONTEXT_RECEIVE:
3494 if (ctx->header_length != 0)
3495 flush_iso_completions(ctx);
3496 break;
3497 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3498 if (ctx->mc_completed != 0)
3499 flush_ir_buffer_fill(ctx);
3500 break;
3501 default:
3502 ret = -ENOSYS;
3503 }
3504
3505 clear_bit_unlock(0, &ctx->flushing_completions);
3506 smp_mb__after_atomic();
3507 }
3508
3509 tasklet_enable(&ctx->context.tasklet);
3510
3511 return ret;
3512 }
3513
3514 static const struct fw_card_driver ohci_driver = {
3515 .enable = ohci_enable,
3516 .read_phy_reg = ohci_read_phy_reg,
3517 .update_phy_reg = ohci_update_phy_reg,
3518 .set_config_rom = ohci_set_config_rom,
3519 .send_request = ohci_send_request,
3520 .send_response = ohci_send_response,
3521 .cancel_packet = ohci_cancel_packet,
3522 .enable_phys_dma = ohci_enable_phys_dma,
3523 .read_csr = ohci_read_csr,
3524 .write_csr = ohci_write_csr,
3525
3526 .allocate_iso_context = ohci_allocate_iso_context,
3527 .free_iso_context = ohci_free_iso_context,
3528 .set_iso_channels = ohci_set_iso_channels,
3529 .queue_iso = ohci_queue_iso,
3530 .flush_queue_iso = ohci_flush_queue_iso,
3531 .flush_iso_completions = ohci_flush_iso_completions,
3532 .start_iso = ohci_start_iso,
3533 .stop_iso = ohci_stop_iso,
3534 };
3535
3536 #ifdef CONFIG_PPC_PMAC
3537 static void pmac_ohci_on(struct pci_dev *dev)
3538 {
3539 if (machine_is(powermac)) {
3540 struct device_node *ofn = pci_device_to_OF_node(dev);
3541
3542 if (ofn) {
3543 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3544 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3545 }
3546 }
3547 }
3548
3549 static void pmac_ohci_off(struct pci_dev *dev)
3550 {
3551 if (machine_is(powermac)) {
3552 struct device_node *ofn = pci_device_to_OF_node(dev);
3553
3554 if (ofn) {
3555 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3556 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3557 }
3558 }
3559 }
3560 #else
3561 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3562 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3563 #endif /* CONFIG_PPC_PMAC */
3564
3565 static int pci_probe(struct pci_dev *dev,
3566 const struct pci_device_id *ent)
3567 {
3568 struct fw_ohci *ohci;
3569 u32 bus_options, max_receive, link_speed, version;
3570 u64 guid;
3571 int i, err;
3572 size_t size;
3573
3574 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3575 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3576 return -ENOSYS;
3577 }
3578
3579 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3580 if (ohci == NULL) {
3581 err = -ENOMEM;
3582 goto fail;
3583 }
3584
3585 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3586
3587 pmac_ohci_on(dev);
3588
3589 err = pci_enable_device(dev);
3590 if (err) {
3591 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3592 goto fail_free;
3593 }
3594
3595 pci_set_master(dev);
3596 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3597 pci_set_drvdata(dev, ohci);
3598
3599 spin_lock_init(&ohci->lock);
3600 mutex_init(&ohci->phy_reg_mutex);
3601
3602 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3603
3604 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3605 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3606 ohci_err(ohci, "invalid MMIO resource\n");
3607 err = -ENXIO;
3608 goto fail_disable;
3609 }
3610
3611 err = pci_request_region(dev, 0, ohci_driver_name);
3612 if (err) {
3613 ohci_err(ohci, "MMIO resource unavailable\n");
3614 goto fail_disable;
3615 }
3616
3617 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3618 if (ohci->registers == NULL) {
3619 ohci_err(ohci, "failed to remap registers\n");
3620 err = -ENXIO;
3621 goto fail_iomem;
3622 }
3623
3624 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3625 if ((ohci_quirks[i].vendor == dev->vendor) &&
3626 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3627 ohci_quirks[i].device == dev->device) &&
3628 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3629 ohci_quirks[i].revision >= dev->revision)) {
3630 ohci->quirks = ohci_quirks[i].flags;
3631 break;
3632 }
3633 if (param_quirks)
3634 ohci->quirks = param_quirks;
3635
3636 /*
3637 * Because dma_alloc_coherent() allocates at least one page,
3638 * we save space by using a common buffer for the AR request/
3639 * response descriptors and the self IDs buffer.
3640 */
3641 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3642 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3643 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3644 PAGE_SIZE,
3645 &ohci->misc_buffer_bus,
3646 GFP_KERNEL);
3647 if (!ohci->misc_buffer) {
3648 err = -ENOMEM;
3649 goto fail_iounmap;
3650 }
3651
3652 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3653 OHCI1394_AsReqRcvContextControlSet);
3654 if (err < 0)
3655 goto fail_misc_buf;
3656
3657 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3658 OHCI1394_AsRspRcvContextControlSet);
3659 if (err < 0)
3660 goto fail_arreq_ctx;
3661
3662 err = context_init(&ohci->at_request_ctx, ohci,
3663 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3664 if (err < 0)
3665 goto fail_arrsp_ctx;
3666
3667 err = context_init(&ohci->at_response_ctx, ohci,
3668 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3669 if (err < 0)
3670 goto fail_atreq_ctx;
3671
3672 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3673 ohci->ir_context_channels = ~0ULL;
3674 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3675 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3676 ohci->ir_context_mask = ohci->ir_context_support;
3677 ohci->n_ir = hweight32(ohci->ir_context_mask);
3678 size = sizeof(struct iso_context) * ohci->n_ir;
3679 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3680
3681 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3682 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3683 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3684 ohci->it_context_mask = ohci->it_context_support;
3685 ohci->n_it = hweight32(ohci->it_context_mask);
3686 size = sizeof(struct iso_context) * ohci->n_it;
3687 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3688
3689 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3690 err = -ENOMEM;
3691 goto fail_contexts;
3692 }
3693
3694 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3695 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3696
3697 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3698 max_receive = (bus_options >> 12) & 0xf;
3699 link_speed = bus_options & 0x7;
3700 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3701 reg_read(ohci, OHCI1394_GUIDLo);
3702
3703 if (!(ohci->quirks & QUIRK_NO_MSI))
3704 pci_enable_msi(dev);
3705 if (request_irq(dev->irq, irq_handler,
3706 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3707 ohci_driver_name, ohci)) {
3708 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3709 err = -EIO;
3710 goto fail_msi;
3711 }
3712
3713 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3714 if (err)
3715 goto fail_irq;
3716
3717 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3718 ohci_notice(ohci,
3719 "added OHCI v%x.%x device as card %d, "
3720 "%d IR + %d IT contexts, quirks 0x%x%s\n",
3721 version >> 16, version & 0xff, ohci->card.index,
3722 ohci->n_ir, ohci->n_it, ohci->quirks,
3723 reg_read(ohci, OHCI1394_PhyUpperBound) ?
3724 ", physUB" : "");
3725
3726 return 0;
3727
3728 fail_irq:
3729 free_irq(dev->irq, ohci);
3730 fail_msi:
3731 pci_disable_msi(dev);
3732 fail_contexts:
3733 kfree(ohci->ir_context_list);
3734 kfree(ohci->it_context_list);
3735 context_release(&ohci->at_response_ctx);
3736 fail_atreq_ctx:
3737 context_release(&ohci->at_request_ctx);
3738 fail_arrsp_ctx:
3739 ar_context_release(&ohci->ar_response_ctx);
3740 fail_arreq_ctx:
3741 ar_context_release(&ohci->ar_request_ctx);
3742 fail_misc_buf:
3743 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3744 ohci->misc_buffer, ohci->misc_buffer_bus);
3745 fail_iounmap:
3746 pci_iounmap(dev, ohci->registers);
3747 fail_iomem:
3748 pci_release_region(dev, 0);
3749 fail_disable:
3750 pci_disable_device(dev);
3751 fail_free:
3752 kfree(ohci);
3753 pmac_ohci_off(dev);
3754 fail:
3755 return err;
3756 }
3757
3758 static void pci_remove(struct pci_dev *dev)
3759 {
3760 struct fw_ohci *ohci = pci_get_drvdata(dev);
3761
3762 /*
3763 * If the removal is happening from the suspend state, LPS won't be
3764 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3765 */
3766 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3767 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3768 flush_writes(ohci);
3769 }
3770 cancel_work_sync(&ohci->bus_reset_work);
3771 fw_core_remove_card(&ohci->card);
3772
3773 /*
3774 * FIXME: Fail all pending packets here, now that the upper
3775 * layers can't queue any more.
3776 */
3777
3778 software_reset(ohci);
3779 free_irq(dev->irq, ohci);
3780
3781 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3782 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3783 ohci->next_config_rom, ohci->next_config_rom_bus);
3784 if (ohci->config_rom)
3785 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3786 ohci->config_rom, ohci->config_rom_bus);
3787 ar_context_release(&ohci->ar_request_ctx);
3788 ar_context_release(&ohci->ar_response_ctx);
3789 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3790 ohci->misc_buffer, ohci->misc_buffer_bus);
3791 context_release(&ohci->at_request_ctx);
3792 context_release(&ohci->at_response_ctx);
3793 kfree(ohci->it_context_list);
3794 kfree(ohci->ir_context_list);
3795 pci_disable_msi(dev);
3796 pci_iounmap(dev, ohci->registers);
3797 pci_release_region(dev, 0);
3798 pci_disable_device(dev);
3799 kfree(ohci);
3800 pmac_ohci_off(dev);
3801
3802 dev_notice(&dev->dev, "removed fw-ohci device\n");
3803 }
3804
3805 #ifdef CONFIG_PM
3806 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3807 {
3808 struct fw_ohci *ohci = pci_get_drvdata(dev);
3809 int err;
3810
3811 software_reset(ohci);
3812 err = pci_save_state(dev);
3813 if (err) {
3814 ohci_err(ohci, "pci_save_state failed\n");
3815 return err;
3816 }
3817 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3818 if (err)
3819 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3820 pmac_ohci_off(dev);
3821
3822 return 0;
3823 }
3824
3825 static int pci_resume(struct pci_dev *dev)
3826 {
3827 struct fw_ohci *ohci = pci_get_drvdata(dev);
3828 int err;
3829
3830 pmac_ohci_on(dev);
3831 pci_set_power_state(dev, PCI_D0);
3832 pci_restore_state(dev);
3833 err = pci_enable_device(dev);
3834 if (err) {
3835 ohci_err(ohci, "pci_enable_device failed\n");
3836 return err;
3837 }
3838
3839 /* Some systems don't setup GUID register on resume from ram */
3840 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3841 !reg_read(ohci, OHCI1394_GUIDHi)) {
3842 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3843 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3844 }
3845
3846 err = ohci_enable(&ohci->card, NULL, 0);
3847 if (err)
3848 return err;
3849
3850 ohci_resume_iso_dma(ohci);
3851
3852 return 0;
3853 }
3854 #endif
3855
3856 static const struct pci_device_id pci_table[] = {
3857 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3858 { }
3859 };
3860
3861 MODULE_DEVICE_TABLE(pci, pci_table);
3862
3863 static struct pci_driver fw_ohci_pci_driver = {
3864 .name = ohci_driver_name,
3865 .id_table = pci_table,
3866 .probe = pci_probe,
3867 .remove = pci_remove,
3868 #ifdef CONFIG_PM
3869 .resume = pci_resume,
3870 .suspend = pci_suspend,
3871 #endif
3872 };
3873
3874 static int __init fw_ohci_init(void)
3875 {
3876 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3877 if (!selfid_workqueue)
3878 return -ENOMEM;
3879
3880 return pci_register_driver(&fw_ohci_pci_driver);
3881 }
3882
3883 static void __exit fw_ohci_cleanup(void)
3884 {
3885 pci_unregister_driver(&fw_ohci_pci_driver);
3886 destroy_workqueue(selfid_workqueue);
3887 }
3888
3889 module_init(fw_ohci_init);
3890 module_exit(fw_ohci_cleanup);
3891
3892 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3893 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3894 MODULE_LICENSE("GPL");
3895
3896 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3897 MODULE_ALIAS("ohci1394");
Michael's Linux tree.