2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: BSD-3-Clause
10 #include <linux/errno.h>
11 #include <asm/arch/fpga_manager.h>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
15 DECLARE_GLOBAL_DATA_PTR
;
18 #define FPGA_TIMEOUT_CNT 0x1000000
20 static struct socfpga_fpga_manager
*fpgamgr_regs
=
21 (struct socfpga_fpga_manager
*)SOCFPGA_FPGAMGRREGS_ADDRESS
;
22 static struct socfpga_system_manager
*sysmgr_regs
=
23 (struct socfpga_system_manager
*)SOCFPGA_SYSMGR_ADDRESS
;
26 static void fpgamgr_set_cd_ratio(unsigned long ratio
)
28 clrsetbits_le32(&fpgamgr_regs
->ctrl
,
29 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB
,
30 (ratio
& 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB
);
33 static int fpgamgr_dclkcnt_set(unsigned long cnt
)
37 /* Clear any existing done status */
38 if (readl(&fpgamgr_regs
->dclkstat
))
39 writel(0x1, &fpgamgr_regs
->dclkstat
);
41 /* Write the dclkcnt */
42 writel(cnt
, &fpgamgr_regs
->dclkcnt
);
44 /* Wait till the dclkcnt done */
45 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
46 if (!readl(&fpgamgr_regs
->dclkstat
))
49 writel(0x1, &fpgamgr_regs
->dclkstat
);
56 /* Start the FPGA programming by initialize the FPGA Manager */
57 static int fpgamgr_program_init(void)
59 unsigned long msel
, i
;
61 /* Get the MSEL value */
62 msel
= readl(&fpgamgr_regs
->stat
);
63 msel
&= FPGAMGRREGS_STAT_MSEL_MASK
;
64 msel
>>= FPGAMGRREGS_STAT_MSEL_LSB
;
68 * If MSEL[3] = 1, cfg width = 32 bit
71 setbits_le32(&fpgamgr_regs
->ctrl
,
72 FPGAMGRREGS_CTRL_CFGWDTH_MASK
);
74 /* To determine the CD ratio */
75 /* MSEL[1:0] = 0, CD Ratio = 1 */
76 if ((msel
& 0x3) == 0x0)
77 fpgamgr_set_cd_ratio(CDRATIO_x1
);
78 /* MSEL[1:0] = 1, CD Ratio = 4 */
79 else if ((msel
& 0x3) == 0x1)
80 fpgamgr_set_cd_ratio(CDRATIO_x4
);
81 /* MSEL[1:0] = 2, CD Ratio = 8 */
82 else if ((msel
& 0x3) == 0x2)
83 fpgamgr_set_cd_ratio(CDRATIO_x8
);
85 } else { /* MSEL[3] = 0 */
86 clrbits_le32(&fpgamgr_regs
->ctrl
,
87 FPGAMGRREGS_CTRL_CFGWDTH_MASK
);
89 /* To determine the CD ratio */
90 /* MSEL[1:0] = 0, CD Ratio = 1 */
91 if ((msel
& 0x3) == 0x0)
92 fpgamgr_set_cd_ratio(CDRATIO_x1
);
93 /* MSEL[1:0] = 1, CD Ratio = 2 */
94 else if ((msel
& 0x3) == 0x1)
95 fpgamgr_set_cd_ratio(CDRATIO_x2
);
96 /* MSEL[1:0] = 2, CD Ratio = 4 */
97 else if ((msel
& 0x3) == 0x2)
98 fpgamgr_set_cd_ratio(CDRATIO_x4
);
101 /* To enable FPGA Manager configuration */
102 clrbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_NCE_MASK
);
104 /* To enable FPGA Manager drive over configuration line */
105 setbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_EN_MASK
);
107 /* Put FPGA into reset phase */
108 setbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK
);
110 /* (1) wait until FPGA enter reset phase */
111 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
112 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE
)
116 /* If not in reset state, return error */
117 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE
) {
118 puts("FPGA: Could not reset\n");
122 /* Release FPGA from reset phase */
123 clrbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK
);
125 /* (2) wait until FPGA enter configuration phase */
126 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
127 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE
)
131 /* If not in configuration state, return error */
132 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE
) {
133 puts("FPGA: Could not configure\n");
137 /* Clear all interrupts in CB Monitor */
138 writel(0xFFF, &fpgamgr_regs
->gpio_porta_eoi
);
140 /* Enable AXI configuration */
141 setbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_AXICFGEN_MASK
);
146 /* Write the RBF data to FPGA Manager */
147 static void fpgamgr_program_write(const void *rbf_data
, unsigned long rbf_size
)
149 uint32_t src
= (uint32_t)rbf_data
;
150 uint32_t dst
= SOCFPGA_FPGAMGRDATA_ADDRESS
;
152 /* Number of loops for 32-byte long copying. */
153 uint32_t loops32
= rbf_size
/ 32;
154 /* Number of loops for 4-byte long copying + trailing bytes */
155 uint32_t loops4
= DIV_ROUND_UP(rbf_size
% 32, 4);
158 "1: ldmia %0!, {r0-r7}\n"
159 " stmia %1!, {r0-r7}\n"
165 "2: ldr %2, [%0], #4\n"
170 : "+r"(src
), "+r"(dst
), "+r"(loops32
), "+r"(loops4
) :
171 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
174 /* Ensure the FPGA entering config done */
175 static int fpgamgr_program_poll_cd(void)
177 const uint32_t mask
= FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK
|
178 FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK
;
179 unsigned long reg
, i
;
181 /* (3) wait until full config done */
182 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
183 reg
= readl(&fpgamgr_regs
->gpio_ext_porta
);
187 printf("FPGA: Configuration error.\n");
191 /* Config done without error */
196 /* Timeout happened, return error */
197 if (i
== FPGA_TIMEOUT_CNT
) {
198 printf("FPGA: Timeout waiting for program.\n");
202 /* Disable AXI configuration */
203 clrbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_AXICFGEN_MASK
);
208 /* Ensure the FPGA entering init phase */
209 static int fpgamgr_program_poll_initphase(void)
213 /* Additional clocks for the CB to enter initialization phase */
214 if (fpgamgr_dclkcnt_set(0x4))
217 /* (4) wait until FPGA enter init phase or user mode */
218 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
219 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE
)
221 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE
)
225 /* If not in configuration state, return error */
226 if (i
== FPGA_TIMEOUT_CNT
)
232 /* Ensure the FPGA entering user mode */
233 static int fpgamgr_program_poll_usermode(void)
237 /* Additional clocks for the CB to exit initialization phase */
238 if (fpgamgr_dclkcnt_set(0x5000))
241 /* (5) wait until FPGA enter user mode */
242 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
243 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE
)
246 /* If not in configuration state, return error */
247 if (i
== FPGA_TIMEOUT_CNT
)
250 /* To release FPGA Manager drive over configuration line */
251 clrbits_le32(&fpgamgr_regs
->ctrl
, FPGAMGRREGS_CTRL_EN_MASK
);
257 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
258 * Return 0 for sucess, non-zero for error.
260 int socfpga_load(Altera_desc
*desc
, const void *rbf_data
, size_t rbf_size
)
262 unsigned long status
;
264 if ((uint32_t)rbf_data
& 0x3) {
265 puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
269 /* Prior programming the FPGA, all bridges need to be shut off */
271 /* Disable all signals from hps peripheral controller to fpga */
272 writel(0, &sysmgr_regs
->fpgaintfgrp_module
);
274 /* Disable all signals from FPGA to HPS SDRAM */
275 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
276 writel(0, SOCFPGA_SDR_ADDRESS
+ SDR_CTRLGRP_FPGAPORTRST_ADDRESS
);
278 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
279 socfpga_bridges_reset(1);
281 /* Unmap the bridges from NIC-301 */
282 writel(0x1, SOCFPGA_L3REGS_ADDRESS
);
284 /* Initialize the FPGA Manager */
285 status
= fpgamgr_program_init();
289 /* Write the RBF data to FPGA Manager */
290 fpgamgr_program_write(rbf_data
, rbf_size
);
292 /* Ensure the FPGA entering config done */
293 status
= fpgamgr_program_poll_cd();
297 /* Ensure the FPGA entering init phase */
298 status
= fpgamgr_program_poll_initphase();
302 /* Ensure the FPGA entering user mode */
303 return fpgamgr_program_poll_usermode();