1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
7 #include <asm/arch/fpga_manager.h>
8 #include <asm/arch/reset_manager.h>
9 #include <asm/arch/system_manager.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/misc.h>
19 #define MIN_BITSTREAM_SIZECHECK 230
20 #define ENCRYPTION_OFFSET 69
21 #define COMPRESSION_OFFSET 229
22 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
23 #define FPGA_TIMEOUT_CNT 0x1000000
25 static const struct socfpga_fpga_manager
*fpga_manager_base
=
26 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS
;
28 static const struct socfpga_system_manager
*system_manager_base
=
29 (void *)SOCFPGA_SYSMGR_ADDRESS
;
31 static void fpgamgr_set_cd_ratio(unsigned long ratio
);
33 static uint32_t fpgamgr_get_msel(void)
37 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
38 reg
= (reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD
) >>
39 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB
;
44 static void fpgamgr_set_cfgwdth(int width
)
47 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
48 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
);
50 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
51 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
);
54 int is_fpgamgr_user_mode(void)
56 return (readl(&fpga_manager_base
->imgcfg_stat
) &
57 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) != 0;
60 static int wait_for_user_mode(void)
62 return wait_for_bit_le32(&fpga_manager_base
->imgcfg_stat
,
63 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
,
64 1, FPGA_TIMEOUT_MSEC
, false);
67 static int is_fpgamgr_early_user_mode(void)
69 return (readl(&fpga_manager_base
->imgcfg_stat
) &
70 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
) != 0;
73 int fpgamgr_wait_early_user_mode(void)
75 u32 sync_data
= 0xffffffff;
77 unsigned start
= get_timer(0);
78 unsigned long cd_ratio
;
80 /* Getting existing CDRATIO */
81 cd_ratio
= (readl(&fpga_manager_base
->imgcfg_ctrl_02
) &
82 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
) >>
83 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
;
85 /* Using CDRATIO_X1 for better compatibility */
86 fpgamgr_set_cd_ratio(CDRATIO_x1
);
88 while (!is_fpgamgr_early_user_mode()) {
89 if (get_timer(start
) > FPGA_TIMEOUT_MSEC
)
91 fpgamgr_program_write((const long unsigned int *)&sync_data
,
93 udelay(FPGA_TIMEOUT_MSEC
);
97 debug("Additional %i sync word needed\n", i
);
99 /* restoring original CDRATIO */
100 fpgamgr_set_cd_ratio(cd_ratio
);
105 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
106 static int wait_for_nconfig_pin_and_nstatus_pin(void)
108 unsigned long mask
= ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK
|
109 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
;
112 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
113 * de-asserted, timeout at 1000ms
115 return wait_for_bit_le32(&fpga_manager_base
->imgcfg_stat
, mask
,
116 true, FPGA_TIMEOUT_MSEC
, false);
119 static int wait_for_f2s_nstatus_pin(unsigned long value
)
121 /* Poll until f2s to specific value, timeout at 1000ms */
122 return wait_for_bit_le32(&fpga_manager_base
->imgcfg_stat
,
123 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
,
124 value
, FPGA_TIMEOUT_MSEC
, false);
128 static void fpgamgr_set_cd_ratio(unsigned long ratio
)
130 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
131 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
);
133 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
134 (ratio
<< ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
) &
135 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
);
138 /* get the MSEL value, verify we are set for FPP configuration mode */
139 static int fpgamgr_verify_msel(void)
141 u32 msel
= fpgamgr_get_msel();
143 if (msel
& ~BIT(0)) {
144 printf("Fail: read msel=%d\n", msel
);
152 * Write cdratio and cdwidth based on whether the bitstream is compressed
155 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width
, u32
*rbf_data
,
158 unsigned int cd_ratio
;
159 bool encrypt
, compress
;
162 * According to the bitstream specification,
163 * both encryption and compression status are
164 * in location before offset 230 of the buffer.
166 if (rbf_size
< MIN_BITSTREAM_SIZECHECK
)
169 encrypt
= (rbf_data
[ENCRYPTION_OFFSET
] >> 2) & 3;
170 encrypt
= encrypt
!= 0;
172 compress
= (rbf_data
[COMPRESSION_OFFSET
] >> 1) & 1;
173 compress
= !compress
;
175 debug("header word %d = %08x\n", 69, rbf_data
[69]);
176 debug("header word %d = %08x\n", 229, rbf_data
[229]);
177 debug("read from rbf header: encrypt=%d compress=%d\n", encrypt
, compress
);
180 * from the register map description of cdratio in imgcfg_ctrl_02:
181 * Normal Configuration : 32bit Passive Parallel
182 * Partial Reconfiguration : 16bit Passive Parallel
186 * cd ratio is dependent on cfg width and whether the bitstream
187 * is encrypted and/or compressed.
189 * | width | encr. | compr. | cd ratio |
199 if (!compress
&& !encrypt
) {
200 cd_ratio
= CDRATIO_x1
;
203 cd_ratio
= CDRATIO_x4
;
205 cd_ratio
= CDRATIO_x2
;
207 /* if 32 bit, double the cd ratio (so register
208 field setting is incremented) */
209 if (cfg_width
== CFGWDTH_32
)
213 fpgamgr_set_cfgwdth(cfg_width
);
214 fpgamgr_set_cd_ratio(cd_ratio
);
219 static int fpgamgr_reset(void)
223 /* S2F_NCONFIG = 0 */
224 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
225 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
227 /* Wait for f2s_nstatus == 0 */
228 if (wait_for_f2s_nstatus_pin(0))
231 /* S2F_NCONFIG = 1 */
232 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
233 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
235 /* Wait for f2s_nstatus == 1 */
236 if (wait_for_f2s_nstatus_pin(1))
239 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
240 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
241 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) != 0)
244 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK
) == 0)
250 /* Start the FPGA programming by initialize the FPGA Manager */
251 int fpgamgr_program_init(u32
* rbf_data
, size_t rbf_size
)
256 if (fpgamgr_verify_msel())
260 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32
, rbf_data
, rbf_size
))
265 * Make sure no other external devices are trying to interfere with
268 if (wait_for_nconfig_pin_and_nstatus_pin())
273 * Deassert the signal drives from HPS
283 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
284 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
286 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
287 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK
);
289 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
290 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
291 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
293 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
294 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
296 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
297 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK
|
298 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK
);
303 * S2F_NENABLE_CONFIG = 0
304 * S2F_NENABLE_NCONFIG = 0
306 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
307 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK
);
308 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
309 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK
);
312 * Disable driving signals that HPS doesn't need to drive.
313 * S2F_NENABLE_NSTATUS = 1
314 * S2F_NENABLE_CONDONE = 1
316 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
317 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK
|
318 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK
);
322 * Drive chip select S2F_NCE = 0
324 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
325 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
328 if (wait_for_nconfig_pin_and_nstatus_pin())
332 ret
= fpgamgr_reset();
339 * EN_CFG_CTRL and EN_CFG_DATA = 1
341 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
342 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
343 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
348 /* Ensure the FPGA entering config done */
349 static int fpgamgr_program_poll_cd(void)
351 unsigned long reg
, i
;
353 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
354 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
355 if (reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
)
358 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
) == 0) {
359 printf("nstatus == 0 while waiting for condone\n");
364 if (i
== FPGA_TIMEOUT_CNT
)
370 /* Ensure the FPGA entering user mode */
371 static int fpgamgr_program_poll_usermode(void)
376 if (fpgamgr_dclkcnt_set(0xf))
379 ret
= wait_for_user_mode();
381 printf("%s: Failed to enter user mode with ", __func__
);
382 printf("error code %d\n", ret
);
388 * Stop DATA path and Dclk
389 * EN_CFG_CTRL and EN_CFG_DATA = 0
391 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
392 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
393 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
398 * S2F_NENABLE_CONFIG = 1
399 * S2F_NENABLE_NCONFIG = 1
401 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
402 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK
);
403 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
404 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK
);
406 /* Disable chip select S2F_NCE = 1 */
407 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
408 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
414 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
415 if (((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) !=
416 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) ||
417 ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) !=
418 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) ||
419 ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
) !=
420 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
))
426 int fpgamgr_program_finish(void)
428 /* Ensure the FPGA entering config done */
429 int status
= fpgamgr_program_poll_cd();
432 printf("FPGA: Poll CD failed with error code %d\n", status
);
437 /* Ensure the FPGA entering user mode */
438 status
= fpgamgr_program_poll_usermode();
440 printf("FPGA: Poll usermode failed with error code %d\n",
445 printf("Full Configuration Succeeded.\n");
451 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
452 * Return 0 for sucess, non-zero for error.
454 int socfpga_load(Altera_desc
*desc
, const void *rbf_data
, size_t rbf_size
)
458 /* disable all signals from hps peripheral controller to fpga */
459 writel(0, &system_manager_base
->fpgaintf_en_global
);
461 /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
462 socfpga_bridges_reset();
464 /* Initialize the FPGA Manager */
465 status
= fpgamgr_program_init((u32
*)rbf_data
, rbf_size
);
469 /* Write the RBF data to FPGA Manager */
470 fpgamgr_program_write(rbf_data
, rbf_size
);
472 return fpgamgr_program_finish();