3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <common.h> /* core U-Boot definitions */
9 #include <spartan2.h> /* Spartan-II device family */
11 /* Define FPGA_DEBUG to get debug printf's */
13 #define PRINTF(fmt,args...) printf (fmt ,##args)
15 #define PRINTF(fmt,args...)
18 #undef CONFIG_SYS_FPGA_CHECK_BUSY
19 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
21 /* Note: The assumption is that we cannot possibly run fast enough to
22 * overrun the device (the Slave Parallel mode can free run at 50MHz).
23 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
24 * the board config file to slow things down.
26 #ifndef CONFIG_FPGA_DELAY
27 #define CONFIG_FPGA_DELAY()
30 #ifndef CONFIG_SYS_FPGA_WAIT
31 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
34 static int spartan2_sp_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
35 static int spartan2_sp_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
36 /* static int spartan2_sp_info(xilinx_desc *desc ); */
38 static int spartan2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
39 static int spartan2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
40 /* static int spartan2_ss_info(xilinx_desc *desc ); */
42 /* ------------------------------------------------------------------------- */
43 /* Spartan-II Generic Implementation */
44 static int spartan2_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
,
45 bitstream_type bstype
)
47 int ret_val
= FPGA_FAIL
;
49 switch (desc
->iface
) {
51 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
52 ret_val
= spartan2_ss_load(desc
, buf
, bsize
);
56 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
57 ret_val
= spartan2_sp_load(desc
, buf
, bsize
);
61 printf ("%s: Unsupported interface type, %d\n",
62 __FUNCTION__
, desc
->iface
);
68 static int spartan2_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
70 int ret_val
= FPGA_FAIL
;
72 switch (desc
->iface
) {
74 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
75 ret_val
= spartan2_ss_dump(desc
, buf
, bsize
);
79 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
80 ret_val
= spartan2_sp_dump(desc
, buf
, bsize
);
84 printf ("%s: Unsupported interface type, %d\n",
85 __FUNCTION__
, desc
->iface
);
91 static int spartan2_info(xilinx_desc
*desc
)
97 /* ------------------------------------------------------------------------- */
98 /* Spartan-II Slave Parallel Generic Implementation */
100 static int spartan2_sp_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
102 int ret_val
= FPGA_FAIL
; /* assume the worst */
103 xilinx_spartan2_slave_parallel_fns
*fn
= desc
->iface_fns
;
105 PRINTF ("%s: start with interface functions @ 0x%p\n",
109 size_t bytecount
= 0;
110 unsigned char *data
= (unsigned char *) buf
;
111 int cookie
= desc
->cookie
; /* make a local copy */
112 unsigned long ts
; /* timestamp */
114 PRINTF ("%s: Function Table:\n"
125 "write data:\t0x%p\n"
129 __FUNCTION__
, &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
,
130 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
, fn
->busy
,
131 fn
->abort
, fn
->post
);
134 * This code is designed to emulate the "Express Style"
135 * Continuous Data Loading in Slave Parallel Mode for
136 * the Spartan-II Family.
138 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
139 printf ("Loading FPGA Device %d...\n", cookie
);
142 * Run the pre configuration function if there is one.
148 /* Establish the initial state */
149 (*fn
->pgm
) (true, true, cookie
); /* Assert the program, commit */
151 /* Get ready for the burn */
152 CONFIG_FPGA_DELAY ();
153 (*fn
->pgm
) (false, true, cookie
); /* Deassert the program, commit */
155 ts
= get_timer (0); /* get current time */
156 /* Now wait for INIT and BUSY to go high */
158 CONFIG_FPGA_DELAY ();
159 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
160 puts ("** Timeout waiting for INIT to clear.\n");
161 (*fn
->abort
) (cookie
); /* abort the burn */
164 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
166 (*fn
->wr
) (true, true, cookie
); /* Assert write, commit */
167 (*fn
->cs
) (true, true, cookie
); /* Assert chip select, commit */
168 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
171 while (bytecount
< bsize
) {
172 /* XXX - do we check for an Ctrl-C press in here ??? */
173 /* XXX - Check the error bit? */
175 (*fn
->wdata
) (data
[bytecount
++], true, cookie
); /* write the data */
176 CONFIG_FPGA_DELAY ();
177 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
178 CONFIG_FPGA_DELAY ();
179 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
181 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
182 ts
= get_timer (0); /* get current time */
183 while ((*fn
->busy
) (cookie
)) {
184 /* XXX - we should have a check in here somewhere to
185 * make sure we aren't busy forever... */
187 CONFIG_FPGA_DELAY ();
188 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
189 CONFIG_FPGA_DELAY ();
190 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
192 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
193 puts ("** Timeout waiting for BUSY to clear.\n");
194 (*fn
->abort
) (cookie
); /* abort the burn */
200 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
201 if (bytecount
% (bsize
/ 40) == 0)
202 putc ('.'); /* let them know we are alive */
206 CONFIG_FPGA_DELAY ();
207 (*fn
->cs
) (false, true, cookie
); /* Deassert the chip select */
208 (*fn
->wr
) (false, true, cookie
); /* Deassert the write pin */
210 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
211 putc ('\n'); /* terminate the dotted line */
214 /* now check for done signal */
215 ts
= get_timer (0); /* get current time */
216 ret_val
= FPGA_SUCCESS
;
217 while ((*fn
->done
) (cookie
) == FPGA_FAIL
) {
219 CONFIG_FPGA_DELAY ();
220 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
221 CONFIG_FPGA_DELAY ();
222 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
224 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
225 puts ("** Timeout waiting for DONE to clear.\n");
226 (*fn
->abort
) (cookie
); /* abort the burn */
233 * Run the post configuration function if there is one.
236 (*fn
->post
) (cookie
);
238 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
239 if (ret_val
== FPGA_SUCCESS
)
246 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
252 static int spartan2_sp_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
254 int ret_val
= FPGA_FAIL
; /* assume the worst */
255 xilinx_spartan2_slave_parallel_fns
*fn
= desc
->iface_fns
;
258 unsigned char *data
= (unsigned char *) buf
;
259 size_t bytecount
= 0;
260 int cookie
= desc
->cookie
; /* make a local copy */
262 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
264 (*fn
->cs
) (true, true, cookie
); /* Assert chip select, commit */
265 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
268 while (bytecount
< bsize
) {
269 /* XXX - do we check for an Ctrl-C press in here ??? */
271 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
272 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
273 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
); /* read the data */
274 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
275 if (bytecount
% (bsize
/ 40) == 0)
276 putc ('.'); /* let them know we are alive */
280 (*fn
->cs
) (false, false, cookie
); /* Deassert the chip select */
281 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
282 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
284 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
285 putc ('\n'); /* terminate the dotted line */
289 /* XXX - checksum the data? */
291 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
298 /* ------------------------------------------------------------------------- */
300 static int spartan2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
302 int ret_val
= FPGA_FAIL
; /* assume the worst */
303 xilinx_spartan2_slave_serial_fns
*fn
= desc
->iface_fns
;
307 PRINTF ("%s: start with interface functions @ 0x%p\n",
311 size_t bytecount
= 0;
312 unsigned char *data
= (unsigned char *) buf
;
313 int cookie
= desc
->cookie
; /* make a local copy */
314 unsigned long ts
; /* timestamp */
316 PRINTF ("%s: Function Table:\n"
324 __FUNCTION__
, &fn
, fn
, fn
->pgm
, fn
->init
,
325 fn
->clk
, fn
->wr
, fn
->done
);
326 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
327 printf ("Loading FPGA Device %d...\n", cookie
);
331 * Run the pre configuration function if there is one.
337 /* Establish the initial state */
338 (*fn
->pgm
) (true, true, cookie
); /* Assert the program, commit */
340 /* Wait for INIT state (init low) */
341 ts
= get_timer (0); /* get current time */
343 CONFIG_FPGA_DELAY ();
344 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
345 puts ("** Timeout waiting for INIT to start.\n");
348 } while (!(*fn
->init
) (cookie
));
350 /* Get ready for the burn */
351 CONFIG_FPGA_DELAY ();
352 (*fn
->pgm
) (false, true, cookie
); /* Deassert the program, commit */
354 ts
= get_timer (0); /* get current time */
355 /* Now wait for INIT to go high */
357 CONFIG_FPGA_DELAY ();
358 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
359 puts ("** Timeout waiting for INIT to clear.\n");
362 } while ((*fn
->init
) (cookie
));
365 while (bytecount
< bsize
) {
367 /* Xilinx detects an error if INIT goes low (active)
368 while DONE is low (inactive) */
369 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
370 puts ("** CRC error during FPGA load.\n");
373 val
= data
[bytecount
++];
376 /* Deassert the clock */
377 (*fn
->clk
) (false, true, cookie
);
378 CONFIG_FPGA_DELAY ();
380 (*fn
->wr
) ((val
& 0x80), true, cookie
);
381 CONFIG_FPGA_DELAY ();
382 /* Assert the clock */
383 (*fn
->clk
) (true, true, cookie
);
384 CONFIG_FPGA_DELAY ();
389 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
390 if (bytecount
% (bsize
/ 40) == 0)
391 putc ('.'); /* let them know we are alive */
395 CONFIG_FPGA_DELAY ();
397 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
398 putc ('\n'); /* terminate the dotted line */
401 /* now check for done signal */
402 ts
= get_timer (0); /* get current time */
403 ret_val
= FPGA_SUCCESS
;
404 (*fn
->wr
) (true, true, cookie
);
406 while (! (*fn
->done
) (cookie
)) {
408 CONFIG_FPGA_DELAY ();
409 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
410 CONFIG_FPGA_DELAY ();
411 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
415 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
416 puts ("** Timeout waiting for DONE to clear.\n");
421 putc ('\n'); /* terminate the dotted line */
424 * Run the post configuration function if there is one.
427 (*fn
->post
) (cookie
);
429 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
430 if (ret_val
== FPGA_SUCCESS
)
437 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
443 static int spartan2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
445 /* Readback is only available through the Slave Parallel and */
446 /* boundary-scan interfaces. */
447 printf ("%s: Slave Serial Dumping is unavailable\n",
452 struct xilinx_fpga_op spartan2_op
= {
453 .load
= spartan2_load
,
454 .dump
= spartan2_dump
,
455 .info
= spartan2_info
,