3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <common.h> /* core U-Boot definitions */
26 #include <spartan2.h> /* Spartan-II device family */
28 /* Define FPGA_DEBUG to get debug printf's */
30 #define PRINTF(fmt,args...) printf (fmt ,##args)
32 #define PRINTF(fmt,args...)
35 #undef CONFIG_SYS_FPGA_CHECK_BUSY
36 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
38 /* Note: The assumption is that we cannot possibly run fast enough to
39 * overrun the device (the Slave Parallel mode can free run at 50MHz).
40 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
41 * the board config file to slow things down.
43 #ifndef CONFIG_FPGA_DELAY
44 #define CONFIG_FPGA_DELAY()
47 #ifndef CONFIG_SYS_FPGA_WAIT
48 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
51 static int Spartan2_sp_load( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
52 static int Spartan2_sp_dump( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
53 /* static int Spartan2_sp_info( Xilinx_desc *desc ); */
55 static int Spartan2_ss_load( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
56 static int Spartan2_ss_dump( Xilinx_desc
*desc
, void *buf
, size_t bsize
);
57 /* static int Spartan2_ss_info( Xilinx_desc *desc ); */
59 /* ------------------------------------------------------------------------- */
60 /* Spartan-II Generic Implementation */
61 int Spartan2_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
63 int ret_val
= FPGA_FAIL
;
65 switch (desc
->iface
) {
67 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
68 ret_val
= Spartan2_ss_load (desc
, buf
, bsize
);
72 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
73 ret_val
= Spartan2_sp_load (desc
, buf
, bsize
);
77 printf ("%s: Unsupported interface type, %d\n",
78 __FUNCTION__
, desc
->iface
);
84 int Spartan2_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
86 int ret_val
= FPGA_FAIL
;
88 switch (desc
->iface
) {
90 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
91 ret_val
= Spartan2_ss_dump (desc
, buf
, bsize
);
95 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
96 ret_val
= Spartan2_sp_dump (desc
, buf
, bsize
);
100 printf ("%s: Unsupported interface type, %d\n",
101 __FUNCTION__
, desc
->iface
);
107 int Spartan2_info( Xilinx_desc
*desc
)
113 /* ------------------------------------------------------------------------- */
114 /* Spartan-II Slave Parallel Generic Implementation */
116 static int Spartan2_sp_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
118 int ret_val
= FPGA_FAIL
; /* assume the worst */
119 Xilinx_Spartan2_Slave_Parallel_fns
*fn
= desc
->iface_fns
;
121 PRINTF ("%s: start with interface functions @ 0x%p\n",
125 size_t bytecount
= 0;
126 unsigned char *data
= (unsigned char *) buf
;
127 int cookie
= desc
->cookie
; /* make a local copy */
128 unsigned long ts
; /* timestamp */
130 PRINTF ("%s: Function Table:\n"
141 "write data:\t0x%p\n"
145 __FUNCTION__
, &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
,
146 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
, fn
->busy
,
147 fn
->abort
, fn
->post
);
150 * This code is designed to emulate the "Express Style"
151 * Continuous Data Loading in Slave Parallel Mode for
152 * the Spartan-II Family.
154 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
155 printf ("Loading FPGA Device %d...\n", cookie
);
158 * Run the pre configuration function if there is one.
164 /* Establish the initial state */
165 (*fn
->pgm
) (TRUE
, TRUE
, cookie
); /* Assert the program, commit */
167 /* Get ready for the burn */
168 CONFIG_FPGA_DELAY ();
169 (*fn
->pgm
) (FALSE
, TRUE
, cookie
); /* Deassert the program, commit */
171 ts
= get_timer (0); /* get current time */
172 /* Now wait for INIT and BUSY to go high */
174 CONFIG_FPGA_DELAY ();
175 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
176 puts ("** Timeout waiting for INIT to clear.\n");
177 (*fn
->abort
) (cookie
); /* abort the burn */
180 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
182 (*fn
->wr
) (TRUE
, TRUE
, cookie
); /* Assert write, commit */
183 (*fn
->cs
) (TRUE
, TRUE
, cookie
); /* Assert chip select, commit */
184 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
187 while (bytecount
< bsize
) {
188 /* XXX - do we check for an Ctrl-C press in here ??? */
189 /* XXX - Check the error bit? */
191 (*fn
->wdata
) (data
[bytecount
++], TRUE
, cookie
); /* write the data */
192 CONFIG_FPGA_DELAY ();
193 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
194 CONFIG_FPGA_DELAY ();
195 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
197 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
198 ts
= get_timer (0); /* get current time */
199 while ((*fn
->busy
) (cookie
)) {
200 /* XXX - we should have a check in here somewhere to
201 * make sure we aren't busy forever... */
203 CONFIG_FPGA_DELAY ();
204 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
205 CONFIG_FPGA_DELAY ();
206 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
208 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
209 puts ("** Timeout waiting for BUSY to clear.\n");
210 (*fn
->abort
) (cookie
); /* abort the burn */
216 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
217 if (bytecount
% (bsize
/ 40) == 0)
218 putc ('.'); /* let them know we are alive */
222 CONFIG_FPGA_DELAY ();
223 (*fn
->cs
) (FALSE
, TRUE
, cookie
); /* Deassert the chip select */
224 (*fn
->wr
) (FALSE
, TRUE
, cookie
); /* Deassert the write pin */
226 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
227 putc ('\n'); /* terminate the dotted line */
230 /* now check for done signal */
231 ts
= get_timer (0); /* get current time */
232 ret_val
= FPGA_SUCCESS
;
233 while ((*fn
->done
) (cookie
) == FPGA_FAIL
) {
235 CONFIG_FPGA_DELAY ();
236 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
237 CONFIG_FPGA_DELAY ();
238 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
240 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
241 puts ("** Timeout waiting for DONE to clear.\n");
242 (*fn
->abort
) (cookie
); /* abort the burn */
249 * Run the post configuration function if there is one.
252 (*fn
->post
) (cookie
);
254 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
255 if (ret_val
== FPGA_SUCCESS
)
262 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
268 static int Spartan2_sp_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
270 int ret_val
= FPGA_FAIL
; /* assume the worst */
271 Xilinx_Spartan2_Slave_Parallel_fns
*fn
= desc
->iface_fns
;
274 unsigned char *data
= (unsigned char *) buf
;
275 size_t bytecount
= 0;
276 int cookie
= desc
->cookie
; /* make a local copy */
278 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
280 (*fn
->cs
) (TRUE
, TRUE
, cookie
); /* Assert chip select, commit */
281 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
284 while (bytecount
< bsize
) {
285 /* XXX - do we check for an Ctrl-C press in here ??? */
287 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
288 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
289 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
); /* read the data */
290 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
291 if (bytecount
% (bsize
/ 40) == 0)
292 putc ('.'); /* let them know we are alive */
296 (*fn
->cs
) (FALSE
, FALSE
, cookie
); /* Deassert the chip select */
297 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
298 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
300 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
301 putc ('\n'); /* terminate the dotted line */
305 /* XXX - checksum the data? */
307 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
314 /* ------------------------------------------------------------------------- */
316 static int Spartan2_ss_load (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
318 int ret_val
= FPGA_FAIL
; /* assume the worst */
319 Xilinx_Spartan2_Slave_Serial_fns
*fn
= desc
->iface_fns
;
323 PRINTF ("%s: start with interface functions @ 0x%p\n",
327 size_t bytecount
= 0;
328 unsigned char *data
= (unsigned char *) buf
;
329 int cookie
= desc
->cookie
; /* make a local copy */
330 unsigned long ts
; /* timestamp */
332 PRINTF ("%s: Function Table:\n"
340 __FUNCTION__
, &fn
, fn
, fn
->pgm
, fn
->init
,
341 fn
->clk
, fn
->wr
, fn
->done
);
342 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
343 printf ("Loading FPGA Device %d...\n", cookie
);
347 * Run the pre configuration function if there is one.
353 /* Establish the initial state */
354 (*fn
->pgm
) (TRUE
, TRUE
, cookie
); /* Assert the program, commit */
356 /* Wait for INIT state (init low) */
357 ts
= get_timer (0); /* get current time */
359 CONFIG_FPGA_DELAY ();
360 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
361 puts ("** Timeout waiting for INIT to start.\n");
364 } while (!(*fn
->init
) (cookie
));
366 /* Get ready for the burn */
367 CONFIG_FPGA_DELAY ();
368 (*fn
->pgm
) (FALSE
, TRUE
, cookie
); /* Deassert the program, commit */
370 ts
= get_timer (0); /* get current time */
371 /* Now wait for INIT to go high */
373 CONFIG_FPGA_DELAY ();
374 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
375 puts ("** Timeout waiting for INIT to clear.\n");
378 } while ((*fn
->init
) (cookie
));
381 while (bytecount
< bsize
) {
383 /* Xilinx detects an error if INIT goes low (active)
384 while DONE is low (inactive) */
385 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
386 puts ("** CRC error during FPGA load.\n");
389 val
= data
[bytecount
++];
392 /* Deassert the clock */
393 (*fn
->clk
) (FALSE
, TRUE
, cookie
);
394 CONFIG_FPGA_DELAY ();
396 (*fn
->wr
) ((val
& 0x80), TRUE
, cookie
);
397 CONFIG_FPGA_DELAY ();
398 /* Assert the clock */
399 (*fn
->clk
) (TRUE
, TRUE
, cookie
);
400 CONFIG_FPGA_DELAY ();
405 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
406 if (bytecount
% (bsize
/ 40) == 0)
407 putc ('.'); /* let them know we are alive */
411 CONFIG_FPGA_DELAY ();
413 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
414 putc ('\n'); /* terminate the dotted line */
417 /* now check for done signal */
418 ts
= get_timer (0); /* get current time */
419 ret_val
= FPGA_SUCCESS
;
420 (*fn
->wr
) (TRUE
, TRUE
, cookie
);
422 while (! (*fn
->done
) (cookie
)) {
424 CONFIG_FPGA_DELAY ();
425 (*fn
->clk
) (FALSE
, TRUE
, cookie
); /* Deassert the clock pin */
426 CONFIG_FPGA_DELAY ();
427 (*fn
->clk
) (TRUE
, TRUE
, cookie
); /* Assert the clock pin */
431 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
432 puts ("** Timeout waiting for DONE to clear.\n");
437 putc ('\n'); /* terminate the dotted line */
440 * Run the post configuration function if there is one.
443 (*fn
->post
) (cookie
);
445 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
446 if (ret_val
== FPGA_SUCCESS
)
453 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
459 static int Spartan2_ss_dump (Xilinx_desc
* desc
, void *buf
, size_t bsize
)
461 /* Readback is only available through the Slave Parallel and */
462 /* boundary-scan interfaces. */
463 printf ("%s: Slave Serial Dumping is unavailable\n",