3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Configuration support for Xilinx Spartan3 devices. Based
10 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
13 #include <common.h> /* core U-Boot definitions */
14 #include <spartan3.h> /* Spartan-II device family */
16 /* Define FPGA_DEBUG to get debug printf's */
18 #define PRINTF(fmt,args...) printf (fmt ,##args)
20 #define PRINTF(fmt,args...)
23 #undef CONFIG_SYS_FPGA_CHECK_BUSY
25 /* Note: The assumption is that we cannot possibly run fast enough to
26 * overrun the device (the Slave Parallel mode can free run at 50MHz).
27 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
28 * the board config file to slow things down.
30 #ifndef CONFIG_FPGA_DELAY
31 #define CONFIG_FPGA_DELAY()
34 #ifndef CONFIG_SYS_FPGA_WAIT
35 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
38 static int spartan3_sp_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
39 static int spartan3_sp_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
40 /* static int spartan3_sp_info(xilinx_desc *desc ); */
42 static int spartan3_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
43 static int spartan3_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
44 /* static int spartan3_ss_info(xilinx_desc *desc); */
46 /* ------------------------------------------------------------------------- */
47 /* Spartan-II Generic Implementation */
48 static int spartan3_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
,
49 bitstream_type bstype
)
51 int ret_val
= FPGA_FAIL
;
53 switch (desc
->iface
) {
55 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
56 ret_val
= spartan3_ss_load(desc
, buf
, bsize
);
60 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
61 ret_val
= spartan3_sp_load(desc
, buf
, bsize
);
65 printf ("%s: Unsupported interface type, %d\n",
66 __FUNCTION__
, desc
->iface
);
72 static int spartan3_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
74 int ret_val
= FPGA_FAIL
;
76 switch (desc
->iface
) {
78 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
79 ret_val
= spartan3_ss_dump(desc
, buf
, bsize
);
83 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
84 ret_val
= spartan3_sp_dump(desc
, buf
, bsize
);
88 printf ("%s: Unsupported interface type, %d\n",
89 __FUNCTION__
, desc
->iface
);
95 static int spartan3_info(xilinx_desc
*desc
)
101 /* ------------------------------------------------------------------------- */
102 /* Spartan-II Slave Parallel Generic Implementation */
104 static int spartan3_sp_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
106 int ret_val
= FPGA_FAIL
; /* assume the worst */
107 xilinx_spartan3_slave_parallel_fns
*fn
= desc
->iface_fns
;
109 PRINTF ("%s: start with interface functions @ 0x%p\n",
113 size_t bytecount
= 0;
114 unsigned char *data
= (unsigned char *) buf
;
115 int cookie
= desc
->cookie
; /* make a local copy */
116 unsigned long ts
; /* timestamp */
118 PRINTF ("%s: Function Table:\n"
129 "write data:\t0x%p\n"
133 __FUNCTION__
, &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
,
134 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
, fn
->busy
,
135 fn
->abort
, fn
->post
);
138 * This code is designed to emulate the "Express Style"
139 * Continuous Data Loading in Slave Parallel Mode for
140 * the Spartan-II Family.
142 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
143 printf ("Loading FPGA Device %d...\n", cookie
);
146 * Run the pre configuration function if there is one.
152 /* Establish the initial state */
153 (*fn
->pgm
) (true, true, cookie
); /* Assert the program, commit */
155 /* Get ready for the burn */
156 CONFIG_FPGA_DELAY ();
157 (*fn
->pgm
) (false, true, cookie
); /* Deassert the program, commit */
159 ts
= get_timer (0); /* get current time */
160 /* Now wait for INIT and BUSY to go high */
162 CONFIG_FPGA_DELAY ();
163 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
164 puts ("** Timeout waiting for INIT to clear.\n");
165 (*fn
->abort
) (cookie
); /* abort the burn */
168 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
170 (*fn
->wr
) (true, true, cookie
); /* Assert write, commit */
171 (*fn
->cs
) (true, true, cookie
); /* Assert chip select, commit */
172 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
175 while (bytecount
< bsize
) {
176 /* XXX - do we check for an Ctrl-C press in here ??? */
177 /* XXX - Check the error bit? */
179 (*fn
->wdata
) (data
[bytecount
++], true, cookie
); /* write the data */
180 CONFIG_FPGA_DELAY ();
181 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
182 CONFIG_FPGA_DELAY ();
183 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
185 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
186 ts
= get_timer (0); /* get current time */
187 while ((*fn
->busy
) (cookie
)) {
188 /* XXX - we should have a check in here somewhere to
189 * make sure we aren't busy forever... */
191 CONFIG_FPGA_DELAY ();
192 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
193 CONFIG_FPGA_DELAY ();
194 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
196 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
197 puts ("** Timeout waiting for BUSY to clear.\n");
198 (*fn
->abort
) (cookie
); /* abort the burn */
204 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
205 if (bytecount
% (bsize
/ 40) == 0)
206 putc ('.'); /* let them know we are alive */
210 CONFIG_FPGA_DELAY ();
211 (*fn
->cs
) (false, true, cookie
); /* Deassert the chip select */
212 (*fn
->wr
) (false, true, cookie
); /* Deassert the write pin */
214 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
215 putc ('\n'); /* terminate the dotted line */
218 /* now check for done signal */
219 ts
= get_timer (0); /* get current time */
220 ret_val
= FPGA_SUCCESS
;
221 while ((*fn
->done
) (cookie
) == FPGA_FAIL
) {
222 /* XXX - we should have a check in here somewhere to
223 * make sure we aren't busy forever... */
225 CONFIG_FPGA_DELAY ();
226 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
227 CONFIG_FPGA_DELAY ();
228 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
230 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
231 puts ("** Timeout waiting for DONE to clear.\n");
232 (*fn
->abort
) (cookie
); /* abort the burn */
239 * Run the post configuration function if there is one.
242 (*fn
->post
) (cookie
);
244 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
245 if (ret_val
== FPGA_SUCCESS
)
252 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
258 static int spartan3_sp_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
260 int ret_val
= FPGA_FAIL
; /* assume the worst */
261 xilinx_spartan3_slave_parallel_fns
*fn
= desc
->iface_fns
;
264 unsigned char *data
= (unsigned char *) buf
;
265 size_t bytecount
= 0;
266 int cookie
= desc
->cookie
; /* make a local copy */
268 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
270 (*fn
->cs
) (true, true, cookie
); /* Assert chip select, commit */
271 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
274 while (bytecount
< bsize
) {
275 /* XXX - do we check for an Ctrl-C press in here ??? */
277 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
278 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
279 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
); /* read the data */
280 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
281 if (bytecount
% (bsize
/ 40) == 0)
282 putc ('.'); /* let them know we are alive */
286 (*fn
->cs
) (false, false, cookie
); /* Deassert the chip select */
287 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
288 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
290 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
291 putc ('\n'); /* terminate the dotted line */
295 /* XXX - checksum the data? */
297 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
304 /* ------------------------------------------------------------------------- */
306 static int spartan3_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
308 int ret_val
= FPGA_FAIL
; /* assume the worst */
309 xilinx_spartan3_slave_serial_fns
*fn
= desc
->iface_fns
;
313 PRINTF ("%s: start with interface functions @ 0x%p\n",
317 size_t bytecount
= 0;
318 unsigned char *data
= (unsigned char *) buf
;
319 int cookie
= desc
->cookie
; /* make a local copy */
320 unsigned long ts
; /* timestamp */
322 PRINTF ("%s: Function Table:\n"
330 __FUNCTION__
, &fn
, fn
, fn
->pgm
, fn
->init
,
331 fn
->clk
, fn
->wr
, fn
->done
);
332 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
333 printf ("Loading FPGA Device %d...\n", cookie
);
337 * Run the pre configuration function if there is one.
343 /* Establish the initial state */
344 (*fn
->pgm
) (true, true, cookie
); /* Assert the program, commit */
346 /* Wait for INIT state (init low) */
347 ts
= get_timer (0); /* get current time */
349 CONFIG_FPGA_DELAY ();
350 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
351 puts ("** Timeout waiting for INIT to start.\n");
353 (*fn
->abort
) (cookie
);
356 } while (!(*fn
->init
) (cookie
));
358 /* Get ready for the burn */
359 CONFIG_FPGA_DELAY ();
360 (*fn
->pgm
) (false, true, cookie
); /* Deassert the program, commit */
362 ts
= get_timer (0); /* get current time */
363 /* Now wait for INIT to go high */
365 CONFIG_FPGA_DELAY ();
366 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
367 puts ("** Timeout waiting for INIT to clear.\n");
369 (*fn
->abort
) (cookie
);
372 } while ((*fn
->init
) (cookie
));
376 (*fn
->bwr
) (data
, bsize
, true, cookie
);
378 while (bytecount
< bsize
) {
380 /* Xilinx detects an error if INIT goes low (active)
381 while DONE is low (inactive) */
382 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
383 puts ("** CRC error during FPGA load.\n");
385 (*fn
->abort
) (cookie
);
388 val
= data
[bytecount
++];
391 /* Deassert the clock */
392 (*fn
->clk
) (false, true, cookie
);
393 CONFIG_FPGA_DELAY ();
395 (*fn
->wr
) ((val
& 0x80), true, cookie
);
396 CONFIG_FPGA_DELAY ();
397 /* Assert the clock */
398 (*fn
->clk
) (true, true, cookie
);
399 CONFIG_FPGA_DELAY ();
404 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
405 if (bytecount
% (bsize
/ 40) == 0)
406 putc ('.'); /* let them know we are alive */
411 CONFIG_FPGA_DELAY ();
413 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
414 putc ('\n'); /* terminate the dotted line */
417 /* now check for done signal */
418 ts
= get_timer (0); /* get current time */
419 ret_val
= FPGA_SUCCESS
;
420 (*fn
->wr
) (true, true, cookie
);
422 while (! (*fn
->done
) (cookie
)) {
423 /* XXX - we should have a check in here somewhere to
424 * make sure we aren't busy forever... */
426 CONFIG_FPGA_DELAY ();
427 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
428 CONFIG_FPGA_DELAY ();
429 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
433 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
434 puts ("** Timeout waiting for DONE to clear.\n");
439 putc ('\n'); /* terminate the dotted line */
442 * Run the post configuration function if there is one.
445 (*fn
->post
) (cookie
);
447 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
448 if (ret_val
== FPGA_SUCCESS
)
455 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
461 static int spartan3_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
463 /* Readback is only available through the Slave Parallel and */
464 /* boundary-scan interfaces. */
465 printf ("%s: Slave Serial Dumping is unavailable\n",
470 struct xilinx_fpga_op spartan3_op
= {
471 .load
= spartan3_load
,
472 .dump
= spartan3_dump
,
473 .info
= spartan3_info
,