3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com
6 * SPDX-License-Identifier: GPL-2.0+
10 * Configuration support for Xilinx Virtex2 devices. Based
11 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
22 #define PRINTF(fmt,args...) printf (fmt ,##args)
24 #define PRINTF(fmt,args...)
28 * If the SelectMap interface can be overrun by the processor, define
29 * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
30 * file and add board-specific support for checking BUSY status. By default,
31 * assume that the SelectMap interface cannot be overrun.
33 #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
34 #undef CONFIG_SYS_FPGA_CHECK_BUSY
37 #ifndef CONFIG_FPGA_DELAY
38 #define CONFIG_FPGA_DELAY()
41 #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
42 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
46 * Don't allow config cycle to be interrupted
48 #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
49 #undef CONFIG_SYS_FPGA_CHECK_CTRLC
53 * Check for errors during configuration by default
55 #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
56 #define CONFIG_SYS_FPGA_CHECK_ERROR
60 * The default timeout in mS for INIT_B to deassert after PROG_B has
61 * been deasserted. Per the latest Virtex II Handbook (page 347), the
62 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
63 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
64 * which yields 11.44 mS. So let's make it bigger in order to handle
65 * an XC2V1000, if anyone can ever get ahold of one.
67 #ifndef CONFIG_SYS_FPGA_WAIT_INIT
68 #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
72 * The default timeout for waiting for BUSY to deassert during configuration.
73 * This is normally not necessary since for most reasonable configuration
74 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
76 #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
77 #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
80 /* Default timeout for waiting for FPGA to enter operational mode after
81 * configuration data has been written.
83 #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
84 #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
87 static int virtex2_ssm_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
88 static int virtex2_ssm_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
90 static int virtex2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
91 static int virtex2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
93 static int virtex2_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
95 int ret_val
= FPGA_FAIL
;
97 switch (desc
->iface
) {
99 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
100 ret_val
= virtex2_ss_load(desc
, buf
, bsize
);
103 case slave_selectmap
:
104 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
105 ret_val
= virtex2_ssm_load(desc
, buf
, bsize
);
109 printf ("%s: Unsupported interface type, %d\n",
110 __FUNCTION__
, desc
->iface
);
115 static int virtex2_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
117 int ret_val
= FPGA_FAIL
;
119 switch (desc
->iface
) {
121 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
122 ret_val
= virtex2_ss_dump(desc
, buf
, bsize
);
126 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
127 ret_val
= virtex2_ssm_dump(desc
, buf
, bsize
);
131 printf ("%s: Unsupported interface type, %d\n",
132 __FUNCTION__
, desc
->iface
);
137 static int virtex2_info(xilinx_desc
*desc
)
143 * Virtex-II Slave SelectMap configuration loader. Configuration via
144 * SelectMap is as follows:
145 * 1. Set the FPGA's PROG_B line low.
146 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
147 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
148 * this process, a configuration error (most likely CRC failure) has
149 * ocurred. At this point a status word may be read from the
150 * SelectMap interface to determine the source of the problem (You
151 * could, for instance, put this in your 'abort' function handler).
152 * 4. After all data has been written, test the state of the FPGA
153 * INIT_B and DONE lines. If both are high, configuration has
154 * succeeded. Congratulations!
156 static int virtex2_ssm_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
158 int ret_val
= FPGA_FAIL
;
159 xilinx_virtex2_slave_selectmap_fns
*fn
= desc
->iface_fns
;
161 PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
162 __FUNCTION__
, __LINE__
, fn
);
165 size_t bytecount
= 0;
166 unsigned char *data
= (unsigned char *) buf
;
167 int cookie
= desc
->cookie
;
170 /* Gotta split this one up (so the stack won't blow??) */
171 PRINTF ("%s:%d: Function Table:\n"
178 __FUNCTION__
, __LINE__
,
179 &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
);
180 PRINTF (" clock 0x%p\n"
188 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
,
189 fn
->busy
, fn
->abort
, fn
->post
);
191 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
192 printf ("Initializing FPGA Device %d...\n", cookie
);
195 * Run the pre configuration function if there is one.
202 * Assert the program line. The minimum pulse width for
203 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
204 * There is no maximum value for the pulse width. Check to make
205 * sure that INIT_B goes low after assertion of PROG_B
207 (*fn
->pgm
) (true, true, cookie
);
211 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_INIT
) {
212 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
213 " to assert.\n", __FUNCTION__
, __LINE__
,
214 CONFIG_SYS_FPGA_WAIT_INIT
);
215 (*fn
->abort
) (cookie
);
218 } while (!(*fn
->init
) (cookie
));
220 (*fn
->pgm
) (false, true, cookie
);
221 CONFIG_FPGA_DELAY ();
222 (*fn
->clk
) (true, true, cookie
);
225 * Start a timer and wait for INIT_B to go high
229 CONFIG_FPGA_DELAY ();
230 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_INIT
) {
231 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
232 " to deassert.\n", __FUNCTION__
, __LINE__
,
233 CONFIG_SYS_FPGA_WAIT_INIT
);
234 (*fn
->abort
) (cookie
);
237 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
239 (*fn
->wr
) (true, true, cookie
);
240 (*fn
->cs
) (true, true, cookie
);
245 * Load the data byte by byte
247 while (bytecount
< bsize
) {
248 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
250 (*fn
->abort
) (cookie
);
255 if ((*fn
->done
) (cookie
) == FPGA_SUCCESS
) {
256 PRINTF ("%s:%d:done went active early, bytecount = %d\n",
257 __FUNCTION__
, __LINE__
, bytecount
);
261 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
262 if ((*fn
->init
) (cookie
)) {
263 printf ("\n%s:%d: ** Error: INIT asserted during"
264 " configuration\n", __FUNCTION__
, __LINE__
);
265 printf ("%d = buffer offset, %d = buffer size\n",
267 (*fn
->abort
) (cookie
);
272 (*fn
->wdata
) (data
[bytecount
++], true, cookie
);
273 CONFIG_FPGA_DELAY ();
276 * Cycle the clock pin
278 (*fn
->clk
) (false, true, cookie
);
279 CONFIG_FPGA_DELAY ();
280 (*fn
->clk
) (true, true, cookie
);
282 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
284 while ((*fn
->busy
) (cookie
)) {
285 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_BUSY
) {
286 printf ("%s:%d: ** Timeout after %d ticks waiting for"
287 " BUSY to deassert\n",
288 __FUNCTION__
, __LINE__
, CONFIG_SYS_FPGA_WAIT_BUSY
);
289 (*fn
->abort
) (cookie
);
295 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
296 if (bytecount
% (bsize
/ 40) == 0)
302 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
304 CONFIG_FPGA_DELAY ();
305 (*fn
->cs
) (false, true, cookie
);
306 (*fn
->wr
) (false, true, cookie
);
308 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
313 * Check for successful configuration. FPGA INIT_B and DONE should
314 * both be high upon successful configuration.
317 ret_val
= FPGA_SUCCESS
;
318 while (((*fn
->done
) (cookie
) == FPGA_FAIL
) || (*fn
->init
) (cookie
)) {
319 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_CONFIG
) {
320 printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
321 "assert and INIT to deassert\n",
322 __FUNCTION__
, __LINE__
, CONFIG_SYS_FPGA_WAIT_CONFIG
);
323 (*fn
->abort
) (cookie
);
329 if (ret_val
== FPGA_SUCCESS
) {
330 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
331 printf ("Initialization of FPGA device %d complete\n", cookie
);
334 * Run the post configuration function if there is one.
337 (*fn
->post
) (cookie
);
340 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
341 printf ("** Initialization of FPGA device %d FAILED\n",
346 printf ("%s:%d: NULL Interface function table!\n",
347 __FUNCTION__
, __LINE__
);
353 * Read the FPGA configuration data
355 static int virtex2_ssm_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
357 int ret_val
= FPGA_FAIL
;
358 xilinx_virtex2_slave_selectmap_fns
*fn
= desc
->iface_fns
;
361 unsigned char *data
= (unsigned char *) buf
;
362 size_t bytecount
= 0;
363 int cookie
= desc
->cookie
;
365 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
367 (*fn
->cs
) (true, true, cookie
);
368 (*fn
->clk
) (true, true, cookie
);
370 while (bytecount
< bsize
) {
371 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
373 (*fn
->abort
) (cookie
);
378 * Cycle the clock and read the data
380 (*fn
->clk
) (false, true, cookie
);
381 (*fn
->clk
) (true, true, cookie
);
382 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
);
383 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
384 if (bytecount
% (bsize
/ 40) == 0)
390 * Deassert CS_B and cycle the clock to deselect the device.
392 (*fn
->cs
) (false, false, cookie
);
393 (*fn
->clk
) (false, true, cookie
);
394 (*fn
->clk
) (true, true, cookie
);
396 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
401 printf ("%s:%d: NULL Interface function table!\n",
402 __FUNCTION__
, __LINE__
);
407 static int virtex2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
409 printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__
);
413 static int virtex2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
415 printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__
);
419 /* vim: set ts=4 tw=78: */
421 struct xilinx_fpga_op virtex2_op
= {
422 .load
= virtex2_load
,
423 .dump
= virtex2_dump
,
424 .info
= virtex2_info
,