3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com
6 * SPDX-License-Identifier: GPL-2.0+
10 * Configuration support for Xilinx Virtex2 devices. Based
11 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
23 #define PRINTF(fmt,args...) printf (fmt ,##args)
25 #define PRINTF(fmt,args...)
29 * If the SelectMap interface can be overrun by the processor, define
30 * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
31 * file and add board-specific support for checking BUSY status. By default,
32 * assume that the SelectMap interface cannot be overrun.
34 #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
35 #undef CONFIG_SYS_FPGA_CHECK_BUSY
38 #ifndef CONFIG_FPGA_DELAY
39 #define CONFIG_FPGA_DELAY()
42 #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
43 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
47 * Don't allow config cycle to be interrupted
49 #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
50 #undef CONFIG_SYS_FPGA_CHECK_CTRLC
54 * Check for errors during configuration by default
56 #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
57 #define CONFIG_SYS_FPGA_CHECK_ERROR
61 * The default timeout in mS for INIT_B to deassert after PROG_B has
62 * been deasserted. Per the latest Virtex II Handbook (page 347), the
63 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
64 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
65 * which yields 11.44 mS. So let's make it bigger in order to handle
66 * an XC2V1000, if anyone can ever get ahold of one.
68 #ifndef CONFIG_SYS_FPGA_WAIT_INIT
69 #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
73 * The default timeout for waiting for BUSY to deassert during configuration.
74 * This is normally not necessary since for most reasonable configuration
75 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
77 #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
78 #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
81 /* Default timeout for waiting for FPGA to enter operational mode after
82 * configuration data has been written.
84 #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
85 #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
88 static int virtex2_ssm_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
89 static int virtex2_ssm_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
91 static int virtex2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
92 static int virtex2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
);
94 static int virtex2_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
,
95 bitstream_type bstype
)
97 int ret_val
= FPGA_FAIL
;
99 switch (desc
->iface
) {
101 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__
);
102 ret_val
= virtex2_ss_load(desc
, buf
, bsize
);
105 case slave_selectmap
:
106 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__
);
107 ret_val
= virtex2_ssm_load(desc
, buf
, bsize
);
111 printf ("%s: Unsupported interface type, %d\n",
112 __FUNCTION__
, desc
->iface
);
117 static int virtex2_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
119 int ret_val
= FPGA_FAIL
;
121 switch (desc
->iface
) {
123 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__
);
124 ret_val
= virtex2_ss_dump(desc
, buf
, bsize
);
128 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__
);
129 ret_val
= virtex2_ssm_dump(desc
, buf
, bsize
);
133 printf ("%s: Unsupported interface type, %d\n",
134 __FUNCTION__
, desc
->iface
);
139 static int virtex2_info(xilinx_desc
*desc
)
145 * Virtex-II Slave SelectMap configuration loader. Configuration via
146 * SelectMap is as follows:
147 * 1. Set the FPGA's PROG_B line low.
148 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
149 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
150 * this process, a configuration error (most likely CRC failure) has
151 * ocurred. At this point a status word may be read from the
152 * SelectMap interface to determine the source of the problem (You
153 * could, for instance, put this in your 'abort' function handler).
154 * 4. After all data has been written, test the state of the FPGA
155 * INIT_B and DONE lines. If both are high, configuration has
156 * succeeded. Congratulations!
158 static int virtex2_ssm_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
160 int ret_val
= FPGA_FAIL
;
161 xilinx_virtex2_slave_selectmap_fns
*fn
= desc
->iface_fns
;
163 PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
164 __FUNCTION__
, __LINE__
, fn
);
167 size_t bytecount
= 0;
168 unsigned char *data
= (unsigned char *) buf
;
169 int cookie
= desc
->cookie
;
172 /* Gotta split this one up (so the stack won't blow??) */
173 PRINTF ("%s:%d: Function Table:\n"
180 __FUNCTION__
, __LINE__
,
181 &fn
, fn
, fn
->pre
, fn
->pgm
, fn
->init
, fn
->err
);
182 PRINTF (" clock 0x%p\n"
190 fn
->clk
, fn
->cs
, fn
->wr
, fn
->rdata
, fn
->wdata
,
191 fn
->busy
, fn
->abort
, fn
->post
);
193 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
194 printf ("Initializing FPGA Device %d...\n", cookie
);
197 * Run the pre configuration function if there is one.
204 * Assert the program line. The minimum pulse width for
205 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
206 * There is no maximum value for the pulse width. Check to make
207 * sure that INIT_B goes low after assertion of PROG_B
209 (*fn
->pgm
) (true, true, cookie
);
213 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_INIT
) {
214 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
215 " to assert.\n", __FUNCTION__
, __LINE__
,
216 CONFIG_SYS_FPGA_WAIT_INIT
);
217 (*fn
->abort
) (cookie
);
220 } while (!(*fn
->init
) (cookie
));
222 (*fn
->pgm
) (false, true, cookie
);
223 CONFIG_FPGA_DELAY ();
224 (*fn
->clk
) (true, true, cookie
);
227 * Start a timer and wait for INIT_B to go high
231 CONFIG_FPGA_DELAY ();
232 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_INIT
) {
233 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
234 " to deassert.\n", __FUNCTION__
, __LINE__
,
235 CONFIG_SYS_FPGA_WAIT_INIT
);
236 (*fn
->abort
) (cookie
);
239 } while ((*fn
->init
) (cookie
) && (*fn
->busy
) (cookie
));
241 (*fn
->wr
) (true, true, cookie
);
242 (*fn
->cs
) (true, true, cookie
);
247 * Load the data byte by byte
249 while (bytecount
< bsize
) {
250 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
252 (*fn
->abort
) (cookie
);
257 if ((*fn
->done
) (cookie
) == FPGA_SUCCESS
) {
258 PRINTF ("%s:%d:done went active early, bytecount = %d\n",
259 __FUNCTION__
, __LINE__
, bytecount
);
263 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
264 if ((*fn
->init
) (cookie
)) {
265 printf ("\n%s:%d: ** Error: INIT asserted during"
266 " configuration\n", __FUNCTION__
, __LINE__
);
267 printf ("%d = buffer offset, %d = buffer size\n",
269 (*fn
->abort
) (cookie
);
274 (*fn
->wdata
) (data
[bytecount
++], true, cookie
);
275 CONFIG_FPGA_DELAY ();
278 * Cycle the clock pin
280 (*fn
->clk
) (false, true, cookie
);
281 CONFIG_FPGA_DELAY ();
282 (*fn
->clk
) (true, true, cookie
);
284 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
286 while ((*fn
->busy
) (cookie
)) {
287 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_BUSY
) {
288 printf ("%s:%d: ** Timeout after %d ticks waiting for"
289 " BUSY to deassert\n",
290 __FUNCTION__
, __LINE__
, CONFIG_SYS_FPGA_WAIT_BUSY
);
291 (*fn
->abort
) (cookie
);
297 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
298 if (bytecount
% (bsize
/ 40) == 0)
304 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
306 CONFIG_FPGA_DELAY ();
307 (*fn
->cs
) (false, true, cookie
);
308 (*fn
->wr
) (false, true, cookie
);
310 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
315 * Check for successful configuration. FPGA INIT_B and DONE should
316 * both be high upon successful configuration.
319 ret_val
= FPGA_SUCCESS
;
320 while (((*fn
->done
) (cookie
) == FPGA_FAIL
) || (*fn
->init
) (cookie
)) {
321 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT_CONFIG
) {
322 printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
323 "assert and INIT to deassert\n",
324 __FUNCTION__
, __LINE__
, CONFIG_SYS_FPGA_WAIT_CONFIG
);
325 (*fn
->abort
) (cookie
);
331 if (ret_val
== FPGA_SUCCESS
) {
332 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
333 printf ("Initialization of FPGA device %d complete\n", cookie
);
336 * Run the post configuration function if there is one.
339 (*fn
->post
) (cookie
);
342 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
343 printf ("** Initialization of FPGA device %d FAILED\n",
348 printf ("%s:%d: NULL Interface function table!\n",
349 __FUNCTION__
, __LINE__
);
355 * Read the FPGA configuration data
357 static int virtex2_ssm_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
359 int ret_val
= FPGA_FAIL
;
360 xilinx_virtex2_slave_selectmap_fns
*fn
= desc
->iface_fns
;
363 unsigned char *data
= (unsigned char *) buf
;
364 size_t bytecount
= 0;
365 int cookie
= desc
->cookie
;
367 printf ("Starting Dump of FPGA Device %d...\n", cookie
);
369 (*fn
->cs
) (true, true, cookie
);
370 (*fn
->clk
) (true, true, cookie
);
372 while (bytecount
< bsize
) {
373 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
375 (*fn
->abort
) (cookie
);
380 * Cycle the clock and read the data
382 (*fn
->clk
) (false, true, cookie
);
383 (*fn
->clk
) (true, true, cookie
);
384 (*fn
->rdata
) (&(data
[bytecount
++]), cookie
);
385 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
386 if (bytecount
% (bsize
/ 40) == 0)
392 * Deassert CS_B and cycle the clock to deselect the device.
394 (*fn
->cs
) (false, false, cookie
);
395 (*fn
->clk
) (false, true, cookie
);
396 (*fn
->clk
) (true, true, cookie
);
398 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
403 printf ("%s:%d: NULL Interface function table!\n",
404 __FUNCTION__
, __LINE__
);
409 static int virtex2_ss_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
411 printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__
);
415 static int virtex2_ss_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
417 printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__
);
421 /* vim: set ts=4 tw=78: */
423 struct xilinx_fpga_op virtex2_op
= {
424 .load
= virtex2_load
,
425 .dump
= virtex2_dump
,
426 .info
= virtex2_info
,