2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
5 * Joe Hershberger <joe.hershberger@ni.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/sizes.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/sys_proto.h>
19 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
20 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
21 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
22 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
23 #define DEVCFG_ISR_DMA_DONE 0x00002000
24 #define DEVCFG_ISR_PCFG_DONE 0x00000004
25 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
26 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
27 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
28 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
29 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
30 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
31 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
33 #ifndef CONFIG_SYS_FPGA_WAIT
34 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
37 #ifndef CONFIG_SYS_FPGA_PROG_TIME
38 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
41 static int zynq_info(xilinx_desc
*desc
)
46 #define DUMMY_WORD 0xffffffff
48 /* Xilinx binary format header */
49 static const u32 bin_format
[] = {
50 DUMMY_WORD
, /* Dummy words */
58 0x000000bb, /* Sync word */
59 0x11220044, /* Sync word */
62 0xaa995566, /* Sync word */
69 * Load the whole word from unaligned buffer
70 * Keep in your mind that it is byte loading on little-endian system
72 static u32
load_word(const void *buf
, u32 swap
)
78 if (swap
== SWAP_NO
) {
79 for (p
= 0; p
< 4; p
++) {
84 for (p
= 3; p
>= 0; p
--) {
93 static u32
check_header(const void *buf
)
97 u32
*test
= (u32
*)buf
;
99 debug("%s: Let's check bitstream header\n", __func__
);
101 /* Checking that passing bin is not a bitstream */
102 for (i
= 0; i
< ARRAY_SIZE(bin_format
); i
++) {
103 pattern
= load_word(&test
[i
], swap
);
106 * Bitstreams in binary format are swapped
107 * compare to regular bistream.
108 * Do not swap dummy word but if swap is done assume
109 * that parsing buffer is binary format
111 if ((__swab32(pattern
) != DUMMY_WORD
) &&
112 (__swab32(pattern
) == bin_format
[i
])) {
113 pattern
= __swab32(pattern
);
115 debug("%s: data swapped - let's swap\n", __func__
);
118 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__
, i
,
119 (u32
)&test
[i
], pattern
, bin_format
[i
]);
120 if (pattern
!= bin_format
[i
]) {
121 debug("%s: Bitstream is not recognized\n", __func__
);
125 debug("%s: Found bitstream header at %x %s swapinng\n", __func__
,
126 (u32
)buf
, swap
== SWAP_NO
? "without" : "with");
131 static void *check_data(u8
*buf
, size_t bsize
, u32
*swap
)
133 u32 word
, p
= 0; /* possition */
135 /* Because buf doesn't need to be aligned let's read it by chars */
136 for (p
= 0; p
< bsize
; p
++) {
137 word
= load_word(&buf
[p
], SWAP_NO
);
138 debug("%s: word %x %x/%x\n", __func__
, word
, p
, (u32
)&buf
[p
]);
140 /* Find the first bitstream dummy word */
141 if (word
== DUMMY_WORD
) {
142 debug("%s: Found dummy word at position %x/%x\n",
143 __func__
, p
, (u32
)&buf
[p
]);
144 *swap
= check_header(&buf
[p
]);
146 /* FIXME add full bitstream checking here */
150 /* Loop can be huge - support CTRL + C */
157 static int zynq_dma_transfer(u32 srcbuf
, u32 srclen
, u32 dstbuf
, u32 dstlen
)
162 /* Set up the transfer */
163 writel((u32
)srcbuf
, &devcfg_base
->dma_src_addr
);
164 writel(dstbuf
, &devcfg_base
->dma_dst_addr
);
165 writel(srclen
, &devcfg_base
->dma_src_len
);
166 writel(dstlen
, &devcfg_base
->dma_dst_len
);
168 isr_status
= readl(&devcfg_base
->int_sts
);
170 /* Polling the PCAP_INIT status for Set */
172 while (!(isr_status
& DEVCFG_ISR_DMA_DONE
)) {
173 if (isr_status
& DEVCFG_ISR_ERROR_FLAGS_MASK
) {
174 debug("%s: Error: isr = 0x%08X\n", __func__
,
176 debug("%s: Write count = 0x%08X\n", __func__
,
177 readl(&devcfg_base
->write_count
));
178 debug("%s: Read count = 0x%08X\n", __func__
,
179 readl(&devcfg_base
->read_count
));
183 if (get_timer(ts
) > CONFIG_SYS_FPGA_PROG_TIME
) {
184 printf("%s: Timeout wait for DMA to complete\n",
188 isr_status
= readl(&devcfg_base
->int_sts
);
191 debug("%s: DMA transfer is done\n", __func__
);
193 /* Clear out the DMA status */
194 writel(DEVCFG_ISR_DMA_DONE
, &devcfg_base
->int_sts
);
199 static int zynq_dma_xfer_init(bitstream_type bstype
)
201 u32 status
, control
, isr_status
;
204 /* Clear loopback bit */
205 clrbits_le32(&devcfg_base
->mctrl
, DEVCFG_MCTRL_PCAP_LPBK
);
207 if (bstype
!= BIT_PARTIAL
) {
208 zynq_slcr_devcfg_disable();
210 /* Setting PCFG_PROG_B signal to high */
211 control
= readl(&devcfg_base
->ctrl
);
212 writel(control
| DEVCFG_CTRL_PCFG_PROG_B
, &devcfg_base
->ctrl
);
213 /* Setting PCFG_PROG_B signal to low */
214 writel(control
& ~DEVCFG_CTRL_PCFG_PROG_B
, &devcfg_base
->ctrl
);
216 /* Polling the PCAP_INIT status for Reset */
218 while (readl(&devcfg_base
->status
) & DEVCFG_STATUS_PCFG_INIT
) {
219 if (get_timer(ts
) > CONFIG_SYS_FPGA_WAIT
) {
220 printf("%s: Timeout wait for INIT to clear\n",
226 /* Setting PCFG_PROG_B signal to high */
227 writel(control
| DEVCFG_CTRL_PCFG_PROG_B
, &devcfg_base
->ctrl
);
229 /* Polling the PCAP_INIT status for Set */
231 while (!(readl(&devcfg_base
->status
) &
232 DEVCFG_STATUS_PCFG_INIT
)) {
233 if (get_timer(ts
) > CONFIG_SYS_FPGA_WAIT
) {
234 printf("%s: Timeout wait for INIT to set\n",
241 isr_status
= readl(&devcfg_base
->int_sts
);
243 /* Clear it all, so if Boot ROM comes back, it can proceed */
244 writel(0xFFFFFFFF, &devcfg_base
->int_sts
);
246 if (isr_status
& DEVCFG_ISR_FATAL_ERROR_MASK
) {
247 debug("%s: Fatal errors in PCAP 0x%X\n", __func__
, isr_status
);
249 /* If RX FIFO overflow, need to flush RX FIFO first */
250 if (isr_status
& DEVCFG_ISR_RX_FIFO_OV
) {
251 writel(DEVCFG_MCTRL_RFIFO_FLUSH
, &devcfg_base
->mctrl
);
252 writel(0xFFFFFFFF, &devcfg_base
->int_sts
);
257 status
= readl(&devcfg_base
->status
);
259 debug("%s: Status = 0x%08X\n", __func__
, status
);
261 if (status
& DEVCFG_STATUS_DMA_CMD_Q_F
) {
262 debug("%s: Error: device busy\n", __func__
);
266 debug("%s: Device ready\n", __func__
);
268 if (!(status
& DEVCFG_STATUS_DMA_CMD_Q_E
)) {
269 if (!(readl(&devcfg_base
->int_sts
) & DEVCFG_ISR_DMA_DONE
)) {
270 /* Error state, transfer cannot occur */
271 debug("%s: ISR indicates error\n", __func__
);
274 /* Clear out the status */
275 writel(DEVCFG_ISR_DMA_DONE
, &devcfg_base
->int_sts
);
279 if (status
& DEVCFG_STATUS_DMA_DONE_CNT_MASK
) {
280 /* Clear the count of completed DMA transfers */
281 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK
, &devcfg_base
->status
);
287 static u32
*zynq_align_dma_buffer(u32
*buf
, u32 len
, u32 swap
)
292 if ((u32
)buf
!= ALIGN((u32
)buf
, ARCH_DMA_MINALIGN
)) {
293 new_buf
= (u32
*)ALIGN((u32
)buf
, ARCH_DMA_MINALIGN
);
296 * This might be dangerous but permits to flash if
297 * ARCH_DMA_MINALIGN is greater than header size
300 debug("%s: Aligned buffer is after buffer start\n",
302 new_buf
-= ARCH_DMA_MINALIGN
;
304 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__
,
305 (u32
)buf
, (u32
)new_buf
, swap
);
307 for (i
= 0; i
< (len
/4); i
++)
308 new_buf
[i
] = load_word(&buf
[i
], swap
);
311 } else if (swap
!= SWAP_DONE
) {
312 /* For bitstream which are aligned */
313 u32
*new_buf
= (u32
*)buf
;
315 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__
,
318 for (i
= 0; i
< (len
/4); i
++)
319 new_buf
[i
] = load_word(&buf
[i
], swap
);
325 static int zynq_validate_bitstream(xilinx_desc
*desc
, const void *buf
,
326 size_t bsize
, u32 blocksize
, u32
*swap
,
327 bitstream_type
*bstype
)
332 buf_start
= check_data((u8
*)buf
, blocksize
, swap
);
337 /* Check if data is postpone from start */
338 diff
= (u32
)buf_start
- (u32
)buf
;
340 printf("%s: Bitstream is not validated yet (diff %x)\n",
345 if ((u32
)buf
< SZ_1M
) {
346 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
351 if (zynq_dma_xfer_init(*bstype
))
357 static int zynq_load(xilinx_desc
*desc
, const void *buf
, size_t bsize
,
358 bitstream_type bstype
)
360 unsigned long ts
; /* Timestamp */
361 u32 isr_status
, swap
;
364 * send bsize inplace of blocksize as it was not a bitstream
367 if (zynq_validate_bitstream(desc
, buf
, bsize
, bsize
, &swap
,
371 buf
= zynq_align_dma_buffer((u32
*)buf
, bsize
, swap
);
373 debug("%s: Source = 0x%08X\n", __func__
, (u32
)buf
);
374 debug("%s: Size = %zu\n", __func__
, bsize
);
376 /* flush(clean & invalidate) d-cache range buf */
377 flush_dcache_range((u32
)buf
, (u32
)buf
+
378 roundup(bsize
, ARCH_DMA_MINALIGN
));
380 if (zynq_dma_transfer((u32
)buf
| 1, bsize
>> 2, 0xffffffff, 0))
383 isr_status
= readl(&devcfg_base
->int_sts
);
384 /* Check FPGA configuration completion */
386 while (!(isr_status
& DEVCFG_ISR_PCFG_DONE
)) {
387 if (get_timer(ts
) > CONFIG_SYS_FPGA_WAIT
) {
388 printf("%s: Timeout wait for FPGA to config\n",
392 isr_status
= readl(&devcfg_base
->int_sts
);
395 debug("%s: FPGA config done\n", __func__
);
397 if (bstype
!= BIT_PARTIAL
)
398 zynq_slcr_devcfg_enable();
403 #if defined(CONFIG_CMD_FPGA_LOADFS)
404 static int zynq_loadfs(xilinx_desc
*desc
, const void *buf
, size_t bsize
,
405 fpga_fs_info
*fsinfo
)
407 unsigned long ts
; /* Timestamp */
408 u32 isr_status
, swap
;
410 loff_t blocksize
, actread
;
413 char *interface
, *dev_part
, *filename
;
415 blocksize
= fsinfo
->blocksize
;
416 interface
= fsinfo
->interface
;
417 dev_part
= fsinfo
->dev_part
;
418 filename
= fsinfo
->filename
;
419 fstype
= fsinfo
->fstype
;
421 if (fs_set_blk_dev(interface
, dev_part
, fstype
))
424 if (fs_read(filename
, (u32
) buf
, pos
, blocksize
, &actread
) < 0)
427 if (zynq_validate_bitstream(desc
, buf
, bsize
, blocksize
, &swap
,
434 buf
= zynq_align_dma_buffer((u32
*)buf
, blocksize
, swap
);
436 if (zynq_dma_transfer((u32
)buf
| 1, blocksize
>> 2,
443 if (fs_set_blk_dev(interface
, dev_part
, fstype
))
446 if (bsize
> blocksize
) {
447 if (fs_read(filename
, (u32
) buf
, pos
, blocksize
, &actread
) < 0)
450 if (fs_read(filename
, (u32
) buf
, pos
, bsize
, &actread
) < 0)
453 } while (bsize
> blocksize
);
455 buf
= zynq_align_dma_buffer((u32
*)buf
, blocksize
, swap
);
457 if (zynq_dma_transfer((u32
)buf
| 1, bsize
>> 2, 0xffffffff, 0))
462 isr_status
= readl(&devcfg_base
->int_sts
);
464 /* Check FPGA configuration completion */
466 while (!(isr_status
& DEVCFG_ISR_PCFG_DONE
)) {
467 if (get_timer(ts
) > CONFIG_SYS_FPGA_WAIT
) {
468 printf("%s: Timeout wait for FPGA to config\n",
472 isr_status
= readl(&devcfg_base
->int_sts
);
475 debug("%s: FPGA config done\n", __func__
);
478 zynq_slcr_devcfg_enable();
484 static int zynq_dump(xilinx_desc
*desc
, const void *buf
, size_t bsize
)
489 struct xilinx_fpga_op zynq_op
= {
491 #if defined(CONFIG_CMD_FPGA_LOADFS)
492 .loadfs
= zynq_loadfs
,