drivers/fpga/zynqpl.c

   1 /*
   2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
   3  *
   4  * (C) Copyright 2012
   5  * Joe Hershberger <joe.hershberger@ni.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <zynqpl.h>
  13 #include <linux/sizes.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 #define DEVCFG_CTRL_PCFG_PROG_B         0x40000000
  18 #define DEVCFG_ISR_FATAL_ERROR_MASK     0x00740040
  19 #define DEVCFG_ISR_ERROR_FLAGS_MASK     0x00340840
  20 #define DEVCFG_ISR_RX_FIFO_OV           0x00040000
  21 #define DEVCFG_ISR_DMA_DONE             0x00002000
  22 #define DEVCFG_ISR_PCFG_DONE            0x00000004
  23 #define DEVCFG_STATUS_DMA_CMD_Q_F       0x80000000
  24 #define DEVCFG_STATUS_DMA_CMD_Q_E       0x40000000
  25 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  26 #define DEVCFG_STATUS_PCFG_INIT         0x00000010
  27 #define DEVCFG_MCTRL_PCAP_LPBK          0x00000010
  28 #define DEVCFG_MCTRL_RFIFO_FLUSH        0x00000002
  29 #define DEVCFG_MCTRL_WFIFO_FLUSH        0x00000001
  30
  31 #ifndef CONFIG_SYS_FPGA_WAIT
  32 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100  /* 10 ms */
  33 #endif
  34
  35 #ifndef CONFIG_SYS_FPGA_PROG_TIME
  36 #define CONFIG_SYS_FPGA_PROG_TIME       (CONFIG_SYS_HZ * 4) /* 4 s */
  37 #endif
  38
  39 int zynq_info(Xilinx_desc *desc)
  40 {
  41         return FPGA_SUCCESS;
  42 }
  43
  44 #define DUMMY_WORD      0xffffffff
  45
  46 /* Xilinx binary format header */
  47 static const u32 bin_format[] = {
  48         DUMMY_WORD, /* Dummy words */
  49         DUMMY_WORD,
  50         DUMMY_WORD,
  51         DUMMY_WORD,
  52         DUMMY_WORD,
  53         DUMMY_WORD,
  54         DUMMY_WORD,
  55         DUMMY_WORD,
  56         0x000000bb, /* Sync word */
  57         0x11220044, /* Sync word */
  58         DUMMY_WORD,
  59         DUMMY_WORD,
  60         0xaa995566, /* Sync word */
  61 };
  62
  63 #define SWAP_NO         1
  64 #define SWAP_DONE       2
  65
  66 /*
  67  * Load the whole word from unaligned buffer
  68  * Keep in your mind that it is byte loading on little-endian system
  69  */
  70 static u32 load_word(const void *buf, u32 swap)
  71 {
  72         u32 word = 0;
  73         u8 *bitc = (u8 *)buf;
  74         int p;
  75
  76         if (swap == SWAP_NO) {
  77                 for (p = 0; p < 4; p++) {
  78                         word <<= 8;
  79                         word |= bitc[p];
  80                 }
  81         } else {
  82                 for (p = 3; p >= 0; p--) {
  83                         word <<= 8;
  84                         word |= bitc[p];
  85                 }
  86         }
  87
  88         return word;
  89 }
  90
  91 static u32 check_header(const void *buf)
  92 {
  93         u32 i, pattern;
  94         int swap = SWAP_NO;
  95         u32 *test = (u32 *)buf;
  96
  97         debug("%s: Let's check bitstream header\n", __func__);
  98
  99         /* Checking that passing bin is not a bitstream */
 100         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
 101                 pattern = load_word(&test[i], swap);
 102
 103                 /*
 104                  * Bitstreams in binary format are swapped
 105                  * compare to regular bistream.
 106                  * Do not swap dummy word but if swap is done assume
 107                  * that parsing buffer is binary format
 108                  */
 109                 if ((__swab32(pattern) != DUMMY_WORD) &&
 110                     (__swab32(pattern) == bin_format[i])) {
 111                         pattern = __swab32(pattern);
 112                         swap = SWAP_DONE;
 113                         debug("%s: data swapped - let's swap\n", __func__);
 114                 }
 115
 116                 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
 117                       (u32)&test[i], pattern, bin_format[i]);
 118                 if (pattern != bin_format[i]) {
 119                         debug("%s: Bitstream is not recognized\n", __func__);
 120                         return 0;
 121                 }
 122         }
 123         debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
 124               (u32)buf, swap == SWAP_NO ? "without" : "with");
 125
 126         return swap;
 127 }
 128
 129 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 130 {
 131         u32 word, p = 0; /* possition */
 132
 133         /* Because buf doesn't need to be aligned let's read it by chars */
 134         for (p = 0; p < bsize; p++) {
 135                 word = load_word(&buf[p], SWAP_NO);
 136                 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
 137
 138                 /* Find the first bitstream dummy word */
 139                 if (word == DUMMY_WORD) {
 140                         debug("%s: Found dummy word at position %x/%x\n",
 141                               __func__, p, (u32)&buf[p]);
 142                         *swap = check_header(&buf[p]);
 143                         if (*swap) {
 144                                 /* FIXME add full bitstream checking here */
 145                                 return &buf[p];
 146                         }
 147                 }
 148                 /* Loop can be huge - support CTRL + C */
 149                 if (ctrlc())
 150                         return 0;
 151         }
 152         return 0;
 153 }
 154
 155
 156 int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 157 {
 158         unsigned long ts; /* Timestamp */
 159         u32 partialbit = 0;
 160         u32 i, control, isr_status, status, swap, diff;
 161         u32 *buf_start;
 162
 163         /* Detect if we are going working with partial or full bitstream */
 164         if (bsize != desc->size) {
 165                 printf("%s: Working with partial bitstream\n", __func__);
 166                 partialbit = 1;
 167         }
 168
 169         buf_start = check_data((u8 *)buf, bsize, &swap);
 170         if (!buf_start)
 171                 return FPGA_FAIL;
 172
 173         /* Check if data is postpone from start */
 174         diff = (u32)buf_start - (u32)buf;
 175         if (diff) {
 176                 printf("%s: Bitstream is not validated yet (diff %x)\n",
 177                        __func__, diff);
 178                 return FPGA_FAIL;
 179         }
 180
 181         if ((u32)buf < SZ_1M) {
 182                 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
 183                        __func__, (u32)buf);
 184                 return FPGA_FAIL;
 185         }
 186
 187         if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
 188                 u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
 189
 190                 /*
 191                  * This might be dangerous but permits to flash if
 192                  * ARCH_DMA_MINALIGN is greater than header size
 193                  */
 194                 if (new_buf > buf_start) {
 195                         debug("%s: Aligned buffer is after buffer start\n",
 196                               __func__);
 197                         new_buf -= ARCH_DMA_MINALIGN;
 198                 }
 199
 200                 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 201                        (u32)buf_start, (u32)new_buf, swap);
 202
 203                 for (i = 0; i < (bsize/4); i++)
 204                         new_buf[i] = load_word(&buf_start[i], swap);
 205
 206                 swap = SWAP_DONE;
 207                 buf = new_buf;
 208         } else if (swap != SWAP_DONE) {
 209                 /* For bitstream which are aligned */
 210                 u32 *new_buf = (u32 *)buf;
 211
 212                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 213                        swap);
 214
 215                 for (i = 0; i < (bsize/4); i++)
 216                         new_buf[i] = load_word(&buf_start[i], swap);
 217
 218                 swap = SWAP_DONE;
 219         }
 220
 221         /* Clear loopback bit */
 222         clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 223
 224         if (!partialbit) {
 225                 zynq_slcr_devcfg_disable();
 226
 227                 /* Setting PCFG_PROG_B signal to high */
 228                 control = readl(&devcfg_base->ctrl);
 229                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 230                 /* Setting PCFG_PROG_B signal to low */
 231                 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 232
 233                 /* Polling the PCAP_INIT status for Reset */
 234                 ts = get_timer(0);
 235                 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
 236                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 237                                 printf("%s: Timeout wait for INIT to clear\n",
 238                                        __func__);
 239                                 return FPGA_FAIL;
 240                         }
 241                 }
 242
 243                 /* Setting PCFG_PROG_B signal to high */
 244                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 245
 246                 /* Polling the PCAP_INIT status for Set */
 247                 ts = get_timer(0);
 248                 while (!(readl(&devcfg_base->status) &
 249                         DEVCFG_STATUS_PCFG_INIT)) {
 250                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 251                                 printf("%s: Timeout wait for INIT to set\n",
 252                                        __func__);
 253                                 return FPGA_FAIL;
 254                         }
 255                 }
 256         }
 257
 258         isr_status = readl(&devcfg_base->int_sts);
 259
 260         /* Clear it all, so if Boot ROM comes back, it can proceed */
 261         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 262
 263         if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
 264                 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
 265
 266                 /* If RX FIFO overflow, need to flush RX FIFO first */
 267                 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
 268                         writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
 269                         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 270                 }
 271                 return FPGA_FAIL;
 272         }
 273
 274         status = readl(&devcfg_base->status);
 275
 276         debug("%s: Status = 0x%08X\n", __func__, status);
 277
 278         if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
 279                 debug("%s: Error: device busy\n", __func__);
 280                 return FPGA_FAIL;
 281         }
 282
 283         debug("%s: Device ready\n", __func__);
 284
 285         if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
 286                 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
 287                         /* Error state, transfer cannot occur */
 288                         debug("%s: ISR indicates error\n", __func__);
 289                         return FPGA_FAIL;
 290                 } else {
 291                         /* Clear out the status */
 292                         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 293                 }
 294         }
 295
 296         if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
 297                 /* Clear the count of completed DMA transfers */
 298                 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
 299         }
 300
 301         debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 302         debug("%s: Size = %zu\n", __func__, bsize);
 303
 304         /* flush(clean & invalidate) d-cache range buf */
 305         flush_dcache_range((u32)buf, (u32)buf +
 306                            roundup(bsize, ARCH_DMA_MINALIGN));
 307
 308         /* Set up the transfer */
 309         writel((u32)buf | 1, &devcfg_base->dma_src_addr);
 310         writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
 311         writel(bsize >> 2, &devcfg_base->dma_src_len);
 312         writel(0, &devcfg_base->dma_dst_len);
 313
 314         isr_status = readl(&devcfg_base->int_sts);
 315
 316         /* Polling the PCAP_INIT status for Set */
 317         ts = get_timer(0);
 318         while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
 319                 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
 320                         debug("%s: Error: isr = 0x%08X\n", __func__,
 321                               isr_status);
 322                         debug("%s: Write count = 0x%08X\n", __func__,
 323                               readl(&devcfg_base->write_count));
 324                         debug("%s: Read count = 0x%08X\n", __func__,
 325                               readl(&devcfg_base->read_count));
 326
 327                         return FPGA_FAIL;
 328                 }
 329                 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
 330                         printf("%s: Timeout wait for DMA to complete\n",
 331                                __func__);
 332                         return FPGA_FAIL;
 333                 }
 334                 isr_status = readl(&devcfg_base->int_sts);
 335         }
 336
 337         debug("%s: DMA transfer is done\n", __func__);
 338
 339         /* Check FPGA configuration completion */
 340         ts = get_timer(0);
 341         while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
 342                 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 343                         printf("%s: Timeout wait for FPGA to config\n",
 344                                __func__);
 345                         return FPGA_FAIL;
 346                 }
 347                 isr_status = readl(&devcfg_base->int_sts);
 348         }
 349
 350         debug("%s: FPGA config done\n", __func__);
 351
 352         /* Clear out the DMA status */
 353         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 354
 355         if (!partialbit)
 356                 zynq_slcr_devcfg_enable();
 357
 358         return FPGA_SUCCESS;
 359 }
 360
 361 int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 362 {
 363         return FPGA_FAIL;
 364 }